KR101099866B1 - Nonvolatile semiconductor memory device and method of data read therein - Google Patents

Abstract

The nonvolatile semiconductor memory device includes a memory cell array having a plurality of memory strings each including a plurality of memory cells connected in series, a memory cell array, and a selection gate line for selecting the memory string. And a control circuit for performing a read operation of reading data from memory cells included in the selected memory string from among the plurality of memory strings. During a read operation, the control circuit applies a first voltage to the gate of at least one memory cell of the non-selected memory string that is not subject to the read operation, and applies a first voltage to the gate of the other memory cell of the non-selected memory string. Configured to apply two voltages.

Description

Nonvolatile semiconductor memory device and method of reading data therein {NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA READ THEREIN}

Cross Reference to Related Application

This application is based on a previous Japanese Patent Application No. 2009-216403 filed on September 18, 2009, and claims priority from this Japanese patent application, the entire contents of which are incorporated herein by reference.

The present invention relates to an electrically rewritable nonvolatile semiconductor memory device and a method of reading data therein.

As miniaturization techniques reach their limits, much is expected from stacking of memory cells as a way to improve the bit density in nonvolatile semiconductor memory devices such as NAND flash memories. As one example, a stacked NAND flash memory constructed by a memory cell using a vertical transistor is proposed (see, for example, Japanese Unexamined Patent Application Publication No. 2007-266143). The operation including the read operation of the stacked NAND flash memory is almost the same as that of the conventional planar NAND flash memory. Therefore, when attempting to increase the capacity of a stacked NAND flash memory, it is important that during a read, leakage current from a non-selected memory string in which a read operation is not performed is suppressed.

Conventionally, a NAND flash memory suppresses leakage current from an unselected memory string by applying a ground potential or a negative potential to the gate of the select transistor connected to the unselected memory string. Moreover, conventionally, NAND flash memory solves the problem described above by reducing the number of memory strings connected to one bit line. In recent years, in addition to the conventional art, there is a need to further increase the suppression of leakage current.

According to a first embodiment of the present invention, a nonvolatile semiconductor memory device includes a memory cell array having a plurality of memory strings each including a plurality of memory cells connected in series; A select gate line disposed on the memory string, the select gate line for selecting the memory string; And a control circuit for performing a read operation of reading data from memory cells included in the selected memory string from among the plurality of memory strings, each memory string having a columnar portion extending in a direction perpendicular to the substrate. A semiconductor layer having a function as a body of the memory cell; A charge storage layer surrounding the columnar portion and holding data by storing charge; An interlayer insulating layer formed to surround the columnar portion via the charge storage layer and extend in parallel with the substrate; And formed around the columnar portion via the charge storage layer and extending in parallel to the substrate, stacked through the interlayer insulating layer, and sharing the selected memory string and the non-selected memory string that are not subject to a read operation. And a plurality of word line conductive layers that function as gates of the memory cells, wherein the control circuit applies a first voltage to the gates of at least one of the non-selected memory strings during a read operation, And a second voltage lower than the first voltage to the gate of another memory cell.

According to a second embodiment of the present invention, a nonvolatile semiconductor memory device includes a memory cell array having a plurality of memory strings each including a plurality of memory cells connected in series; A select gate line disposed on the memory string, the select gate line for selecting the memory string; And a control circuit configured to execute a read operation of reading data from a memory cell included in the selected memory string among the plurality of memory strings, each memory string having a columnar portion extending in a direction perpendicular to the substrate, A semiconductor layer functioning as a body of the memory cell; A charge storage layer surrounding the columnar portion and holding data by storing charge; An interlayer insulating layer formed to surround the columnar portion via the charge storage layer and extend in parallel with the substrate; It is formed to surround the columnar portion via the charge storage layer, and extend in parallel to the substrate, and is laminated via the interlayer insulating layer, and to share the selected memory string and the non-selected memory string that are not subject to the read operation. A plurality of word line conductive layers functioning as gates of memory cells; A connection portion connecting the lower ends of the pair of columnar portions in the semiconductor layer to function as a body of the back gate transistor; And a back gate conductive layer surrounding the connection portion via the charge storage layer, extending parallel to the substrate, and functioning as a gate of the back gate transistor, wherein the control circuit includes at least one of the unselected memory strings during a read operation; The first voltage is applied to the gate of one memory cell and the second voltage lower than the first voltage is applied to the gate of the other memory cell of the non-selected memory string.

According to a third embodiment of the present invention, a method of reading data in a nonvolatile semiconductor memory device, comprising: a memory cell array having a plurality of memory strings each including a plurality of memory cells connected in series; A semiconductor layer disposed on the memory string, the select gate line selecting a memory string, each memory string having a columnar portion extending in a direction perpendicular to the substrate, the semiconductor layer functioning as a body of the memory cell; A charge storage layer surrounding the columnar portion and holding data by storing charge; An interlayer insulating layer formed to surround the columnar portion via the charge storage layer and extend in parallel with the substrate; And formed around the columnar portion via the charge storage layer and extending in parallel to the substrate, stacked through the interlayer insulating layer, and sharing the selected memory string and the non-selected memory string that are not subject to a read operation. And a plurality of word line conductive layers functioning as gates of the memory cells, during execution of a read operation of reading data from a memory cell included in the selected memory string from among the plurality of memory strings. And applying a first voltage to a gate of one memory cell and applying a second voltage lower than the first voltage to a gate of another memory cell of the non-selected memory string.

During a read operation in the nonvolatile semiconductor memory device, the current flowing from the bit line to the source line through the unselected memory string can be suppressed.

1 is a circuit diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.
2 is a schematic perspective view of a memory cell array AR1.
3 is an equivalent circuit diagram of a memory cell array AR1.
4 is a partial cross-sectional view of the memory cell array AR1.
5 is a circuit diagram showing a specific configuration of the control circuit AR2.
6 is a circuit diagram showing a boost circuit 12a.
7A is a timing chart showing the operation of the boost circuit 12a.
7B is a timing chart showing the operation of the boost circuit 12a.
8 is a circuit diagram showing a word line driver circuit 13a.
9 is a circuit diagram showing a back gate line driving circuit 14.
10 is a circuit diagram showing a selection gate line driving circuit 15a.
11 is a circuit diagram showing a source line driver circuit 16.
12 is a circuit diagram showing a sense amplifier circuit 17. FIG.
13 is a timing chart showing a read operation according to the first embodiment.
14 is a schematic diagram of a read operation according to the first embodiment;
Fig. 15 is a timing chart showing a write operation according to the first embodiment.
16 is a timing chart showing an erase operation according to the first embodiment.
17 is a timing chart showing a read operation according to the second embodiment.
18 is a schematic diagram of a read operation according to the second embodiment;
Fig. 19 is a block diagram showing a word line driver circuit 13a according to the third embodiment.
20 is a partial circuit diagram showing row decoder circuits 19a and 19b according to the third embodiment.
21 is a timing chart showing a read operation according to the third embodiment;
22 is a schematic diagram of a read operation according to the third embodiment;
Fig. 23 is a circuit diagram showing a word line driver circuit 13a according to the fourth embodiment.
24 is a circuit diagram showing a back gate line driving circuit 14 according to the fourth embodiment.
25 is a timing chart showing a read operation according to the fourth embodiment.
26 is a schematic diagram of a read operation according to the fourth embodiment;

[First Embodiment]

[Configuration]

First, the entire configuration of a nonvolatile semiconductor memory device according to the first embodiment will be described with reference to FIG. 1 is a circuit diagram of a nonvolatile semiconductor memory device according to the first embodiment.

As shown in FIG. 1, the nonvolatile semiconductor memory device according to the first embodiment includes a memory cell array AR1 and a control circuit AR2 provided around the memory cell array AR1.

As shown in Fig. 1, the memory cell array AR1 is configured to have a plurality of memory strings MS each having electrically rewritable memory transistors MTr1-MTr8 (memory cells) connected in series. The control circuit AR2 is constituted by various kinds of control circuits configured to control the voltage and the like applied to the gates of the memory transistors MTr1 to MTr8. The control circuit AR2 executes a write operation of writing data into the memory transistor MTr, an erase operation of erasing data in the memory transistor MTr, and a read operation of reading data from the memory transistor MTr. During the write operation and the read operation, the voltage applied to the selected memory string MS is almost similar to the conventional stacked flash memory.

However, during the read operation, the control circuit AR2 applies the read pass voltage Vread to the gate of at least one of the memory transistors MTr included in the unselected memory string MS, and applies it to the other memory transistor MTr contained in the unselected memory string MS. The ground potential Vss (0 V) is applied. The read pass voltage Vread is equal to the voltage applied to the gate of the unselected memory transistor MTr in the selected memory string MS, and causes the memory transistor MTr to be in a conductive state regardless of the data stored in the memory transistor MTr. The potential of the body of the memory transistor MTr to which the read pass voltage Vread is applied is proportional to the amount of the inversion layer formed so that the ground voltage Vss is lower than the potential of the body of the other memory transistor MTr applied to the gate. This kind of potential difference allows a well-type potential to be formed in the unselected memory string MS, so that leakage current in the unselected memory string MS can be suppressed.

As shown in FIG. 1, memory cell array AR1 includes m columns of memory blocks MB. Each memory block MB includes n rows and 2 columns of memory units MU. The memory unit MU includes a memory string MS, a source side select transistor SSTr connected to one end of the memory string MS, and a drain side select transistor SDTr connected to the other end of the memory string MS. Note that in the example shown in FIG. 1, the first column of the memory unit MU is indicated by (1), and the second column of the memory unit MU is indicated by (2). The bit line BL and the source line SL are shared by the m columns of the memory block MB.

As shown in Fig. 2, the memory cell array AR1 is configured to have electrical data-storage memory transistors MTr arranged in a three-dimensional matrix. That is, not only are arranged in a matrix in the horizontal direction, but the memory transistors MTr are also arranged in the stacking direction (the direction perpendicular to the substrate). A plurality of memory transistors MTr aligned in the stacking direction are connected in series to constitute a memory string MS. The source side select transistor SSTr and drain side select transistor SDTr, which are selectively brought into a conductive state, are connected to both ends of the memory string MS, respectively. The memory strings MS are arranged long in the stacking direction. Note that the detailed laminate structure is described later.

Next, the circuit configuration of the memory cell array AR1 is described in detail with reference to FIG. 3 is an equivalent circuit diagram of the memory cell array AR1.

As shown in FIG. 3, the memory cell array AR1 includes a plurality of bit lines BL and a plurality of memory blocks MB. The bit lines BL extend in the column direction and are formed of stripes having a predetermined spacing in the row direction. The memory blocks MB are repeatedly provided in the column direction at predetermined intervals.

As shown in FIG. 3, the memory block MB includes a plurality of memory units MUs arranged in a matrix in the row direction and the column direction. Multiple memory units MUs are provided to be commonly connected to one bit line BL. The memory unit MU includes a memory string MS, a source side select transistor SSTr, and a drain side select transistor SDTr. The memory units MUs adjacent to each other in the column direction are formed so that their configuration is symmetrical to each other in the column direction. The memory units MU are arranged in a matrix in the row direction and the column direction.

The memory string MS is constituted by memory transistors MTr1-MTr8 and back gate transistor BTr connected in series. The memory transistors MTr1-MTr4 are connected in series in the stacking direction. The memory transistors MTr5-MTr8 are similarly connected in series in the stacking direction. Memory transistors MTr1-MTr8 store information by trapping charges in the charge storage layer. The back gate transistor BTr is connected between the lowermost memory transistors MTr4 and MTr5. Therefore, the memory transistors MTr1-MTr8 and the back gate transistor BTr are connected in a U-shaped cross section in the column direction. The source of the drain side select transistor SDTr is connected to one end of the memory string MS (drain of the memory transistor MTr1). The drain of the source side select transistor SSTr is connected to the other end of the memory string MS (the source of the memory transistor MTr8).

The gates of the memory transistors Mtr1 in the memory units MU arranged in line in the row direction are commonly connected to the word line WL1 extending in the row direction. Similarly, the gates of the memory transistors MTr2-MTr8 each arranged in a row direction are commonly connected to each word line WL2-WL8 extending in the row direction. Note that two memory strings MS adjacent in the column direction also share the word lines WL1-WL8. Moreover, the gates of the back gate transistors BTr arranged in a matrix in the row direction and the column direction are commonly connected to the back gate line BG.

Each gate of the drain side selection transistor SDTr in the memory units MU arranged in a row direction is commonly connected to the drain side selection gate line SGD extending in the row direction. Moreover, the drains of the drain side select transistors SDTr arranged in the column direction are commonly connected to the bit lines BL extending in the column direction.

Each gate of the source side selection transistor SSTr in the memory units MU arranged in a row direction is commonly connected to a source side selection gate line SGS extending in the row direction. In addition, the sources of the source-side select transistors SSTr of the memory unit MU pairs adjacent to each other in the column direction arranged in a row direction are commonly connected to the source lines SL extending in the row direction.

Next, the laminated structure of the nonvolatile semiconductor memory device according to the first embodiment will be described with reference to FIG. 4 is a partial cross-sectional view of the memory cell array AR1.

As shown in FIG. 4, the memory cell array AR1 includes a back gate transistor layer 20, a memory transistor layer 30, a select transistor layer 40, and a wiring layer 50 on the substrate 10. The back gate transistor layer 20 functions as a back gate transistor BTr. The memory transistor layer 30 functions as a memory transistor MTr1-MTr8 (memory string MS). The select transistor layer 40 functions as a source side select transistor SSTr and a drain side select transistor SDTr. The wiring layer 50 functions as a source line SL and a bit line BL.

The back gate transistor layer 20 includes a back gate conductive layer 21, as shown in FIG. 4. The back gate conductive layer 21 functions as a back gate line BG. In addition, the back gate conductive layer 21 functions as a back gate transistor BTr.

The back gate conductive layer 21 is formed to extend in two dimensions in the row direction and the column direction parallel to the substrate. The back gate conductive layer 21 is divided into memory blocks MB. The back gate conductive layer 21 is made of polysilicon (poly-Si).

The back gate transistor layer 20 includes a back gate hole 22, as shown in FIG. The back gate hole 22 is formed by digging out the back gate conductive layer 21. The back gate hole 22 is formed in a generally rectangular shape that is long in the column direction when viewed from the top. The back gate holes 22 are formed in a matrix in the row direction and the column direction.

The memory transistor layer 30 is formed on the top surface of the back gate transistor layer 20, as shown in FIG. 4. The memory transistor layer 30 includes word line conductive layers 31a-31d. Word line conductive layers 31a-31d function as word lines WL1-WL8. In addition, the word line conductive layers 31a-31d function as gates of the memory transistors MTr1-MTr8.

The word line conductive layers 31a to 31d are stacked with interlayer insulating layers (not shown) inserted therebetween. The word line conductive layers 31a to 31d are formed to extend in the row direction at predetermined intervals in the column direction along the predetermined region. The word line conductive layers 31a-31d are made of polysilicon (poly-Si).

The memory transistor layer 30 includes memory holes 32, as shown in FIG. 4. The memory holes 32 are formed through the word line conductive layers 31a-31d. The memory holes 32 are formed in line with the end portions of the back gate holes 22 in the column direction.

In addition, the back gate transistor layer 20 and the memory transistor layer 30 are formed of a block insulating layer 33a, a charge storage layer 33b, a tunnel insulating layer 33c, and a U-shaped semiconductor layer, as shown in FIG. (34). The block insulating layer 33a, the charge storage layer 33b, the tunnel insulating layer 33c, and the U-shaped semiconductor layer 34 function as MONOS of the memory transistors MTr1-MTr8. The charge storage layer 33b holds data by storing charge. U-shaped semiconductor layer 34 functions as a body of memory string MS.

As shown in FIG. 4, the block insulating layer 33a is formed to a predetermined thickness on the sidewalls of the block gate hole 22 and the memory hole 32. The charge storage layer 33b is formed to a predetermined thickness on the side of the block insulating layer 33a. The tunnel insulation layer 33c is formed to a predetermined thickness on the side of the charge storage layer 33b. The U-shaped semiconductor layer 34 is formed in contact with the side surface of the tunnel insulation layer 33c. The U-shaped semiconductor layer 34 is formed to fill the back gate hole 22 and the memory hole 32. The U-shaped semiconductor layer 34 is formed in a U shape when viewed in the row direction. U-shaped semiconductor layer 34 comprises a pair of columnar portions 34a extending in a direction perpendicular to substrate 10 and a connecting portion 34b configured to connect the lower ends of the pair of columnar portions 34a. It includes.

The block insulating layer 33a and the tunnel insulating layer 33c are made of SiO ₂ (silicon oxide). The charge storage layer 33b is made of silicon nitride (SiN). The U-shaped semiconductor layer 34 is made of polysilicon (poly-Si).

In other words, the above-described configuration of the back gate transistor layer 20 is formed so that the tunnel insulation layer 33c surrounds the connecting portion 34b. The back gate conductive layer 21 is formed to surround the connecting portion 34b.

In other words, the above-described configuration of the memory transistor layer 30 is formed so that the tunnel insulation layer 33c surrounds the columnar portion 34a. The charge storage layer 33b is formed to surround the tunnel insulation layer 33c. The block insulating layer 33a is formed to surround the charge storage layer 33b. The word line conductive layers 31a-31d are formed to surround the block insulating layer 33a and the columnar portion 34a.

The select transistor layer 40 includes a source side conductive layer 41a and a drain side conductive layer 41b, as shown in FIG. The source side conductive layer 41a functions as a source side select gate line SGS. In addition, the source side conductive layer 41a functions as a gate of the source side select transistor SSTr. The drain side conductive layer 41b functions as the drain side select gate line SGD. In addition, the drain side conductive layer 41b functions as a gate of the drain side select transistor SDTr.

The source side conductive layer 41a and the drain side conductive layer 41b are formed in stripes extending in the row direction at predetermined intervals in the column direction. The pair of source side conductive layers 41a and the pair of drain side conductive layers 41b are alternately arranged in the column direction. The source side conductive layer 41a is formed in the upper layer of one of the columnar portions 34a constituting the U-shaped semiconductor layer 34, and the drain side conductive layer 41b forms the U-shaped semiconductor layer 34. It is formed in the upper layer of the other one of the circumferential portions 34a constituting. The source side conductive layer 41a and the drain side conductive layer 41b are made of polysilicon (poly-Si).

The select transistor layer 40 includes a source side hole 42a and a drain side hole 42b, as shown in FIG. The source side hole 42a is formed to penetrate the source side conductive layer 41a. The source side hole 42a is formed at a position aligned with the memory hole 32. The drain side hole 42b is formed to penetrate the drain side conductive layer 41b. The drain side hole 42b is formed at a position aligned with the memory hole 32.

As shown in FIG. 4, the select transistor layer 40 includes a source side gate insulating layer 43a, a source side columnar semiconductor layer 44a, a drain side gate insulating layer 43b and a drain side columnar semiconductor layer ( 44b). The source side columnar semiconductor layer 44a functions as a body of the source side selection transistor SSTr. The drain side columnar semiconductor layer 44b functions as a body of the drain side select transistor SDTr.

The source side gate insulating layer 43a is formed on the sidewall of the source side hole 42a. The source side columnar semiconductor layer 44a is formed in a columnar shape to extend in a direction perpendicular to the substrate 10 and to be in contact with the source side gate insulating layer 43a. The drain side gate insulating layer 43b is formed on the sidewall of the drain side hole 42b. The drain side columnar semiconductor layer 44b is formed in a columnar shape to extend in a direction perpendicular to the substrate 10 and to come into contact with the drain side gate insulating layer 43b.

The source side gate insulating layer 43a and the drain side gate insulating layer 43b are made of SiO ₂ (silicon oxide). The source side columnar semiconductor layer 44a and the drain side columnar semiconductor layer 44b are made of polysilicon (poly-Si).

In other words, the above-described configuration of the select transistor layer 40 is formed so as to surround the source side columnar semiconductor layer 44a. The source side conductive layer 41a is formed to surround the source side gate insulating layer 43a and the source side columnar semiconductor layer 44a. The drain side gate insulating layer 43b is formed to surround the drain side columnar semiconductor layer 44b. The drain side conductive layer 41b is formed to surround the drain side gate insulating layer 43b and the drain side columnar semiconductor layer 44b.

The wiring layer 50 is formed on the top layer of the select transistor layer 40, as shown in FIG. The wiring layer 50 includes a source line layer 51, a plug layer 52, and a bit line layer 53. The source line layer 51 functions as a source line SL. The bit line layer 53 functions as a bit line BL.

The source line layer 51 is formed in a plate-like shape extending in the row direction. The source line layer 51 is formed in contact with the top surface of the pair of source side columnar semiconductor layers 44a adjacent to each other in the column direction. The plug layer 52 extends in a direction perpendicular to the substrate 10 and is formed to be in contact with the top surface of the drain side columnar semiconductor layer 44b. The bit line layer 53 is formed of streaks extending in the column direction and having a predetermined interval in the row direction. The bit line layer 53 is formed to be in contact with the top surface of the plug layer 52. The source line layer 51, plug layer 52 and bit line layer 53 are made of a metal such as tungsten (W).

Next, a specific configuration of the control circuit AR2 is described with reference to FIG. 5 is a circuit diagram showing a specific configuration of the control circuit AR2. As shown in Fig. 5, the control circuit AR2 includes the address decoder circuit 11, the boost circuits 12a-12d, the word line driving circuits 13a and 13b, the back gate line driving circuit 14, and the selection gate line driving. Circuits 15a and 15b, source line drive circuit 16, sense amplifier circuit (S / A) 17, sequencer 18 and row decoder circuits 19a and 19b.

As shown in Fig. 5, the address decoder circuit 11 outputs the signal BAD to the row decoder circuits 19a and 19b, and outputs the signal CAD to the sense amplifier circuit 17. The signal BAD is for specifying a memory block MB (block address). The signal CAD is for specifying a column (column address) in the memory block MB.

The boost circuits 12a-12d generate a boost voltage having a voltage stepped up from the power supply voltage. As shown in FIG. 5, the boost circuit 12a transfers the boost voltage to the word line driver circuits 13a and 13b. The boost circuit 12b transfers the boost voltage to the back gate line driver circuit 14. The boost circuit 12c outputs a boost voltage to the source line driver circuit 16. The boost circuit 12d outputs the signal RDEC including the boost voltage to the row decoder circuits 19a and 19b.

As shown in Fig. 5, the word line driving circuit 13a outputs signals VCG1-VCG4 and signals VCGOFF-1 and VCGOFF4. The word line driver circuit 13b outputs signals VCG5-VCG8 and signals VCGOFF5-VCGOFF8. Signals VCG1-VCG4 are used to drive word line WL1-WL4 in selected memory block MB <i>, and signals VCGOFF1-VCGOFF4 are used to drive word line WL1-WL4 in unselected memory block MB <x>. The signal VCG5-VCG8 is used when driving the word line WL5-WL8 in the selected memory block MB <i>, and the signal VCGOFF5-VCGOFF8 is used when driving the word line WL5-WL8 in the unselected memory block MB <x>. Note that all memory strings MS in unselected memory block MB <x> are unselected memory strings MS.

As shown in Fig. 5, the back gate line driving circuit 14 outputs the signal VBG and the signal VBGOFF. The signal VBG is used when driving the back gate line BG in the selected memory block MB <i>, and the signal VBGOFF is used when driving the back gate line BG in the unselected memory block MB <x>.

As shown in Fig. 5, the selection gate line driving circuit 15a outputs the signal VSGS2, the signal VSGD1, and the signal VSGOFF. The selection gate line driver circuit 15b outputs the signal VSGS1, the signal VSGD2, and the signal VSGOFF. The signal VSGS1 and the signal VSGS2 are used when driving the first column source side select gate line SGS and the second column source side select gate line SGS in the selection memory block MB <i>, respectively. The signals VSGD1 and VSGD2 are used to drive the first column drain side select gate line SGD and the second column drain side select gate line SGD in the selection memory block MB <i>, respectively. The signal VSGOFF is used when driving the source side select gate line SGS and the drain side select gate line SGD in the unselected memory block MB <x>.

As shown in Fig. 5, the source line driving circuit 16 outputs the signal VSL. The signal VSL is used when driving the source line SL.

As shown in Fig. 5, the sense amplifier circuit 17 outputs the signal VBL in accordance with the column address signal CAD, thereby charging the predetermined bit line BL to a predetermined potential, and then changing the potential of the bit line BL. Based on the determination, the retention data of the memory transistor MTr in the memory string MS is determined. In addition, the sense amplifier circuit 17 outputs a signal VBL suitable for the write data to the predetermined bit line BL in accordance with the column address CAD.

As shown in Fig. 5, the sequencer 18 controls the circuits 11-17 described above by supplying control signals to the circuits 11-17 described above.

As shown in Fig. 5, row decoder circuits 19a and 19b are provided one each in one of the memory blocks MB. The row decoder circuit 19a is provided on one end side in the row direction of the memory block MB. The row decoder circuit 19b is provided on the other end side in the row direction of the memory block MB.

The row decoder circuit 19a is based on the signals BAD, the signals VCG1-VCG4 and the signals VCGOFF1-VCGOFF4, and the signals VCG1 <i> -VCG4 <i> (or signals VCG1 <x> -VCG4) to the gates of the memory transistors MTr1-MTr4. <x>). In addition, the row decoder circuit 19a may optionally select a signal VSGS2 <i> (or a signal VSGS2 <x) at a gate of the source-side selection transistor SSTr in the second column memory unit MU based on the signal BAD, the signal VSGS2 and the signal VSGOFF. Enter>). Further, the row decoder circuit 19a may optionally select a signal VSGD1 <i> (or a signal VSGD1 <x) at a gate of the drain side select transistor SDTr in the first column memory unit MU based on the signal BAD, the signal VSGD1, and the signal VSGOFF. Enter>).

The row decoder circuit 19a includes a NAND circuit 19aa, a NOT circuit 19ab, a voltage conversion circuit 19ac, a first transfer transistor Tra1-Tra6, and a second transfer transistor Trb1-Trb6. The voltage conversion circuit 19ac generates a signal VSELa <i> (or VSELa <x>) based on the signal BAD received through the NAND circuit 19aa and the NOT circuit 19ab, and the signal RDEC, and this signal VSELa <i> (or VSELa <x>) is output to the gates of the first transfer transistors Tra1-Tra6. In addition, the voltage conversion circuit 19ac generates the signal VbSELa <i> (or VbSELa <x>) based on the signal BAD and the signal RDEC, and transmits the signal VbSELa <i> (or VbSELa <x>) to the second transmission. It outputs to the gates of the transistors Trb1-Trb6.

The first transfer transistor Tra1-Tra4 is connected between the word line driver circuit 13a and each word line WL1-WL4. The first transfer transistors Tra1-Tra4 output signals VCG1 <i> -VCG4 <i> to the word lines WL1-WL4 based on the signals VCG1-VCG4 and VSELa <i>. The first transfer transistor Tra5 is connected between the selection gate line driving circuit 15a and the source side selection gate line SGS in the second column memory unit MU. The first transfer transistor Tra5 outputs the signal VSGS2 <i> to the source side select gate line SGS in the second column memory unit MU based on the signal VSGS2 and the signal VSELa <i>. The first transfer transistor Tra6 is connected between the selection gate line driving circuit 15a and the drain side selection gate line SGD in the first column memory unit MU. The first transfer transistor Tra6 outputs the signal VSGD1 <i> to the drain side select gate line SGD in the first column memory unit MU based on the signal VSGD1 and the signal VSELa <i>.

The second transfer transistors Trb1-Trb4 are connected between the word line driver circuit 13a and each word line WL1-WL4. The second transfer transistor Trb1-Trb4 outputs the signals VCG1 <x> -VCG4 <x> to the word lines WL1-WL4 based on the signals VCGOFF1-VCGOFF4 and VbSELa <x>. The second transfer transistor Trb5 is connected between the selection gate line driving circuit 15a and the source side selection gate line SGS in the second column memory unit MU. The second transfer transistor Trb5 outputs the signal VSGS2 <x> to the source side select gate line SGS in the second column memory unit MU based on the signal VSGOFF and the signal VbSELa <x>. The second transfer transistor Trb6 is connected between the selection gate line driving circuit 15a and the drain side selection gate line SGD in the first column memory unit MU. The second transfer transistor Trb6 outputs the signal VSGD1 <x> to the drain side select gate line SGD in the first column memory unit MU based on the signal VSGOFF and the signal VbSELa <x>.

The row decoder circuit 19b uses the signals VCG5 <i> -VCG8 <i> (or signals VCG5 <x> -VCG8 to the gates of the memory transistors MTr5-MTr8 based on the signals BAD, signals VCG5-VCG8 and signals VCGOFF5-VCGOFF8. <x>). In addition, the row decoder circuit 19b selectively selects the signal VSGS1 <i> (or the signal VSGS1 <x) at the gate of the source-side selection transistor SSTr in the first column memory unit MU based on the signal BAD, the signal VSGS1 and the signal VSGOFF. Enter>). Further, the row decoder circuit 19a may optionally select a signal VSGD2 <i> (or a signal VSGD2 <x) at the gate of the drain side select transistor SDTr in the second column memory unit MU based on the signal BAD, the signal VSGD2, and the signal VSGOFF. Enter>).

The row decoder circuit 19b includes a NAND circuit 19ba, a NOT circuit 19bb, a voltage conversion circuit 19bc, a first transfer transistor Trc1-Trc7, and a second transfer transistor Trd1-Trd7. The voltage conversion circuit 19bc generates a signal VSELb <i> (or VSELb <x>) based on the signal BAD received through the NAND circuit 19ba and the NOT circuit 19bb, and the signal RDEC, and this signal VSELb <i> (or VSELb <x>) is output to the gates of the first transfer transistors Trc1-Trc7. In addition, the voltage conversion circuit 19bc generates the signal VbSELb <i> (or VbSELb <x>) based on the signal BAD and the signal RDEC, and transmits this signal VbSELb <i> (or VbSELb <x>) to the second transmission. It outputs to the gates of the transistors Trd1-Trd7.

The first transfer transistors Trc1-Trc4 are connected between the word line driver circuit 13b and each word line WL5-WL8. The first transfer transistors Trc1-Trc4 output signals VCG5 <i> -VCG8 <i> to the word lines WL5-WL8 based on the signals VCG5-VCG8 and VSELb <i>. The first transfer transistor Trc5 is connected between the back gate line driving circuit 14 and the back gate line BG. The first transfer transistor Trc5 outputs the signal VBG to the back gate line BG based on the signal VBG and the signal VSELb <i>. The first transfer transistor Trc6 is connected between the selection gate line driving circuit 15b and the source side selection gate line SGS in the first column memory unit MU. The first transfer transistor Trc6 outputs the signal VSGS1 <i> to the source side select gate line SGS in the first column memory unit MU based on the signal VSGS1 and the signal VSELb <i>. The first transfer transistor Trc7 is connected between the selection gate line driving circuit 15b and the drain side selection gate line SGD in the second column memory unit MU. The first transfer transistor Trc7 outputs the signal VSGD2 <i> to the drain side select gate line SGD in the second column memory unit MU based on the signal VSGD2 and the signal VSELb <i>.

The second transfer transistors Trd1-Trd4 are connected between the word line driver circuit 13b and each word line WL5-WL8. The second transfer transistors Trd1-Trd4 output signals VCG5 <x> -VCG8 <x> to the word lines WL5-WL8 based on the signals VCGOFF5-VCGOFF8 and VbSELb <x>. The second transfer transistor Trd5 is connected between the back gate line driving circuit 14 and the back gate line BG. The second transfer transistor Trd5 outputs the signal VBGOFF to the back gate line BG based on the signal VBGOFF and the signal VbSELb <x>. The second transfer transistor Trd6 is connected between the selection gate line driving circuit 15b and the source side selection gate line SGS in the first column memory unit MU. The second transfer transistor Trd6 outputs the signal VSGS1 <x> to the source side select gate line SGS in the first column memory unit MU based on the signal VSGOFF and the signal VbSELb <x>. The second transfer transistor Trd7 is connected between the selection gate line driving circuit 15b and the drain side selection gate line SGD in the second column memory unit MU. The second transfer transistor Trd7 outputs the signal VSGD2 <x> to the drain side select gate line SGD in the second column memory unit MU based on the signal VSGOFF and the signal VbSELb <x>.

That is, connected to the word lines WL1-WL8 are the first transfer transistors Tra1-Tra4 and Trc1-Trc4 and the second transfer transistors Trb1-Trb4 and Trd1-Trd4, respectively. Connected to the source side select gate line SGS and the drain side select gate line SGD are first transfer transistors Tra5 and Tra6 (Trc6 and Trc7) and second transfer transistors Trb5 and Trb6 (Trd6 and Trd7), respectively. Connected to the back gate line BG are the first transfer transistor Trc5 and the second transfer transistor Trd5. Moreover, the first transfer transistors Tra1-Tra6 and Trc1-Trc7 become conductive when the memory string MS is selected. The second transfer transistors Trb1-Trb6 and Trd1-Trd7 become conductive when the memory string MS is not selected. Note that the number of signal lines supplying a signal to the provided word lines WL1-WL8 is greater than 8, for example, the number of memory transistors MTr1-MTr8 in one memory string of 16 memory strings MS.

Next, a specific configuration of the boost circuits 12a-12d is described with reference to FIG. 6. 6 is a circuit diagram showing the boost circuit 12a. Note that since the configuration of the boost circuits 12b-12d is similar to that of the boost circuit 12a, the boost circuit 12a is mainly described below.

The boost circuit 12a uses the charge / discharge of the capacitor to generate a voltage higher than the power supply voltage Vdd. As shown in FIG. 6, the boost circuit 12a includes diodes 121a-121n and charge / discharge circuits 122a-122l. Note that the boost circuit 12a may further include a diode and a charge / discharge circuit.

The diodes 121a-121e are connected in series, as shown in FIG. 6. In addition, the diodes 121f-121n are connected in series. One end of the diode 121a is connected to one end of the diode 121f. One end of the diode 121e is connected to one end of the diode 121n.

As shown in Fig. 6, the charge / discharge circuits 122a-122d have their output terminals connected between the diodes 121a-121e. The charge / discharge circuits 122e-122l have their output terminals connected between the diodes 121f-121n. The charge / discharge circuits 122a-122l have an AND circuit 123, an inverter 124, and a capacitor 125 connected in series.

The charge / discharge circuits 122a-122d are configured such that one of the input terminals of the AND circuit 123 alternately receives the signal φ1 or the signal φ2. The charge / discharge circuits 122a-122d are configured such that the other of the input terminals of the AND circuit 123 receives the signal PASS.

The charge / discharge circuits 122e-122l are configured such that one of the input terminals of the AND circuit 123 alternately receives the signal φ1 or the signal φ2. The charge / discharge circuits 122e-122l are configured such that the other of the input terminals of the AND circuit 123 receives the signal PRG.

Here, the operation of the boost circuit 12a is described with reference to FIGS. 7A and 7B. 7A and 7B are timing charts showing the operation of the boost circuit 12a. As shown in Figs. 7A and 7B, the boost circuit 12a sets the signal PASS or the signal PRG to the power supply voltage Vdd or the ground voltage Vss, depending on the signal to be generated.

Next, specific configurations of the word line driving circuits 13a and 13b are described with reference to FIG. 8 is a circuit diagram showing the word line driver circuit 13a. Note that since the configuration of the word line driver circuit 13b is similar to that of the word line driver circuit 13a, the word line driver circuit 13a is mainly described below.

The word line driver circuit 13a is constituted by the first to eighth word line driver circuits 13A-13H, as shown in FIG. The first to eighth word line driver circuits 13A-13H output signals VCG1-VCG4 and VCGOFF1-VCGOFF4, respectively. Note that in the word line driving circuit 13b, the first to eighth word line driving circuits 13A-13H output VCG5-VCG8 and VCGOFF5-VCGOFF8 (not shown), respectively.

As shown in FIG. 8, the first word line driver circuit 13A includes NAND circuits 131a-131c, a voltage conversion circuit 132, NOT circuits 133a and 133b, and transfer transistors 134a-134e. do. Input terminals of the NAND circuits 131a-131c receive a control signal from the sequencer 18. The output terminal of the NAND circuit 131a is connected to the gate of the transfer transistor 134a through the voltage conversion circuit 132. The output terminal of the NAND circuit 131b is connected to the gates of the transfer transistors 134b and 134c through the NOT circuit 133a. The output terminal of the NAND circuit 131c is connected to the gate of the transfer transistor 134d. In addition, the output terminal of the NAND circuit 131c is connected to the gate of the transfer transistor 134e through the NOT circuit 133b.

The transfer transistor 134a has one end connected to the output terminal of the boost circuit 12a and the other end connected to the node 135. Here, node 135 outputs signal VCG1. The transfer transistor 134b is connected in series with the transfer transistor 134c. The other end of the transfer transistor 134b is connected to the ground voltage Vss. The other end of transfer transistor 134c is connected to node 135. The transfer transistor 134d is connected in series with the transfer transistor 134e. The other end of the transfer transistor 134d is connected to the power supply voltage Vdd. The other end of transfer transistor 134e is connected to node 135. Note that the second to eighth word line driving circuits 13B-13H have a configuration similar to that of the first word line driving circuit 13A.

Next, the specific configuration of the back gate line driving circuit 14 is described with reference to FIG. 9 is a circuit diagram showing the back gate line driving circuit 14.

The back gate line driving circuit 14 is constituted by the first and second back gate line driving circuits 14A and 14B, as shown in FIG. The first and second back gate line driving circuits 14A and 14B output signals VBG and VBGOFF, respectively.

As shown in FIG. 9, the first back gate line driving circuit 14A includes the NAND circuits 141a-141c, the voltage conversion circuit 142, the NOT circuits 143a and 143b, and the transfer transistors 144a-144e. Include. Since these circuits 141a-141c, 142, and 143a and 143b and the transfer transistors 144a-144e have a connection relationship that is substantially similar to that of the first word line driver circuit 13A, description thereof is omitted. Note that one end of the transfer transistor 144a is connected to the boost circuit 12b and the other end is connected to the node 145. Node 145 outputs signal VBG. The second back gate line driver circuit 14B has a configuration similar to the first back gate line driver circuit 14A.

Next, the specific configuration of the selection gate line driving circuits 15a and 15b is described with reference to FIG. 10 is a circuit diagram showing the selection gate line driver circuit 15a. Note that since the configuration of the selection gate line driving circuit 15b is similar to that of the selection gate line driving circuit 15a, the selection gate line driving circuit 15a is mainly described below.

The selection gate line driving circuit 15a is constituted by the first to third selection gate line driving circuits 15A-15C, as shown in FIG. The first to third select gate line driving circuits 15A-15C output signals VSGS2, VSGD1, and VSGOFF, respectively. Note that in the selection gate line driving circuit 15b, the first to third selection gate line driving circuits 15A-15C output signals VSGS1, VSGD2 and VSGOFF (not shown), respectively.

As shown in FIG. 10, the first select gate line driving circuit 15A includes NAND circuits 151a and 151b, NOT circuits 152a and 152b, voltage conversion circuits 153a and 153b, and transfer transistors 154a and 154b. ). NAND circuits 151a and 151b receive control signals from sequencer 18, respectively. NAND circuits 151a and 151b have their output terminals connected to one of the input terminals of voltage conversion circuits 153a and 153b, respectively. In addition, the NAND circuits 151a and 151b have their output terminals connected to other ones of the input terminals of the voltage conversion circuits 153a and 153b through the NOT circuits 152a and 152b, respectively. The voltage conversion circuits 153a and 153b have their output terminals connected to the gates of the transfer transistors 154a and 154b, respectively.

Transfer transistor 154a has one end connected to ground voltage Vss and the other end connected to node 155. Here, node 155 outputs signal VSGS2. The transfer transistor 154b has one end connected to the power supply voltage Vdd and the other end connected to the node 155. Note that the second and third select gate line driver circuits 15B and 15C have a configuration similar to that of the first select gate line driver circuit 15A.

Next, a specific configuration of the source line driver circuit 16 is described with reference to FIG. 11 is a circuit diagram showing the source line driver circuit 16.

The source line driving circuit 16 includes NAND circuits 161a-161c, NOT circuits 162a-162c, voltage conversion circuits 163a-163c, and transfer transistors 164a-164c, as shown in FIG. do. NAND circuits 161a-161c receive control signals from sequencer 18, respectively. The NAND circuits 161a-161c have their output terminals connected to one of the input terminals of the voltage conversion circuits 163a-163c, respectively. In addition, the NAND circuits 161a-161c have their output terminals connected to other ones of the input terminals of the voltage conversion circuits 163a-163c through the NOT circuits 162a-162c respectively. The voltage conversion circuits 163a-163c have their output terminals connected to the gates of the transfer transistors 164a-164c, respectively.

The transfer transistor 164a has one end connected to the output terminal of the boost circuit 12c and the other end connected to the node 165. Here, node 165 outputs signal VSL. Transfer transistor 164b has one end connected to ground voltage Vss and the other end connected to node 165. The transfer transistor 164c has one end connected to the power supply voltage Vdd and the other end connected to the node 165.

Next, a specific configuration of the sense amplifier circuit 17 is described with reference to FIG. 12 is a circuit diagram showing the sense amplifier circuit 17. As shown in FIG. 12, the sense amplifier circuit 17 includes select circuits 171a-171c, NAND circuits 172a and 172b, NOT circuits 173a and 173b, and voltage conversion circuits 174a and 174b. . The selection circuits 171a-171c selectively connect the bit line BL to the source line SL, and set the potential of the bit line BL to the same potential as the source line SL.

The selection circuits 171a-171c include the page buffer 171A and the transfer transistors 171B and 171C, respectively, as shown in FIG. 12. The page buffer 171A receives a signal from the bit line BL, and outputs a signal to the external and address decoder circuit 11 based on the received signal. One end of the transistor 171B is connected to the bit line BL, and the other end thereof is connected to the page buffer 171A. The gate of transistor 171B receives the output signal VCUT from voltage conversion circuit 174a. One end of the transistor 171C is connected to the bit line BL, and the other end thereof is connected to the source line SL. The gate of the transistor 171C receives the output signal VRST from the voltage conversion circuit 174b.

NAND circuits 172a and 172b respectively receive control signals from sequencer 18. NAND circuits 172a and 172b have their output terminals connected to one of the input terminals of voltage conversion circuits 174a and 174b, respectively. In addition, the NAND circuits 172a and 172b have their output terminals connected to other ones of the input terminals of the voltage conversion circuits 174a and 174b through the NOT circuits 173a and 173b, respectively. The voltage conversion circuit 174a inputs the signal VCUT to the gate of the transistor 171B based on the received signal. The voltage conversion circuit 174b inputs the signal VRST to the gate of the transistor 171C based on the received signal.

[Read Action]

Next, a read operation in the nonvolatile semiconductor memory device according to the first embodiment will be described with reference to FIG. 13 is a timing chart showing a read operation according to the first embodiment. The read operation shown in FIG. 13 is executed on the selection memory transistor MTr2 included in the selection memory transistor MTr of the first column in the selection memory block MB <i>. Note that all memory strings MS in unselected memory block MB <x> are unselected memory strings MS.

First, the operation in the selected memory block MB <i> is described with reference to FIG. Initially, at time t11, signal VBL rises to voltage Vpre. That is, the bit line BL is precharged with the voltage Vpre. Then, at time t12, the signals VSELa <i> and VSELb <i> rise to the voltage Vpp. Next, at time t13, the signals VSGS1 <i> and VSGD1 <i> rise to the voltage Vdd. In addition, at time t13, the signals VCG1 <i>, VCG3 <i> -VCG8 <i> and VBG <i> rise to the read pass voltage Vread. Note that the voltage Vpp is the voltage that causes the first transfer transistors Tra1-Tra4 and Trc1-Trc4 to conduct.

After time t13, the voltage change of the bit line BL is detected by the sense amplifier circuit 15, thereby reading data in the selected memory transistor MTr2.

Next, the operation in the unselected memory block MB <x> is described with reference to FIG. First, at time t11, the signal VBL rises to the voltage Vpre. Then, at time t12, signals VbSELa <x> and VbSELb <x> rise to voltage Vpp. Next, at time t13, the signals VCG1 <x>, VCG3 <x>, VCG6 <x>, VCG8 <x> and VBG <x> rise to the read pass voltage Vread. Note that the signals VCG2 <x>, VCG4 <x>, VCG5 <x> and VCG7 <x> remain at the voltage Vss.

The outline of the above described read operation in the unselected memory block MB <x> is now described with reference to FIG. In Fig. 14, the memory transistor MTr3 is assumed to be in the write state (the electrons are stored in the charge storage layer, the threshold voltage of the memory transistor has a positive value), and the memory transistor MTr6 is assumed to be in the erased state (excessive erase operation). Due to this, the threshold voltage of the memory transistor has a negative value which is too large). That is, the charge storage layer in the memory transistor MTr3 is assumed to have a high concentration of electrons, and the charge storage layer in the memory transistor layer MTr6 is assumed to have a high concentration of holes.

When the operation shown in FIG. 13 is executed, as shown in FIG. 14, the source side select transistor SSTr, the drain side select transistor SDTr and the memory transistors MTr2, MTr4, MTr5 and MTr7 in the unselected memory block MB <x>. There is no channel formed within the body of the. On the other hand, there are channels formed in the bodies of the memory transistors MTr1, MTr3, MTr6 and MTr8, and the back gate transistor BTr.

That is, during the read operation in the nonvolatile semiconductor memory device according to the first embodiment, the gates of the memory transistors MTr1-MTr8 and the back gate transistor BTr in the unselected memory string MS are alternately applied with the read pass voltage Vread and the voltage Vss. The potentials of the bodies of the memory transistors MTr1, MTr3, MTr6 and MTr8, and the back gate transistor BTr are made lower than the potentials of the bodies of the other memory transistors MTr2, MTr4, MTr5 and MTr7, and the source side select transistor SSTr. Since the voltage Vread is applied to the memory transistor, a channel is formed in the body of the memory transistor regardless of whether the memory transistor is in the write state (MTr3) or in the erased state (MTr6).

The read operation described above causes an energy barrier to be formed between the body of the source side select transistor SSTr and the source line SL, and an energy barrier is formed between the body of the drain side select transistor SDTr and the bit line BL. These energy barriers make it possible to suppress the current flowing from the bit line BL to the source line SL through the unselected memory string MS during the read operation.

Further, the well type potential is formed in the body of the memory transistors MTr1, MTr3, MTr6 and MTr8, and the back gate transistor BTr. By trapping electrons within the well potential, the current flowing from the bit line BL to the source line SL through the unselected memory string MS can be suppressed during the read operation.

[Write operation]

Next, a write operation in the nonvolatile semiconductor memory device according to the first embodiment will be described with reference to FIG. 15 is a timing chart showing a write operation according to the first embodiment. The write operation shown in FIG. 15 is executed on the selection memory transistor MTr2 included in the selection memory transistor MTr of the first column in the selection memory block MB <i>.

First, at time t21, the signals VSELa <i> and VSELb <i> rise to the voltage Vpp. Then, at time t22, signal VSL rises to voltage Vdd. In addition, at time t22, the signal VBL rises to the voltage Vdd when " 1 " writing is performed, and remains at the voltage Vss when " 0 " writing is performed. Next, at time t23, the signal VSGD1 <i> rises to the voltage Vdd. In addition, at time t23, the signal VCG2 <i> rises to the voltage Vprg, and the signals VCG1 <i>, VCG3 <i> -VCG8 <i> and VBG <i> rise to the voltage Vpass. Note that the voltage Vpass is the voltage that causes the memory transistor MTr to be in a conductive state, and the voltage Vprg is the voltage that causes charge to be stored in the charge storage layer of the memory transistor MTr.

After time t23, a predetermined voltage is applied to the gate of the selection memory transistor MTr2, thereby performing a write operation.

[Clear operation]

Next, the erase operation in the nonvolatile semiconductor memory device according to the first embodiment will be described with reference to FIG. 16 is a timing chart showing an erase operation according to the first embodiment. The erase operation shown in FIG. 16 is executed on the memory transistors MTr1-MTr8 in the entire selection memory block MB <i>.

First, at time t31, the signals VSELa <i> and VSELb <i> rise to the voltage Vdd. Then, at time t32, signals VSGS1 <i>, VSGS2 <i>, VSGD1 <i>, VSGD2 <i>, VCG1 <i> -VCG8 <i> and VBG <i> rise to the voltage Vdd-Vth . Next, at time t33, the signals VSL and VBL rise to the voltage Vera. In addition, at time t33, the signals VSGS1 <i>, VSGS2 <i>, VSGD1 <i>, VSGD2 <i>, VCG1 <i> -VCG8 <i> and VBG <i> are set to a floating state, and then Boosted by engagement. Then, at time t34, signals VCG1 <i> -VCG8 <i> and VBG <i> are lowered to voltage Vss. Note that the voltage Vera is the voltage causing the generation of the GIDL current.

After the time t34, holes caused by the GIDL current are injected into the charge storage layer of the memory transistors MTr1-MTr8, whereby the erase operation is executed.

[Advantages]

Next, the advantages of the first embodiment are described. As shown in Fig. 14 described above, during the read operation in the nonvolatile semiconductor memory device according to the first embodiment, the well type potential is selected from the memory transistors MTr1, MTr3, MTr6, MTr8, And in the body of the back gate transistor BTr. Therefore, during the read operation in the nonvolatile semiconductor memory device according to the first embodiment, the current flowing from the bit line BL to the source line SL through the unselected memory string MS can be suppressed.

Second Embodiment

[Configuration]

Next, a nonvolatile semiconductor memory device according to the second embodiment will be described. Since the configuration of the nonvolatile semiconductor memory device according to the second embodiment is similar to that of the first embodiment, the description thereof is omitted. Note that, in the second embodiment, the same symbols are given to the configuration similar to that of the first embodiment, and the description thereof is omitted.

During a read operation in the nonvolatile semiconductor memory device according to the second embodiment, the power supply voltage Vdd is coupled to the memory transistors MTr (eg, MTr2 and MTr3, and / or MTr5) which are adjacent to each other included in the unselected memory string MS. By being applied to the gate of MTr6, the potential of the body between adjacent memory transistors MTr is lower than the potential of the body of the other memory transistors MTr to which the ground voltage Vss is applied to the gate. The power supply voltage Vdd is a positive voltage less than the read pass voltage Vread.

[Read Action]

Next, a read operation in the nonvolatile semiconductor memory device according to the second embodiment will be described with reference to FIG. 17 is a timing chart showing a read operation according to the second embodiment. In the read operation of the second embodiment, only the operation in the unselected memory block MB <x> is different from the operation of the first embodiment.

The read operation in the unselected memory block MB <x> is the first in that at time t13 the signals VCG2 <x>, VCG3 <x>, VCG6 <x> and VCG7 <x> rise to the power supply voltage Vdd. It is different from the read operation of the embodiment. Note that the signals VCG1 <x>, VCG4 <x>, VCG5 <x>, VCG8 <x> and VBG <x> remain at ground voltage Vss. The other signals are driven similarly to the first embodiment.

The outline of the above described read operation in the unselected memory block MB <x> is now described with reference to FIG. In Fig. 18, memory transistors MTr2 and MTr3 are assumed to be in a write state, and memory transistors MTr6 and MTr7 are assumed to be under erased.

When the operation shown in FIG. 17 is executed, as shown in FIG. 18, the source side select transistor SSTr, the drain side select transistor SDTr, the memory transistors MTr1-MTr4, MTr5, and MTr8 in the unselected memory block MB <x>. And no channel is formed in the body of the back gate transistor BTr. On the other hand, even if there is no channel formed in the body of the memory transistors MTr2 and MTr3 to which the power supply voltage Vdd is applied continuously, regardless of the data stored in the memory transistors MTr2 and MTr3, the two electric fields MTr2 and There is a channel formed between MTr3. In addition, a small potential well is formed in the body between the memory transistors MTr2 and MTr3.

Moreover, since the memory transistors MTr6 and MTr7 are in the over erased state, a continuous expansion channel is formed in the body. As a result, the potential of the body immediately below the memory transistors MTr6 and MTr7 is lowered overall (a large potential well is formed) compared to the potentials of the bodies of the memory transistors MTr5 and MTr8 (to which the voltage Vss is applied).

That is, during the read operation in the nonvolatile semiconductor memory device according to the second embodiment, the voltage Vdd is applied to the adjacent memory transistors MTr2 and MTr3 and the gates of the memory transistors MTr6 and MTr7 adjacent to each other in the unselected memory string MS. , The potential of the body between the memory transistors MTr2 and MTr3, and the potential of the body between the memory transistors MTr6 and MTr7 are made lower than the potential of the body of the other memory transistors MTr.

[Advantages]

Next, the advantages of the second embodiment are described. As shown in Fig. 18, in the non-selected memory block MB <x>, an energy barrier is formed between the source side select transistor SSTr and the source line SL and between the drain side select transistor SDTr and the bit line BL. These energy barriers make it possible to suppress the current flowing from the bit line BL to the source line SL through the unselected memory string MS during the read operation in the nonvolatile semiconductor memory according to the second embodiment.

Moreover, in the non-selected memory block MB <x>, a well type potential is formed in the body between the memory transistors MTr2 and MTr3. In addition, successive expansion well potentials are formed in the bodies of the memory transistors MTr6 and MTr7. By trapping electrons in these well type potentials, the current flowing from the bit line BL to the source line SL through the unselected memory string MS can be suppressed during the read operation in the nonvolatile semiconductor memory according to the second embodiment.

Third Embodiment

[Configuration]

Next, the configuration of the nonvolatile semiconductor memory device according to the third embodiment will be described with reference to FIGS. 19 and 20. 19 is a block diagram showing a word line driver circuit 13a according to the third embodiment. 20 is a partial circuit diagram showing the row decoder circuits 19a and 19b according to the third embodiment. Note that, in the third embodiment, the same symbols are given to configurations similar to those of the first and second embodiments, and the description thereof is omitted.

During the read operation in the nonvolatile semiconductor memory device according to the third embodiment, the power supply voltage Vdd is applied only to the gate of the back gate transistor BTr included in the non-selected memory string MS, so that only the potential of the body of the back gate transistor BTr is applied. It is lower than the potential of others. In order to realize such a configuration, the nonvolatile semiconductor memory device according to the third embodiment includes word line driving circuits 13a and 13b and row decoder circuits 19a and 19b different from the circuits of the first embodiment.

During the read operation, the word line driving circuits 13a and 13b do not need to drive the word lines WL1-WL8 contained in the unselected memory block MB <x>. Therefore, the word line driving circuit 13a includes only the first to fourth word line driving circuits 13A-13D and outputs only the signals VCG1-VCG4, as shown in FIG. different. Note that the word line driver circuit 13b has a configuration similar to that of the word line driver circuit 13a.

As shown in Fig. 20, the row decoder circuit 19a has a configuration in which the second transfer transistors Trb1-Trb4 are omitted for similar reasons as the word line driving circuits 13a and 13b described above. Similarly, the row decoder circuit 19b has a configuration in which the second transfer transistors Trd1-Trd4 are omitted.

[Read Action]

Next, a read operation in the nonvolatile semiconductor memory device according to the third embodiment will be described with reference to FIG. 21 is a timing chart showing a read operation according to the third embodiment. In the read operation of the third embodiment, only the operation in the unselected memory block MB <x> is different from the operation of the first embodiment.

The operation in the unselected memory block MB <x> differs from the operation of the first and second embodiments in that only the signal VBG <x> rises to the power supply voltage Vdd at time t13. Note that the signals VCG1 <x> -VCG8 <x> remain at ground voltage Vss. The other signals are driven similarly to the first embodiment.

The outline of the above-described read operation in the unselected memory block MB <x> is now described with reference to FIG. In Fig. 22, memory transistor MTr3 is assumed to be in a write state, and memory transistor MTr6 is assumed to be in an erased state.

When the above-described operation shown in FIG. 21 is executed, as shown in FIG. 22, the source side select transistor SSTr, the drain side select transistor SDTr, and the memory transistors MTr1-MTr5 in the unselected memory block MB <x>. There is no channel formed in the body of MTr7 and MTr8. On the other hand, there are channels formed in the bodies of the memory transistor MTr6 and the back gate transistor BTr, respectively. Note that the channel in the body of the memory transistor MTr6 is based on the over erased state of the memory transistor MTr6.

That is, during the read operation in the nonvolatile semiconductor memory device according to the third embodiment, the voltage Vdd is applied only to the gate of the back gate transistor BTr included in the non-selected memory string MS, whereby the potential of the body of the back gate transistor BTr is changed. Make it lower than the potential of anything else.

[Advantages]

Next, the advantages of the third embodiment are described. As shown in Fig. 22, in the non-selected memory block MB <x>, an energy barrier is formed between the source side select transistor SSTr and the source line SL and between the drain side select transistor SDTr and the bit line BL. These energy barriers make it possible to suppress the current flowing from the bit line BL to the source line SL through the unselected memory string MS during the read operation in the nonvolatile semiconductor memory according to the third embodiment.

Moreover, in the non-selected memory block MB <x>, the well type potential is formed in the body of the back gate transistor BTr. By trapping electrons in this well type potential, the current flowing from the bit line BL to the source line SL through the unselected memory string MS can be suppressed during the read operation in the nonvolatile semiconductor memory according to the third embodiment.

In addition, as shown in FIGS. 19 and 20, the occupied area of the circuit in the nonvolatile semiconductor memory device according to the third embodiment can be reduced as compared with the first and second embodiments.

[Example 4]

[Configuration]

Next, the configuration of the nonvolatile semiconductor memory device according to the fourth embodiment will be described with reference to FIGS. 23 and 24. Fig. 23 is a block diagram showing the word line driver circuit 13a. 24 is a circuit diagram showing the back gate line driving circuit 14. Note that, in the fourth embodiment, the same symbols are given to configurations similar to those of the first to third embodiments, and the description thereof is omitted.

During the read operation in the nonvolatile semiconductor memory device according to the fourth embodiment, the read pass voltage Vread is applied to the gate of the memory transistor MTr included in the unselected memory string MS, thereby similarly to the first embodiment, the memory transistor Make the potential of the body of the MTr lower than that of others. Furthermore, in the nonvolatile semiconductor memory device according to the fourth embodiment, the voltage VNN is applied to the memory transistor MTr and the back gate transistor BTr included in the unselected memory string MS, whereby the potentials of the bodies of the memory transistor MTr and the back gate transistor BTr are provided. Make it higher than the potential of others. Note that the voltage VNN is a negative voltage. In order to realize such a configuration, the nonvolatile semiconductor memory device according to the fourth embodiment includes boost circuits 12a and 12b, word line driving circuits 13a and 13b, and back gate line driving circuit 14 different from those of the first embodiment. ).

The boost circuit 12a inputs a signal having a negative voltage VNN to the word line driving circuits 13a and 13b. The boost circuit 12b inputs a signal having a negative voltage VNN to the back gate line driving circuit 14.

As shown in Fig. 23, the word line driving circuit 13a includes first to eighth word line driving circuits 13A "-13H" different from the first embodiment. Note that since the configuration of the word line driver circuit 13b is similar to that of the word line driver circuit 13a, the word line driver circuit 13a is mainly described below.

The first word line driving circuit 13A "includes NAND circuits 131a" -131c ", NOT circuits 132a" -132c ", voltage conversion circuits 133a" -133c ", and transfer transistors 134a" -134c ". Each of the NAND circuits 131a "-131c" receives a control signal from the sequencer 18. The NAND circuits 131a "-131c" have their output terminals respectively being voltage conversion circuits 133a "-133c. Is connected to one of the input terminals of " " In addition, the NAND circuits 131a " -131c " have their output terminals respectively connected via voltage conversion circuits 133a " -133c " Is connected to the other of the input terminals of the voltage conversion circuits 133a "-133c", and their output terminals are respectively connected to gates of the transfer transistors 134a "-134c".

The transfer transistor 134a "has one end connected to the output terminal of the boost circuit 12a and the other end connected to the node 135". Here, node 135 "outputs signal VCG1. Transfer transistor 134b" has one end connected to ground voltage Vss and the other end connected to node 135 ". Transfer transistor 134c" Is connected at one end to the power supply voltage Vdd, and at the other end to the node 135 ". Note that the second to eighth word line driver circuits 13B" -13H "drive the first word line. It has a configuration similar to the circuit 13A ".

The back gate line driving circuit 14 includes first and second back gate line driving circuits 14A "and 14B" different from the first embodiment, as shown in FIG. The first back gate line driving circuit 14A "includes the NAND circuits 141a" -141c ", the NOT circuits 142a" -142c ", the voltage conversion circuits 143a" -143c ", and the transfer transistors 144a" -144c. These circuits 141a "-141c", 142a "-142c", and 143a "-143c" and the transfer transistors 144a "-144c" are the first word line driver circuit 13A "described above. Since it has a connection relationship similar to), the description is omitted. Note that the transfer transistor 144a "has one end connected to the output terminal of the boost circuit 12b and the other end connected to the node 145". Node 145 "outputs signal VBG. Note that second back gate line driver circuit 14B" has a configuration similar to first back gate line driver circuit 14A ".

[Read Action]

Next, a read operation in the nonvolatile semiconductor memory device according to the fourth embodiment will be described with reference to FIG. 25 is a timing chart showing a read operation according to the fourth embodiment. In the read operation of the fourth embodiment, only the operation in the unselected memory block MB <x> is different from the read operation of the first embodiment.

The operation in the unselected memory block MB <x> differs from the first to third embodiments in that the signals VCG1 <x>, VCG8 <x>, and VBG <x> fall to the voltage VNN at time t13. In addition, the signals VCG3 <x> and VCG6 <x> rise to the read pass voltage Vread. Note that the signals VCG2 <x>, VCG4 <x>, VCG5 <x>, and VCG7 <x> remain at ground voltage Vss. The other signals are driven similarly to the first embodiment.

An overview of the above-described operation in the unselected memory block MB <x> is now described with reference to FIG. In Fig. 26, the memory transistor MTr3 is assumed to be in the write state, and the memory transistor MTr6 is assumed to be in the erased state.

In the case where the above-described operation shown in FIG. 25 is executed, as shown in FIG. 26, the source side select transistor SSTr, the drain side select transistor SDTr, the memory transistors MTr1, MTr2, in the unselected memory block MB <x>, as shown in FIG. There are no channels formed in the bodies of MTr4, MTr5, MTr7 and MTr8, and the back gate transistor BTr. On the other hand, there are channels formed in the bodies of the memory transistors MTr3 and MTr6, respectively. In addition, the concentrations of holes in the memory transistors MTr1 and MTr8 and the back gate transistor BTr increase.

That is, during the read operation in the nonvolatile semiconductor memory device according to the fourth embodiment, the voltage Vread is applied to the gates of the memory transistors MTr3 and MTr5 in the non-selected memory string MS, thereby increasing the potentials of the bodies of the memory transistors MTr3 and MTr5. It is lower than the potential of others. On the other hand, during the read operation in the nonvolatile semiconductor memory device according to the fourth embodiment, the negative voltage VNN is applied to the gates of the memory transistors MTr1 and MTr8 and the back gate transistor BTr in the unselected memory string MS, thereby The potentials of the bodies of MTr1 and MTr8 and the back gate transistor BTr are made higher than those of others. In addition, the gates of the memory transistors MTr2, MTr4, MTr5, and MTr7 are set to the ground voltage Vss such that the gate to which the voltage VNN is applied is not adjacent to the gate to which the read-through voltage Vread is applied. This is to prevent the generation of a large electric field in the body of the memory transistor MTr due to the voltage VNN and the read pass voltage Vread.

[Advantages]

Next, the advantages of the fourth embodiment are described. As shown in Fig. 26, in the non-selected memory block MB <x>, an energy barrier is formed between the source side select transistor SSTr and the source line SL and between the drain side select transistor SDTr and the bit line BL. These energy barriers make it possible to suppress the current flowing from the bit line BL to the source line SL through the unselected memory string MS during the read operation in the nonvolatile semiconductor memory according to the fourth embodiment.

Moreover, in the unselected memory block MB <x>, a well type potential is formed in the bodies of the memory transistors MTr3 and MTr6. By trapping electrons within this well type potential, the current flowing from the bit line BL to the source line SL can be suppressed. Moreover, the bodies of the memory transistors MTr1 and MTr8 and the back gate transistor BTr constitute a potential barrier. This potential barrier makes it possible to suppress the current flowing from the bit line BL to the source line SL through the unselected memory string MS during the read operation in the nonvolatile semiconductor memory according to the fourth embodiment.

[Other Embodiments]

The description of the embodiment of the nonvolatile semiconductor memory device according to the present invention ends here, but the present invention is not limited to the above-described embodiment, and various changes, additions, substitutions, and the like are within the scope and spirit of the present invention. You will see that it is possible.

AR1: memory cell array
AR2: control circuit
10: substrate
20: back gate transistor layer
21: back gate conductive layer
30: memory transistor layer
33a: block insulation layer
33b: charge storage layer
33c: tunnel insulation layer
34: U-shaped semiconductor layer
34a: columnar portion
34b: connection part
40: select transistor layer
41a: source side conductive layer
41b: drain side conductive layer
50: wiring layer

Claims (20)

A nonvolatile semiconductor memory device,
A memory cell array having a plurality of memory strings each comprising a plurality of memory cells connected in series;
A select gate line disposed on the memory string, the select gate line to select the memory string; And
A control circuit that executes a read operation for reading data from the memory cells included in a selected memory string among a plurality of the memory strings
Including,
Each said memory string
A semiconductor layer having a columnar portion extending in a direction perpendicular to the substrate and functioning as a body of the memory cell;
A charge storage layer surrounding the columnar portion and holding data by storing charge;
An interlayer insulating layer formed to surround the columnar portion via the charge storage layer and extend in parallel to the substrate; And
It is formed so as to surround the columnar portion via the charge storage layer and extend parallel to the substrate, and is laminated via the interlayer insulating layer, and is not selected for the read memory string and the read operation. A plurality of word line conductive layers sharing a memory string to function as a gate of the memory cell
Including;
The control circuit applies a first voltage to a gate of at least one memory cell of the unselected memory strings, and a second lower than the first voltage to a gate of another memory cell of the unselected memory strings during the read operation. A nonvolatile semiconductor memory device for applying a voltage. The nonvolatile semiconductor memory device of claim 1, wherein the first voltage is a positive voltage that causes the memory cell to be in a conductive state regardless of data stored in the memory cell. The method of claim 1,
During the read operation, the control circuit applies the first voltage to the gates of two or more memory cells adjacent to each other in the unselected memory string,
And the first voltage is a positive voltage less than a read pass voltage that causes the memory cell to be in a conductive state regardless of data stored in the memory cell. The method of claim 1,
The memory string includes a back gate transistor connected between the memory cells,
The memory string is
A connecting portion which functions as a body of the back gate transistor by connecting lower ends of the pair of columnar portions in the semiconductor layer; And
A back gate conductive layer surrounding the connection portion via the charge storage layer, extending in parallel to the substrate, and functioning as a gate of the back gate transistor
More,
And the control circuit applies the first voltage to the gate of the back gate transistor in the unselected memory string during the read operation. The nonvolatile semiconductor memory device of claim 1, wherein the second voltage is a negative voltage. The semiconductor device of claim 1, further comprising a first transfer transistor and a second transfer transistor each having one end connected to the word line conductive layer.
The first transfer transistor is in a conductive state when the memory string is selected,
And the second transfer transistor is in a conductive state when the memory string is not selected. The semiconductor device of claim 4, further comprising a third transfer transistor and a fourth transfer transistor each having one end connected to the back gate conductive layer.
The third transfer transistor is in a conductive state when the memory string is selected,
And the fourth transfer transistor is in a conductive state when the memory string is not selected. The nonvolatile semiconductor memory device of claim 1, wherein, during the read operation, the control circuit alternately applies the first voltage and the second voltage to a gate of a memory cell in the unselected memory string. The nonvolatile semiconductor memory device of claim 1, wherein the second voltage is a ground voltage. The nonvolatile semiconductor memory device of claim 1, wherein, during the read operation, the control circuit applies a third voltage lower than the second voltage to a gate of another memory cell of the memory cells in the unselected memory string. . The memory device of claim 10, wherein, during the read operation, the control circuit applies the first voltage to a gate of an n th memory cell in the unselected memory string, and the (n + 1) th memory cell in the unselected memory string. And applying the second voltage to a gate of the second voltage, and applying the third voltage to a gate of an (n + 2) th memory cell in the unselected memory string. The method of claim 10,
The first voltage is a positive voltage configured to cause at least one of the memory cells to be in a conductive state regardless of data stored in at least one of the memory cells,
The second voltage is a ground voltage,
And the third voltage is a negative voltage. A nonvolatile semiconductor memory device,
A memory cell array having a plurality of memory strings each comprising a plurality of memory cells connected in series;
A select gate line disposed on the memory string, the select gate line to select the memory string; And
A control circuit configured to execute a read operation of reading data from a memory cell included in a selected memory string among the plurality of memory strings
Including,
Each said memory string
A semiconductor layer having a columnar portion extending in a direction perpendicular to the substrate and functioning as a body of the memory cell;
A charge storage layer surrounding the columnar portion and holding data by storing charge;
An interlayer insulating layer formed to surround the columnar portion via the charge storage layer and extend in parallel to the substrate;
It is formed so as to surround the columnar portion via the charge storage layer and extend in parallel with the substrate, and is laminated via the interlayer insulating layer, and is not selected for the read memory string and the read operation. A plurality of word line conductive layers sharing a memory string to function as a gate of the memory cell;
A connection portion connecting the lower ends of the pair of columnar portions in the semiconductor layer to function as a body of a back gate transistor; And
A back gate conductive layer surrounding the connection portion via the charge storage layer, extending in parallel to the substrate, and functioning as a gate of the back gate transistor
Including;
The control circuit applies a first voltage to a gate of at least one memory cell of the unselected memory strings, and a second lower than the first voltage to a gate of another memory cell of the unselected memory strings during the read operation. A nonvolatile semiconductor memory device for applying a voltage. 15. The nonvolatile semiconductor memory device of claim 13, wherein the first voltage is a positive voltage less than a read pass voltage that causes the memory cell to be conductive regardless of data stored in the memory cell. The nonvolatile semiconductor memory device of claim 13, wherein the second voltage is a ground voltage. The method of claim 13,
A first transfer transistor having one end connected to the word line conductive layer; And
A second transfer transistor and a third transfer transistor each having one end connected to the back gate conductive layer.
Further comprising:
The first transfer transistor is in a conductive state when the memory string is selected,
The second transfer transistor is brought into a conductive state when the memory string is not selected,
And the third transfer transistor is in a conductive state when the memory string is not selected. A data reading method in a nonvolatile semiconductor memory device, wherein the nonvolatile semiconductor memory device is disposed on the memory string and the memory cell array having a plurality of memory strings each including a plurality of memory cells connected in series. And a selection gate line for selecting the memory string, each memory string having a columnar portion extending in a direction perpendicular to a substrate, the semiconductor layer functioning as a body of the memory cell; A charge storage layer surrounding the columnar portion and holding data by storing charge; An interlayer insulating layer formed to surround the columnar portion via the charge storage layer and extend in parallel to the substrate; And are formed to surround the columnar portion via the charge storage layer and extend parallel to the substrate, and are stacked via the interlayer insulating layer, and are not subject to the selected memory string and a read operation. A plurality of word line conductive layers sharing a select memory string to function as a gate of the memory cell;
During a read operation of reading data from a memory cell included in the selected memory string among the plurality of memory strings, a first voltage is applied to a gate of at least one memory cell of the unselected memory strings, and the non-selection is performed. And applying a second voltage lower than the first voltage to a gate of another memory cell of a memory string. 18. The data read of claim 17 wherein the first voltage is a positive voltage that causes the memory cell to be conductive regardless of data stored in at least one of the memory cells. Way. The method of claim 17,
During the read operation, the first voltage is applied to gates of two or more memory cells adjacent to each other in the unselected memory string,
And wherein the first voltage is less than a read pass voltage and is a positive voltage configured to bring the memory cell into a conductive state regardless of data stored in the memory cell. The method of claim 17,
Each said memory string comprises a back gate transistor connected between said memory cells,
Each said memory string
A connecting portion which functions as a body of the back gate transistor by connecting lower ends of the pair of columnar portions in the semiconductor layer; And
A back gate conductive layer surrounding the connection portion via the charge storage layer, extending in parallel to the substrate, and functioning as a gate of the back gate transistor
More,
During the read operation, the first voltage is applied to a gate of the back gate transistor in the unselected memory string.

Images