KR101096210B1 - Method for Manufacturing Semiconductor Device - Google Patents

Abstract

The present invention forms a barrier film that is connected to the lower electrode contact plug of the dummy cell region, so that a dip-out solution penetrates into the ferry region during the dip out during the subsequent process, thereby removing the oxide layer, and stacking the plate layer on the removed region. The lower bit line (MTO layer) is not exposed during the etching process for connecting the metal wiring of the ferry region, or the short circuit between the metal wiring and the penetrated plate layer can be prevented, and as a result, the stability of the capacitor manufacturing process can be prevented. Provided are a method of manufacturing a semiconductor device that can be improved.

Description

Method for Manufacturing Semiconductor Device {Method for Manufacturing Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of increasing a yield in manufacturing a highly integrated semiconductor device.

A semiconductor memory device stores information such as data and program instructions. The semiconductor memory device is largely divided into DRAM and SRAM. Here, DRAM is an abbreviation of Dynamic Random Access Memory, and it is a memory that can read and store stored information, and can read and write information, but periodically within a certain period of time while power is supplied. If the information is not rewritten, the memory is lost. As described above, DRAM needs to continue refreshing, but it is widely used as a large-capacity memory because the price per memory cell is low and the density can be increased.

In general, one memory element, that is, a memory cell is composed of one transistor and one capacitor. Here, the capacitor has a structure in which a dielectric film (Dielectric) is interposed between two electrodes. The capacitance of the capacitor is proportional to the electrode surface area and the dielectric constant of the dielectric film and inversely proportional to the spacing between the electrodes, that is, the thickness of the dielectric film. Until now, a method of using a dielectric film having a high dielectric constant, a method of reducing the thickness of the dielectric film, a method of increasing the lower electrode surface area, or a method of reducing the distance between electrodes has been proposed to manufacture a capacitor having high capacitance.

However, as device sizes gradually decrease due to an increase in the degree of integration of semiconductor memory devices, it becomes more difficult to manufacture capacitors capable of securing sufficient capacitance due to a decrease in surface area of the lower electrode. In addition, it is limited to increase the dielectric constant only without increasing the electrode surface area of the capacitor in order to increase the capacitance of the capacitor. Accordingly, researches to improve the structure of the lower electrode have been continuously conducted. As a result, a concave type or a cylinder type capacitor having a three-dimensional structure has been developed to increase the electrode surface area.

1A to 1C are cross-sectional views illustrating a problem of a method of manufacturing a semiconductor device according to an embodiment of the prior art.

Referring to FIG. 1A, an isolation layer 120 defining an active region 110 is formed in a semiconductor substrate 100 including a cell region 1000a, a dummy cell region 1000b, and a ferry region 1000c.

A gate pattern 135 including a gate oxide layer, a gate conductive layer, and a gate hard mask layer is formed on the semiconductor substrate 100. In this case, the gate patterns of the cell region 1000a and the dummy cell region 1000b are not shown.

The first interlayer insulating layer 130 is formed on the entire surface including the gate pattern.

A photoresist film is formed on the first interlayer insulating layer 130, and a photoresist pattern (not shown) is formed by an exposure and development process using a contact plug mask.

The first interlayer insulating layer 130 is etched using the photoresist pattern as a mask to form a contact plug 140 for a storage node and a contact plug 150 for a bit line to expose the active region 110.

The bit line 160 connected to the bit line contact plug 150 is formed. In this case, the bit line 160 of the ferry region 1000c is called an MTO layer (metal layer), and the bit line 160 is formed when the bit line 160 is formed in the cell region 1000a and the dummy cell region 1000b. It can be formed at the same time. Here, a plurality of bit lines 160 are formed to be connected to the gate pattern 135 and to the active region 110.

Thereafter, the hard mask layer 170 is formed on the entire surface including the bit line 160.

First and second sacrificial insulating layers 180 and 190 are formed on the entire surface including the bit line hard mask layer 170.

The support layer 200 and the third sacrificial insulating layer 210 are formed on the first and second sacrificial insulating layers 180 and 190. In this case, the support layer 200 refers to an NFC (Nitride Floating Cap) film and is formed of a nitride film (Nitride).

A photosensitive film is formed on the third sacrificial insulating film 210, and a photosensitive film pattern (not shown) is formed by an exposure and development process using a lower electrode mask.

The third sacrificial insulating film 210, the support layer 200, the second sacrificial insulating film 190, the first sacrificial insulating film 180 and the bit line until the contact plug 140 for the storage node is exposed using the photoresist pattern as a mask. The hard mask layer 170 is etched to form the lower electrode region 220. In this case, the lower electrode region 220 of the cell region 1000a is formed of a hole type, and the lower electrode region 220 of the dummy cell region 1000b is formed of a line type. The reason why the lower electrode region 220 of the dummy cell region 1000b is formed in a line type is that the cell serves as a barrier film to prevent the wet solution of the ferry region 1000c from penetrating during subsequent processes. It surrounds the outer region of the area 1000a. Since the lower electrode region 220 of the dummy cell region 1000b formed as such a line type has a lower etching rate than the hole type, the lower contact node 140 for the storage node 140 as shown in FIG. 1A is not exposed. Unsuccessful defects occur.

Referring to FIG. 1B, after filling a conductive layer in the lower electrode region 220, the lower electrode 230 is formed by planarization etching.

Thereafter, a wet dip out process is performed to remove the second and first sacrificial insulating layers 180 and 190. In this case, in the normal process, the sacrificial insulating layers 180 and 190 of the cell region 1000a and the dummy cell region 1000b are removed, and the ferry region 1000c is formed by the support layer 200 and the dummy lower electrode 230. Lower sacrificial insulating layers 180 and 190 are not removed. However, due to a phenomenon in which the lower electrode region 220 of the dummy cell region 1000b does not expose the contact plug 140 for the lower storage node as shown in FIG. 1B, the wet solution may reach the ferry region 1000c. The sacrificial insulating layers 180 and 190 are partially removed by penetrating.

Referring to FIG. 1C, a dielectric layer (not shown) and a plate layer (upper electrode 240) are formed in regions of the etched sacrificial insulating layer. In this case, some plate layers 240 are stacked in the ferry region 1000c.

A second interlayer insulating layer 250 is formed on the entire surface including the plate layer 240.

Thereafter, a photosensitive film pattern (not shown) is formed by an exposure and development process using a metal wiring mask. The second interlayer insulating layer 250 is etched using the photoresist pattern as a mask to form a first metal wire 260 connected to the plate layer 240 and the second bit line 160 is exposed until the lower bit line 160 is exposed. The interlayer insulating layer 250, the second sacrificial insulating layer 190, the first sacrificial insulating layer 180, and the bit line hard mask layer 170 are etched to form a second metal wiring 270. At this time, during the etching process for forming the second metal wiring 270, a defect that cannot be etched until the lower bit line 160 is exposed due to the partial plate layer 240 stacked on the ferry region 1000c. And a short circuit between the plate layer 240 and the second metal wire 270 (see 'C' in FIG. 1C).

In order to solve the above-mentioned conventional problem, the present invention forms a barrier film that is connected to the lower electrode contact plug of the dummy cell region, so that the oxide film is removed by penetration of the dip-out solution into the ferry region during the dip-out during the subsequent process. In addition, the plate layer may be stacked on the removed region to prevent the lower bit line (MTO layer) from being exposed or the short circuit between the metal wiring and the penetrated plate layer during the etching process for connecting the metal wiring of the ferry region. And as a result provide a method of manufacturing a semiconductor device capable of improving the stability of a capacitor manufacturing process.

According to an embodiment of the present invention, a cell region, a dummy cell region, and a ferry region are provided, and a first sacrificial insulating film is formed on a semiconductor substrate including a contact plug, and when the contact plug of the dummy cell region and the ferry region is exposed. Etching the first sacrificial insulating film, and filling the insulating material to form a barrier film; forming a second sacrificial insulating film on the entire surface including the barrier film; until the barrier film and the contact plug are exposed. Etching the second and first sacrificial insulating layers to form a lower electrode region, forming a lower electrode in the lower electrode region, and removing the second and first sacrificial insulating layers using a dip out process, and then It provides a method of manufacturing a semiconductor device comprising forming a.

Preferably, forming an etch stop film between the contact plug and the first sacrificial insulating film.

Preferably, the method further includes forming a support layer and a third sacrificial insulating film on the second sacrificial insulating film.

Preferably, the barrier film is formed of a nitride film (Nitride).

Preferably, after the forming of the upper electrode, forming an interlayer insulating film on the entire surface including the upper electrode and using the metal wiring mask until the barrier film of the ferry region is exposed, the interlayer insulating film, the supporting layer and Etching the second sacrificial insulating film to form a first metal wiring, and etching the interlayer insulating film, the support layer, and the second and first sacrificial insulating films to form a second metal wiring.

Preferably, the support layer is characterized in that the NFC (Nitride Floating Cap) film.

The present invention forms a barrier film that is connected to the lower electrode contact plug of the dummy cell region, so that a dip-out solution penetrates into the ferry region during the dip out during the subsequent process, thereby removing the oxide layer, and stacking the plate layer on the removed region. The lower bit line (MTO layer) is not exposed during the etching process for connecting the metal wiring of the ferry region, or the short circuit between the metal wiring and the penetrated plate layer can be prevented, and as a result, the stability of the capacitor manufacturing process can be prevented. There is an advantage that can be improved.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. The present invention can also be applied to a reservoir capacitor formed in the ferry region 3000c in the same manner.

2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 2A, an isolation layer 320 defining an active region 310 is formed in a semiconductor substrate 300 having a cell region 3000a, a dummy cell region 3000b, and a ferry region 3000c.

Next, a gate pattern (not shown) including a gate oxide film, a gate conductive layer, and a gate hard mask layer is formed on the semiconductor substrate 300. In this case, the gate patterns of the cell region 3000a and the dummy cell region 3000b are not shown.

The first interlayer insulating layer 330 is formed on the entire surface including the gate pattern.

A photoresist film is formed on the first interlayer insulating layer 330, and a photoresist pattern (not shown) is formed by an exposure and development process using a contact plug mask.

The first interlayer insulating layer 330 is etched using the formed photoresist pattern to form a contact plug 340 for a storage node and a contact plug 350 for a bit line to expose the active region 310.

A bit line 360 connected to the bit line contact plug 350 is formed. In this case, the bit line 360 of the ferry region 3000c is called an MTO layer (metal layer), and the bit line 360 is formed when the bit line 360 is formed in the cell region 3000a and the dummy cell region 3000b. It can be formed at the same time. Here, a plurality of bit lines 360 are formed to be connected to the gate pattern 335 and to the active region 310.

Thereafter, the hard mask layer 370 for the bit line is formed on the entire surface including the bit line 360.

The first sacrificial insulating layer 380 is formed on the entire surface including the bit line hard mask layer 370.

Thereafter, a photoresist pattern (not shown) is formed by an exposure and development process using a barrier film forming mask of the dummy cell region 3000b and the ferry region 3000c.

Thereafter, the first sacrificial insulating layer 380 and the bit line hard mask layer 370 are etched using the photoresist pattern as a mask until the contact plug 340 for the storage node of the dummy cell region 3000b is exposed. After etching the first sacrificial insulating film until the bit line hard mask layer 370 of the region 3000c is exposed, the nitride film for forming the barrier film is buried, and chemical mechanical polishing is performed to etch the barrier film ( 385, 385 ').

Referring to FIG. 2B, the second sacrificial insulating layer 390, the support layer 400, and the third sacrificial insulating layer 410 are sequentially formed on the entire surface including the first sacrificial insulating layer 380. In this case, the support layer 400 refers to a NFC (Nitride Floating Cap) film, and preferably formed of a nitride film (Nitride).

A photoresist layer is formed on the third sacrificial insulating layer 410, and a photoresist pattern (not shown) is formed by an exposure and development process using a lower electrode mask.

The third sacrificial insulating film 410, the support layer 400, the second sacrificial insulating film 390, the first sacrificial insulating film 380 and the bit until the contact plug 340 for the storage node is exposed using the photoresist pattern as a mask. The line hard mask layer 370 is etched to form the lower electrode region 420. In this case, the dummy cell region 3000b may etch the third sacrificial insulating layer 410, the support layer 400, and the second sacrificial insulating layer 390 until the barrier layer 385 is exposed, thereby lowering the lower electrode region 420 ′. ). Due to the barrier layer 385, even if the lower electrode region 420 ′ of the dummy cell region 3000b is formed in a line type, penetration of a wet solution or the like of the ferry region 3000c during the subsequent process may be prevented. Can be.

Referring to FIG. 2C, after filling a conductive layer in the lower electrode regions 420 and 420 ′, the lower electrode 430 is formed by planarization etching.

After the lower electrode 430 is formed, a wet dip out process is performed to remove the second and first sacrificial insulating layers 390 and 380 of the cell region 3000a and the dummy cell region 3000b.

Subsequently, a dielectric film (not shown) and a plate layer (upper electrode 440) are formed in the etched sacrificial insulating layer. At this time, the plate layer 440 is stacked in the ferry region 3000c. Thereafter, the plate layer 440 of the ferry region 3000c is partially patterned.

Next, a second interlayer insulating film 450 is formed on the entire surface including the plate layer 440.

After forming a photoresist film on the second interlayer insulating film 450, a photoresist pattern (not shown) is formed by an exposure and development process using a metal wiring mask. The second interlayer insulating film 450, the plate layer 440, the support layer 400, and the second sacrificial insulating film, respectively, are exposed until the barrier film 385 ′ of the ferry region 3000c is exposed using a photoresist pattern as a mask. 390 is etched to form a first metal wire 460, and the second interlayer insulating layer 450, the plate layer 440, the support layer 400, and the second layer are exposed until the bit line 360 is exposed. The sacrificial insulating layer 390 is etched to form a second metal wire 470. Due to the barrier layer 385 ′, excessive etching is performed when the first metal wire 460 is formed to prevent the short-circuit with the bit line 360. In addition, the barrier layer 385 prevents the penetration of the wet solution into the ferry region 3000c during the wet deep-out process, so that the plate layer 440 and the second metal wiring 470 are shorted. The phenomenon can be prevented.

As described above, the present invention forms a barrier layer that is connected to the lower electrode contact plug of the dummy cell region, whereby a dip-out solution penetrates into the ferry region during the dip-out during the subsequent process, thereby removing the oxide layer and removing the region. The plate layer is stacked on the lower layer to prevent the lower bit line (MTO layer) from being exposed or the short circuit between the metal line and the infiltrated plate layer during the etching process for connecting the metal lines in the ferry region. There is an advantage that can improve the stability of the manufacturing process.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A to 1C are cross-sectional views illustrating problems of a method of manufacturing a semiconductor device in accordance with an embodiment of the prior art.

2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Claims (6)

Forming a first sacrificial insulating film on a semiconductor substrate including a cell region, a dummy cell region, and a ferry region, the contact plug including a contact plug; Etching the first sacrificial insulating film until the contact plugs of the dummy cell region and the ferry region are exposed, and then filling an insulating material to form a barrier film; Forming a second sacrificial insulating film on the entire surface including the barrier film; Etching the second and first sacrificial insulating layers to form a lower electrode region until the barrier layer and the contact plug are exposed; Forming a lower electrode in the lower electrode region; And Removing the second and first sacrificial insulating layers using a dip out process, and then forming an upper electrode Wherein the semiconductor device is a semiconductor device. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, And forming an etch stop layer between the contact plug and the first sacrificial insulating layer. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, Claim 4 was abandoned when the registration fee was paid. The method of claim 1, The barrier film is formed of a nitride film (Nitride), characterized in that the manufacturing method of a semiconductor device. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, After forming the upper electrode, Forming an interlayer insulating film on the entire surface including the upper electrode; And The interlayer insulating film and the second sacrificial insulating film are etched to form a first metal wiring until the barrier film of the ferry region is exposed using a metal wiring mask, and the interlayer insulating film, the second and first sacrificial insulating films are formed. Etching to form a second metal wire Wherein the semiconductor device is a semiconductor device. Claim 6 was abandoned when the registration fee was paid. The method of claim 3, wherein The support layer is a manufacturing method of a semiconductor device, characterized in that the NFC (Nitride Floating cap) film.

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