KR101080903B1 - High voltage transistor for a flash memory device - Google Patents

High voltage transistor for a flash memory device Download PDF

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KR101080903B1
KR101080903B1 KR1020060096076A KR20060096076A KR101080903B1 KR 101080903 B1 KR101080903 B1 KR 101080903B1 KR 1020060096076 A KR1020060096076 A KR 1020060096076A KR 20060096076 A KR20060096076 A KR 20060096076A KR 101080903 B1 KR101080903 B1 KR 101080903B1
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South Korea
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formed
high voltage
flash memory
film
conductive film
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KR1020060096076A
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Korean (ko)
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KR20080030246A (en
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김태균
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주식회사 하이닉스반도체
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Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage transistor of a flash memory device, comprising: a gate oxide film formed on a semiconductor substrate, a first conductive film formed on a gate oxide film, and a first conductive film formed on a semiconductor substrate, exposing a portion of the first conductive film, A high voltage transistor of a flash memory device comprising a dielectric film comprising a contact hole having an area larger than 80% of the conductive film area, a dielectric film, and a second conductive film formed on the exposed first conductive film.
Flash Memory, High Voltage Transistors, Dielectric Films, Contacts, Threshold Voltage

Description

High voltage transistor for a flash memory device

1 is a graph illustrating electrical characteristics of a high voltage transistor of a conventional flash memory device.

2 is a layout diagram illustrating a high voltage transistor of a flash memory device according to an exemplary embodiment of the present invention.

3 is a graph showing electrical characteristics according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: channel area 101: active area

102 gate 103 contact hole

The present invention relates to a high voltage transistor of a flash memory device, and more particularly to a high voltage transistor of a flash memory device for improving the electrical characteristics of the high voltage transistor.

The flash memory device is a memory device in which stored data is maintained even though power is not supplied. The flash memory device is classified into a NAND type and a NOR type. Unlike NOR flash, NAND flash is a memory device that reads data sequentially, and the memory cell array has a string structure in which a plurality of memory cells are connected side by side. Each string is connected with a high voltage transistor. The high voltage transistor is mainly used in a flash memory device during a program or erase operation and serves as a switch for passing or blocking a high voltage.

However, as the degree of integration decreases, the gap between devices decreases and the resistance of the select transistor gate increases, so that a predetermined region of the dielectric film (ONO film) of the select transistor and the peripheral region transistor is removed to form a contact hole. The transistor is formed by connecting the floating gate and the control gate through the contact hole. This dielectric film contact process can reduce the pitch size than before, which is useful for reducing the chip size of the device and reducing the resistance of the select transistor.

However, when a contact hole is formed by removing a predetermined region of the dielectric layer, a poly swell phenomenon occurs in the gate. When the poly swell phenomenon occurs, the center portion of the gate swells and is formed relatively higher than the edge portion. In a subsequent process, a nitride film is formed as an etch stop film on the gate, and an interlayer insulating film is formed to insulate the upper and lower layers. After the interlayer insulating film is formed, the upper portion of the interlayer insulating film is planarized by a chemical mechanical polishing (CMP) process, in which a nitrate in the center may be exposed or polished due to the inflated gate profile. Due to the poly swell phenomenon, not only an abnormal topology is formed, but also highly flowable ions such as Na + easily penetrate into the gate. Then, the transistor increases the leakage current, so that the fluctuation range of the threshold voltage is widened. This will be described with reference to FIG. 1.

1 is a graph illustrating electrical characteristics of a high voltage transistor of a conventional flash memory device. The graph A when no poly swell phenomenon has occurred and the graph B when a poly swell phenomenon have occurred are compared. The x-axis represents the threshold voltage (unit: V) and the y-axis represents the distribution (%). Therefore, as a graph showing the distribution of threshold voltages, when the poly swell phenomenon does not occur (A), the inclination angle of the threshold voltage distribution appears steeply. On the other hand, when the poly swell phenomenon occurs (B), the inclination angle of the threshold voltage distribution is lower than when the poly swell phenomenon does not occur. That is, in the case of the device in which the poly swell phenomenon occurs, the threshold voltage distribution is wide, so that the electrical characteristics are weak. This electrical degradation is particularly noticeable in high voltage transistors with low well concentrations, which also affects the erase and program operation of the memory cell, thereby lowering the reliability of the device.

Accordingly, an object of the present invention is to form a contact hole formed in the dielectric film therebetween as large as possible in the design rule to electrically connect the first conductive film for the floating gate and the second conductive film for the control gate. In a subsequent process, the fluorine ions generated during the formation of the conductive film are trapped inside the gate oxide film, thereby increasing the threshold voltage, thereby obtaining an excellent threshold voltage distribution of the high voltage transistor.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage transistor of a flash memory device. The present invention relates to a gate oxide film formed on a semiconductor, a first conductive film formed on a gate oxide film, and a contact hole formed on the first conductive film and exposing a portion of the first conductive film. A dielectric film comprising: a high voltage transistor of a flash memory device having a second conductive film formed on the dielectric film, wherein a distance between an edge of the contact hole and an edge of the second conductive film in a channel direction is smaller than a width of a second conductive film; do.

The distance between the edge of the contact hole and the edge of the channel region in the vertical direction of the channel direction is smaller than 10% of the width of the channel region.

The area of the contact hole is larger than 80% of the area of the dielectric film formed on the channel region and smaller than the total area.

The second conductive film is formed of tungsten silicide.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be embodied in various other forms, and only the present embodiments make the disclosure of the present invention complete and the scope of the invention to those skilled in the art. It is provided to inform you completely.

2 is a layout diagram illustrating a high voltage transistor of a flash memory device according to an exemplary embodiment of the present invention. After the process of isolating the device in manufacturing a high voltage transistor of a flash memory device, a gate 102 for forming a high voltage transistor is formed on the semiconductor substrate. The high voltage transistor is formed at the same time as the flash memory cell of the cell region. Although not shown, a method of forming the high voltage transistor is as follows.

A gate oxide film is formed over the semiconductor substrate. A first conductive film for a gate electrode is formed on the gate oxide film. A dielectric film is formed over the first conductive film to suppress the movement of electrons. The dielectric film is formed by sequentially stacking an oxide film-nitride-oxide (ONO film). In the cell region, the dielectric film blocks the floating gate and the control gate. However, since the floating gate and the control gate must be connected in the peripheral region, the contact region 103 is formed by etching a predetermined region of the dielectric film. A portion of the first conductive layer is exposed through the contact hole 103. Next, a second conductive film is formed over the entire structure. The second conductive film is also formed in the cell region, and is formed to form the gate of the transistor in the control gate or peripheral circuit region of the flash memory cell. In the peripheral circuit region, the second conductive layer is electrically connected to the lower first conductive layer through the contact hole 103 formed in the dielectric layer. Thereafter, the second conductive film, the dielectric film, and the first conductive film are patterned by an etching process to form a gate line. When the gate line is formed, a source / drain is formed in the active region 101 around the gate line.

In the above, the contact hole formed in the dielectric film is formed in the following form. The contact holes 103 formed in the dielectric film are formed in one wide pattern. More specifically, the distance W 'between the edge of the gate 102 and the edge of the contact hole 103 in the channel direction is smaller than 10% of the width W of the gate 102. The distance L ′ between the edge of the channel region 100 and the edge of the contact hole 103 in the vertical direction of the channel 100 is smaller than 10% of the width L of the channel region 100. Alternatively, the dielectric film contact holes 103 are formed in one wide pattern, but larger than about 80% of the total dielectric film area formed on the channel region 100.

On the other hand, after the source / drain is formed in the active region 101, a nitride film is formed along the gate pattern surface, and an interlayer insulating film is formed over the entire structure. The upper part of the interlayer insulating film is planarized by performing a chemical mechanical polishing process. Most of the nitride film formed on the gate is removed by the planarization process. This is because even if the dielectric film is etched at the center of the gate, the center portion of the gate is higher due to poly swell, so that the nitride film on the gate is mostly removed during the planarization process. Since the second conductive film formed under the nitride film may be damaged while the nitride film is removed, a third conductive film may be further formed on the second conductive film by using the same material as the second conductive film.

On the other hand, a florin gas is generated in the process of forming a conductive film on the dielectric film using a source gas containing a fluorine component. Florin gas is introduced into the gate oxide film so that fluorine ions are trapped in the gate oxide film, thereby increasing the thickness of the gate oxide film. As the thickness of the gate oxide film increases, the threshold voltage of the high voltage transistor increases, so that the distribution of the threshold voltage appears narrow.

3 is a graph showing electrical characteristics according to an embodiment of the present invention. The graph shows the characteristics of the threshold voltage distribution among the timely characteristics of the transistor fabricated by the present invention. The size of the high voltage NMOS transistor used for measuring electrical characteristics is 0.9 nm in width and 1.3 nm in length. Thus, the values in the graph may vary depending on the specifications of the device used for the measurement. The horizontal axis of the graph represents the threshold voltage (unit: V) of the high voltage transistor, and the new axis represents the distribution ratio (%) of the threshold voltage. Therefore, high inclination angle of the graph means that the distribution of threshold voltage is narrow, which also means that the electrical characteristics are good.

The graph includes a graph (D) in which a dielectric film contact (ONC) hole is formed when a poly swell phenomenon does not occur and a graph (C) in a case where a contact pattern proposed in the present invention is widely formed. First, when the graph (D) in which the poly swell phenomenon does not occur, the threshold voltage distribution is about 0.72 to 0.78V, which is excellent in electrical characteristics. In contrast, graph (C) of the present invention also shows excellent electrical characteristics with a threshold voltage distribution of about 0.73 to 0.7V. The reason why the distribution of the threshold voltage shows a sharp characteristic can be explained as follows.

In the manufacturing method of FIG. 2, a large contact hole area of the dielectric film is formed so that the upper part of the nitride film is largely removed in a subsequent process. Then, when a tungsten silicide (WSix) layer is formed as a subsequent gate electrode, fluorine gas is generated and flows into the gate oxide layer due to process characteristics. As a result, fluorine ions are trapped inside the gate oxide film to generate Si-F bonds. In general, when the florin gas flows into the oxide film, the thickness of the oxide film is increased. Therefore, the threshold voltage distribution lowered due to the increase in the thickness of the oxide film is increased, and as a result, the overall threshold voltage distribution is narrowly formed, thereby securing excellent electrical characteristics.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

According to the flash memory device manufacturing method described above, even if the degree of integration decreases, the dielectric film pattern may be easily formed, and the distribution width of the threshold voltage of the high voltage NMOS transistor may be narrowly formed, thereby stably improving the electrical characteristics.

Claims (4)

  1. A gate oxide film formed over the semiconductor substrate;
    A first conductive film formed on the gate oxide film; And
    And a dielectric layer formed on the first conductive layer, wherein the dielectric layer exposes a portion of the first conductive layer and has a contact hole having an area larger than 80% of the dielectric layer area.
  2. Claim 2 has been abandoned due to the setting registration fee.
    The method of claim 1,
    And a gap between the edge of the contact hole and the edge of the dielectric layer is less than 10% of the width of the region where the channel is to be formed.
  3. Claim 3 was abandoned when the setup registration fee was paid.
    The method of claim 1,
    The area of the contact hole is greater than 80% of the area of the dielectric film formed on the first conductive film and the high voltage transistor of the flash memory device narrower than the total area of the dielectric film including the contact hole.
  4. Claim 4 was abandoned when the registration fee was paid.
    The method of claim 1,
    And a second conductive layer formed over the contact hole and the dielectric layer and formed of tungsten silicide.
KR1020060096076A 2006-09-29 2006-09-29 High voltage transistor for a flash memory device KR101080903B1 (en)

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KR101080903B1 true KR101080903B1 (en) 2011-11-09

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100546202B1 (en) 1999-06-30 2006-01-24 주식회사 하이닉스반도체 Contact-forming method of the flash cell, this pirom
JP2006100409A (en) 2004-09-28 2006-04-13 Toshiba Corp Semiconductor device and its manufacturing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100546202B1 (en) 1999-06-30 2006-01-24 주식회사 하이닉스반도체 Contact-forming method of the flash cell, this pirom
JP2006100409A (en) 2004-09-28 2006-04-13 Toshiba Corp Semiconductor device and its manufacturing method

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