KR101078739B1 - Semiconductor package and stack semiconductor package having the same - Google Patents

Semiconductor package and stack semiconductor package having the same Download PDF

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KR101078739B1
KR101078739B1 KR1020090113230A KR20090113230A KR101078739B1 KR 101078739 B1 KR101078739 B1 KR 101078739B1 KR 1020090113230 A KR1020090113230 A KR 1020090113230A KR 20090113230 A KR20090113230 A KR 20090113230A KR 101078739 B1 KR101078739 B1 KR 101078739B1
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semiconductor
chip
pad
chip select
semiconductor package
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KR1020090113230A
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KR20110016371A (en
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민복규
김재면
나다운
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주식회사 하이닉스반도체
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Abstract

반도체 패키지 및 이를 갖는 적층 반도체 패키지가 개시되어 있다. 반도체 패키지는, 사각 플레이트 형상을 갖고, 4개의 모서리들 중 1개 이상 3개 이하의 상기 모서리들에 형성된 면취부를 갖는 반도체 칩, 상기 반도체 칩 상에 배치되며 상기 반도체 칩 내에 배치된 회로부와 전기적으로 연결된 데이터 본딩 패드들 및 상기 면취부가 형성되지 않은 상기 모서리에 배치되며 상기 회로부와 전기적으로 연결된 칩 선택 패드를 포함한다.A semiconductor package and a laminated semiconductor package having the same are disclosed. The semiconductor package has a rectangular plate shape and has a chamfer formed at one or more of three corners of the four corners, the semiconductor chip being electrically disposed on the semiconductor chip and electrically disposed on the semiconductor chip. And a chip select pad connected to the data bonding pads and the edge where the chamfer is not formed and electrically connected to the circuit unit.

Description

반도체 패키지 및 이를 갖는 적층 반도체 패키지{Semiconductor package and stack semiconductor package having the same}Semiconductor package and stack semiconductor package having the same

본 발명은 반도체 패키지 및 이를 갖는 적층 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package and a laminated semiconductor package having the same.

최근 들어, 방대한 데이터를 저장 및/또는 방대한 데이터를 단 시간 내 처리하는 것이 가능한 반도체 칩을 갖는 반도체 패키지가 개발된 바 있다.Recently, semiconductor packages having semiconductor chips capable of storing massive data and / or processing massive data in a short time have been developed.

또한, 최근에는 복수개의 반도체 칩들을 적층하여 데이터 저장 용량 및 데이터 처리 속도를 보다 향상시킨 적층 반도체 패키지가 개발되고 있다.In recent years, a multilayer semiconductor package has been developed in which a plurality of semiconductor chips are stacked to further improve data storage capacity and data processing speed.

적층 반도체 패키지를 구현하기 위해서는 적층된 복수개의 반도체 칩들 중 어느 하나의 반도체 칩을 선택하기 위한 칩 선택 기술을 필요로 한다.In order to implement the stacked semiconductor package, a chip selection technique for selecting any one of the plurality of stacked semiconductor chips is required.

특히, 동종의 반도체 칩들을 적층 할 경우, 적층된 반도체 칩들 중 특정 반도체 칩을 선택하기 어려운 문제점을 갖는다.In particular, when stacking the same kind of semiconductor chips, it is difficult to select a specific semiconductor chip among the stacked semiconductor chips.

본 발명은 적층된 복수개의 반도체 칩들 중 어느 하나를 선택하기에 적합한 반도체 패키지를 제공한다. The present invention provides a semiconductor package suitable for selecting any one of a plurality of stacked semiconductor chips.

또한, 본 발명은 적층된 복수개의 반도체 칩들 중 어느 하나를 선택하기에 적합한 반도체 패키지를 이용하여 구성한 적층 반도체 패키지를 제공한다. The present invention also provides a laminated semiconductor package constructed by using a semiconductor package suitable for selecting any one of a plurality of stacked semiconductor chips.

일 견지에서, 본 발명에 따른 반도체 패키지는, 4개의 모서리를 갖는 플레이트 형상을 갖고, 상기 4개의 모서리들 중 1개 이상 3개 이하의 모서리에 형성된 면취부(chamfering portion) 및 데이터를 처리하고 저장하는 회로부를 갖는 반도체 칩; 상기 반도체 칩 상에 배치되며 상기 회로부와 전기적으로 연결된 데이터 본딩 패드들; 및 상기 면취부가 형성되지 않은 나머지 모서리에 인접하게 배치되며 상기 회로부와 전기적으로 연결된 칩 선택 패드를 포함한다.In one aspect, the semiconductor package according to the present invention has a plate shape having four corners, and processes and stores chamfering portions and data formed at one or more of three corners of the four corners. A semiconductor chip having a circuit portion to make; Data bonding pads disposed on the semiconductor chip and electrically connected to the circuit unit; And a chip select pad disposed adjacent to the other corner where the chamfer is not formed and electrically connected to the circuit unit.

반도체 패키지의 상기 면취부 및 상기 면취부와 만나는 상기 반도체 칩의 에지는 둔각을 형성한다. The chamfer of the semiconductor package and the edge of the semiconductor chip which meets the chamfer form an obtuse angle.

반도체 패키지의 상기 면취부 및 상기 면취부와 만나는 상기 반도체 칩의 에지는 직각을 형성한다.The chamfer of the semiconductor package and the edge of the semiconductor chip which meets the chamfer form a right angle.

반도체 패키지의 상기 면취부는, 평면상에서 보았을 때, 오목한 곡선 형상을 갖는다.The chamfered portion of the semiconductor package has a concave curved shape when viewed in plan view.

반도체 패키지의 상기 칩 선택 패드는 면취부가 형성되지 않은 모서리에 적어도 2개가 인접하게 배치된다.At least two chip select pads of the semiconductor package are disposed adjacent to corners where the chamfers are not formed.

반도체 패키지는 상기 데이터 본딩 패드 및 상기 반도체 칩 중 상기 데이터 본딩 패드의 대응하는 위치를 관통하는 관통 전극을 더 포함한다.The semiconductor package further includes a through electrode penetrating a corresponding position of the data bonding pad and the data bonding pad of the semiconductor chip.

반도체 패키지의 상기 데이터 본딩 패드들은, 평면상에서 보았을 때, 정방 행렬(square matrix) 형상으로 형성되며, 상기 데이터 본딩 패드들 사이의 간격은 상호 동일하다.The data bonding pads of the semiconductor package, when viewed in plan view, are formed in a square matrix shape, and the spacing between the data bonding pads is the same.

다른 견지에서, 본 발명에 따른 적층 반도체 패키지는, 4개의 모서리를 갖는 플레이트 형상을 갖고, 상기 4개의 모서리들 중 1개 이상 3개 이하의 모서리에 형성된 면취부(chamfering portion) 및 데이터를 처리하고 저장하는 회로부를 갖는 반도체 칩, 상기 반도체 칩 상에 배치되며 상기 회로부와 전기적으로 연결된 데이터 본딩 패드들 및 상기 면취부가 형성되지 않은 나머지 모서리에 인접하게 배치되며 상기 회로부와 전기적으로 연결된 칩 선택 본딩 패드를 포함하는 복수 개의 반도체 패키지들을 포함하며, 상기 각 반도체 패키지들은 수직하게 적층되고, 평면상 상기 칩 선택 본딩 패드들은 이웃한 반도체 패키지들의 면취부에 의하여 노출되며, 상기 각 반도체 패키지들의 데이터 본딩 패드들은 상호 전기적으로 연결된다.
적층 반도체 패키지의 상기 각 반도체 패키지들은 상기 각 반도체 칩들을 관통하여 상기 각 반도체 칩들의 상기 데이터 본딩 패드들을 전기적으로 연결하는 관통 전극들을 포함한다.In another aspect, the laminated semiconductor package according to the present invention has a plate shape having four corners, and processes chamfering portions and data formed at one or three or less corners of the four corners. A semiconductor chip having a circuit portion to store the semiconductor chip, data bonding pads disposed on the semiconductor chip and electrically connected to the circuit portion, and a chip select bonding pad disposed adjacent to the other corner where the chamfer is not formed and electrically connected to the circuit portion. The semiconductor package includes a plurality of semiconductor packages, wherein each of the semiconductor packages is vertically stacked, and planar chip select bonding pads are exposed by chamfers of neighboring semiconductor packages, and data bonding pads of the semiconductor packages are mutually connected. Electrically connected.
Each of the semiconductor packages of the multilayer semiconductor package may include through electrodes electrically connecting the data bonding pads of the semiconductor chips through the semiconductor chips.

삭제delete

적층 반도체 패키지는 적층된 상기 반도체 패키지들이 실장되며 상기 각 관통 전극들과 접속되는 데이터 접속 패드들 및 상기 칩 선택 패드의 외곽에 상기 칩 선택 패드와 인접하게 배치된 칩 선택용 접속 패드를 포함하는 기판 및 상기 면취부를 통해 노출된 상기 칩 선택 패드 및 상기 칩 선택 패드와 대응하는 칩 선택용 패드를 전기적으로 연결하는 연결 부재를 더 포함한다.The multilayer semiconductor package may include a substrate on which the stacked semiconductor packages are mounted and including data connection pads connected to the through electrodes, and a chip selection connection pad disposed adjacent to the chip selection pad on an outer side of the chip selection pad. And a connection member electrically connecting the chip select pad exposed through the chamfer and the chip select pad corresponding to the chip select pad.

적층 반도체 패키지의 상기 칩 선택 패드는 이웃한 반도체 패키지의 면취부에 의하여 완전히 노출된다.The chip select pad of the multilayer semiconductor package is completely exposed by chamfers of neighboring semiconductor packages.

적층 반도체 패키지의 상기 칩 선택 패드는 이웃한 반도체 패키지의 면취부에 의하여 일부만 노출된다.The chip select pad of the multilayer semiconductor package is partially exposed by the chamfers of neighboring semiconductor packages.

적층 반도체 패키지의 상기 면취부 및 상기 면취부와 만나는 상기 각 반도체 패키지의 상기 반도체 칩의 에지는 둔각을 형성한다.The chamfer of the multilayer semiconductor package and the edge of the semiconductor chip of each semiconductor package which meets the chamfer form an obtuse angle.

적층 반도체 패키지의 상기 면취부 및 상기 면취부와 만나는 상기 각 반도체 패키지의 상기 반도체 칩의 에지는 직각을 형성한다.The chamfered portion of the multilayer semiconductor package and the edge of the semiconductor chip of each semiconductor package that meets the chamfer form a right angle.

적층 반도체 패키지의 상기 면취부는, 평면상에서 보았을 때, 상기 칩 선택 패드를 노출하기 위해 오목한 곡선 형상을 갖는다.The chamfered portion of the laminated semiconductor package has a concave curved shape to expose the chip select pad when viewed in plan view.

적층 반도체 패키지의 상기 칩 선택 패드는 상기 제2 모서리 그룹에 적어도 2개가 배치되고, 상기 칩 선택용 본딩 패드들은 상기 칩 선택용 본딩 패드들의 개수에 대응하는 개수를 갖는다.At least two chip selection pads of the multilayer semiconductor package may be disposed in the second corner group, and the chip selection bonding pads may have a number corresponding to the number of the chip selection bonding pads.

적층 반도체 패키지의 상기 데이터 본딩 패드들은, 평면상에서 보았을 때, 정방 행렬(square matrix) 형상으로 형성되며, 상기 데이터 본딩 패드들 사이의 간격은 상호 동일하다.The data bonding pads of the multilayer semiconductor package are formed in a square matrix shape when viewed in plan view, and the spacing between the data bonding pads is the same.

적층 반도체 패키지의 상기 각 반도체 패키지들의 상기 각 반도체 칩들은 상 기 칩 선택 패드를 기준으로 상호 90°간격으로 회전된 상태로 적층된다.The semiconductor chips of the semiconductor packages of the stacked semiconductor package are stacked in a state of being rotated at a 90 ° interval with respect to the chip selection pad.

본 발명은 반도체 칩의 일부를 절단 또는 제거하고 반도체 칩 중 제거된 부분을 이용하여 도전성 와이어로 반도체 패키지와 기판을 연결함으로써 복수개의 반도체 패키지들 중 특정 반도체를 쉽게 선택할 수 있다.The present invention can easily select a specific semiconductor from among a plurality of semiconductor packages by cutting or removing a portion of the semiconductor chip and connecting the semiconductor package and the substrate with a conductive wire using the removed portion of the semiconductor chip.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명의 일실시예에 따른 반도체 패키지를 도시한 평면도이다.1 is a plan view illustrating a semiconductor package according to an embodiment of the present invention.

도 1을 참조하면, 반도체 패키지(100)는 반도체 칩(10), 데이터 본딩 패드(20)들 및 칩 선택 패드(30)를 포함한다.Referring to FIG. 1, the semiconductor package 100 includes a semiconductor chip 10, data bonding pads 20, and a chip select pad 30.

반도체 칩(10)은, 예를 들어, 사각 플레이트 형상을 갖는다. 본 실시예에서, 반도체 칩(10)이 사각 플레이트 형상을 갖는 것이 도시 및 설명되고 있지만, 이와 다르게 반도체 칩(10)은 사각 플레이트 형상 대신 다양한 형상을 가질 수 있다. 예를 들어, 반도체 칩(10)은 삼각 플레이트 또는 5각 플레이트 형상을 가질 수 있다.The semiconductor chip 10 has a square plate shape, for example. In the present embodiment, although the semiconductor chip 10 has a rectangular plate shape, it is illustrated and described. Alternatively, the semiconductor chip 10 may have various shapes instead of the rectangular plate shape. For example, the semiconductor chip 10 may have a triangular plate or a pentagonal plate shape.

반도체 칩(10)은 데이터를 처리하기 위한 데이터 처리부(미도시), 데이터를 저장하기 위한 데이터 저장부(미도시)를 갖는 회로부를 포함한다.The semiconductor chip 10 includes a circuit unit having a data processing unit (not shown) for processing data and a data storage unit (not shown) for storing data.

사각 플레이트 형상을 갖는 반도체 칩(10)은, 평면상에서 보았을 때, 4개의 모서리(corner, 1,2,3,4)들을 갖는다. 이하, 본 실시예에서는, 예를 들어, 3개의 모서리들을 제1 모서리 그룹(1,2,3)으로서 정의하기로 하고, 제1 모서리 그 룹(1,2,3)에 포함되지 않은 나머지 하나의 모서리(4)를 제2 모서리 그룹(4)으로서 정의하기로 한다. 본 실시예에서, 제1 모서리 그룹은 1개 내지 3개의 모서리를 포함할 수 있다.The semiconductor chip 10 having a rectangular plate shape has four corners 1,2,3,4 when viewed in plan view. Hereinafter, in the present embodiment, for example, three corners will be defined as the first corner group (1, 2, 3), and the other one not included in the first corner group (1, 2, 3). The edge 4 of the is defined as the second corner group 4. In this embodiment, the first corner group may include one to three corners.

반도체 칩(10)의 제1 모서리 그룹(1,2,3)에는 각각 면취부(chamfering portion, 12)가 형성된다.Chamfering portions 12 are formed in the first corner groups 1, 2, and 3 of the semiconductor chip 10, respectively.

본 실시예에서, 제1 모서리 그룹(1,2,3)에 각각 형성된 면취부(12)는 반도체 칩(10)의 모서리를, 평면상에서 보았을 때, 삼각형 형상으로 절단한 형상을 갖고, 이로 인해, 상기 면취부(12) 및 면취부(12)와 만나는 반도체 칩(10)의 에지들은 둔각(θ1)으로 형성된다.In the present embodiment, the chamfered portions 12 formed in the first corner groups 1, 2, and 3 respectively have a shape in which the edges of the semiconductor chips 10 are cut into triangular shapes when viewed in plan view, thereby The edges of the semiconductor chip 10 that meet the chamfer 12 and the chamfer 12 are formed at an obtuse angle θ1.

도 2에 도시된 바와 같이 제1 모서리 그룹(1,2,3)에 각각 형성된 면취부(12)는 반도체 칩(10)의 모서리를, 평면상에서 보았을 때, 사각형 형상으로 절단한 형상을 갖고, 이로 인해, 상기 면취부(12) 및 면취부(12)와 만나는 반도체 칩(10)의 에지들은 각각 직각(θ2)으로 형성된다.As shown in FIG. 2, the chamfered portions 12 formed in the first edge groups 1, 2, and 3 respectively have a shape in which the edges of the semiconductor chips 10 are cut into a rectangular shape when viewed in plan view. As a result, edges of the semiconductor chip 10 that meet the chamfer 12 and the chamfer 12 are formed at right angles θ2, respectively.

도 3에 도시된 바와 같이 제1 모서리 그룹(1,2,3)에 각각 형성된 면취부(12)는 반도체 칩(10)의 모서리를, 평면상에서 보았을 때, 오목한 곡면 형상으로 절단한 형상을 가질 수 있다.As shown in FIG. 3, the chamfered portions 12 formed in the first edge groups 1, 2, and 3, respectively, have a shape in which the edges of the semiconductor chips 10 are cut into concave curved shapes when viewed in plan view. Can be.

도 1을 다시 참조하면, 데이터 본딩 패드(20)들은 반도체 칩(10)의 상면 또는 상면과 대향 하는 하면의 중앙부에 1열 또는 2열로 형성될 수 있다. 이와 다르게, 데이터 본딩 패드(20)는 반도체 칩(10)의 상기 상면 또는 상기 하면의 에지를 따라 1열 또는 2열로 형성될 수 있다. 데이터 본딩 패드(20)는 반도체 칩(10)의 회 로부와 전기적으로 연결된다.Referring back to FIG. 1, the data bonding pads 20 may be formed in one or two rows at the center of the top surface or the bottom surface of the semiconductor chip 10 opposite to the top surface. Alternatively, the data bonding pads 20 may be formed in one or two rows along an edge of the upper surface or the lower surface of the semiconductor chip 10. The data bonding pad 20 is electrically connected to the circuit portion of the semiconductor chip 10.

바람직하게, 데이터 본딩 패드(20)들은 반도체 칩(10)의 상면 또는 상면과 대향 하는 하면의 중앙부에 정방 행렬(square matrix) 형태로 배치될 수 있다. 정방 행렬 형태로 배치된 데이터 본딩 패드(20)들은 상호 동일한 형상 및 동일한 간격으로 형성된다.Preferably, the data bonding pads 20 may be disposed in the form of a square matrix at the center of the top surface or the bottom surface of the semiconductor chip 10 opposite to the top surface. The data bonding pads 20 arranged in the form of a square matrix are formed in the same shape and at the same intervals.

본 실시예에서, 반도체 칩(10)은 데이터 본딩 패드(20) 및 반도체 칩(10) 중 데이터 본딩 패드(20)와 대응하는 위치를 관통하는 관통 전극(25)을 포함한다.In the present embodiment, the semiconductor chip 10 includes a data bonding pad 20 and a through electrode 25 penetrating a position corresponding to the data bonding pad 20 in the semiconductor chip 10.

관통 전극(25)은 데이터 본딩 패드(20) 및 반도체 칩(10)을 순차적으로 관통하고, 관통 전극(25)의 양쪽 단부들 중 적어도 하나에는 솔더와 같은 접속 부재가 배치될 수 있다.The through electrode 25 sequentially penetrates the data bonding pad 20 and the semiconductor chip 10, and a connection member such as solder may be disposed on at least one of both ends of the through electrode 25.

칩 선택 패드(30)는 반도체 칩(10)의 상기 상면 상에 배치된다. 칩 선택 패드(30)는 면취부(12)가 형성되지 않은 반도체 칩(10)의 제2 모서리 그룹(4)에 인접하게 배치된다. 칩 선택 패드(30)는 반도체 칩(10)의 회로부와 전기적으로 연결된다. 칩 선택 패드(30)로는 반도체 칩을 선택하기 위한 칩 선택 신호가 입력된다.The chip select pad 30 is disposed on the top surface of the semiconductor chip 10. The chip select pad 30 is disposed adjacent to the second edge group 4 of the semiconductor chip 10 where the chamfer 12 is not formed. The chip select pad 30 is electrically connected to a circuit portion of the semiconductor chip 10. A chip select signal for selecting a semiconductor chip is input to the chip select pad 30.

본 실시예에서, 칩 선택 패드(30)는, 도 4에 도시된 바와 같이, 제2 모서리 그룹(4)에 인접하게 적어도 2개가 배치될 수 있다.In the present embodiment, at least two chip select pads 30 may be disposed adjacent to the second corner group 4 as shown in FIG. 4.

도 5는 도 1에 도시된 반도체 패키지를 이용한 적층 반도체 패키지를 도시한 단면도이고, 도 6는 도 5의 적층 반도체 패키지의 평면도이다.5 is a cross-sectional view illustrating a multilayer semiconductor package using the semiconductor package illustrated in FIG. 1, and FIG. 6 is a plan view of the multilayer semiconductor package of FIG. 5.

도 5 및 도 6을 참조하면, 적층 반도체 패키지(200)는 복수개의 반도체 패키지(100)들을 포함한다. 본 실시예에서, 적층 반도체 패키지(200)는, 예를 들어, 4 개의 반도체 패키지(100), 연결 부재(60), 기판(70) 및 몰딩 부재(80)를 포함한다.5 and 6, the multilayer semiconductor package 200 includes a plurality of semiconductor packages 100. In the present embodiment, the laminated semiconductor package 200 includes, for example, four semiconductor packages 100, a connection member 60, a substrate 70, and a molding member 80.

각 반도체 패키지(100)들은 면취부(12)가 형성된 모서리들을 갖는 제1 모서리 그룹(1,2,3) 및 면취부(12)가 형성되지 않은 모서리를 갖는 제2 모서리 그룹(4)을 갖는 반도체 칩(10), 데이터 본딩 패드(20) 및 칩 선택 패드(30)를 포함한다.Each semiconductor package 100 has a first corner group 1, 2, 3 having corners with the chamfer 12 formed therein, and a second corner group 4 with a corner where the chamfer 12 is not formed. The semiconductor chip 10 includes a data bonding pad 20 and a chip select pad 30.

본 실시예에서, 제1 모서리 그룹(1,2,3)에 각각 형성된 면취부(12)들은 반도체 칩(10)의 모서리를, 평면상에서 보았을 때, 삼각형 형상으로 절단한 형상을 갖고, 이로 인해, 상기 면취부(12) 및 면취부(12)와 만나는 반도체 칩(10)의 에지들은 둔각으로 형성될 수 있다. 이와 다르게, 제1 모서리 그룹(1,2,3)에 각각 형성된 면취부(12)들은 반도체 칩(10)의 모서리를, 평면상에서 보았을 때, 사각형 형상으로 절단한 형상을 갖고, 이로 인해 면취부(12) 및 면취부(12)와 만나는 반도체 칩(10)의 에지들은 각각 직각으로 형성될 수 있다. 이와 다르게, 제1 모서리 그룹(1,2,3)에 각각 형성된 면취부(12)들은 반도체 칩(10)의 모서리를, 평면상에서 보았을 때, 오목한 곡면 형상으로 절단한 형상을 가질 수 있다.In the present embodiment, the chamfered portions 12 formed in the first edge groups 1, 2, and 3 respectively have a shape in which the edges of the semiconductor chips 10 are cut in a triangular shape when viewed in plan view, thereby The edges of the semiconductor chip 10 that meet the chamfer 12 and the chamfer 12 may be formed at an obtuse angle. In contrast, the chamfered portions 12 formed in the first edge groups 1, 2, and 3, respectively, have a shape in which the edges of the semiconductor chip 10 are cut into a rectangular shape when viewed in plan view, thereby chamfering portions Edges of the semiconductor chip 10 that meet the chamfer 12 and the chamfer 12 may be formed at right angles, respectively. Alternatively, the chamfered portions 12 formed in the first edge groups 1, 2, and 3 may have shapes in which the edges of the semiconductor chip 10 are cut into concave curved shapes when viewed in plan view.

데이터 본딩 패드(25)들은 각 반도체 패키지(100)들의 각 반도체 칩(10)의 상면 중앙부에 정방 행렬 형태로 배치될 수 있고, 칩 선택 패드(30)는 제2 모서리 그룹(4)에 배치된다. 칩 선택 패드(30)는 적어도 2개가 제2 모서리 그룹(4)에 배치될 수 있다.The data bonding pads 25 may be disposed in the shape of a square matrix at the center of the upper surface of each semiconductor chip 10 of each of the semiconductor packages 100, and the chip selection pads 30 may be disposed in the second corner group 4. . At least two chip select pads 30 may be disposed in the second corner group 4.

본 실시예에서는, 예를 들어, 4개의 반도체 패키지(100)들이 상호 수직한 방향으로 적층 되며, 4개의 반도체 패키지(100)들을 적층 할 때, 평면에서 볼 때 하부에 배치된 반도체 패키지(100)의 칩 선택 패드(30)는 상부에 배치되는 반도체 패키지(100)의 면취부(12)에 의하여 외부에 노출된다. 이를 구현하기 위하여, 4개의 반도체 패키지(100)들은 적층 될 때, 각각의 칩 선택 패드(30)가 이웃한 반도체 패키지의 칩 선택 패드와 상호 90°각도로 회전된 상태로 적층되는 것이 바람직하다.In the present embodiment, for example, four semiconductor packages 100 are stacked in a direction perpendicular to each other, and when the four semiconductor packages 100 are stacked, the semiconductor package 100 disposed below in a plan view. The chip select pad 30 is exposed to the outside by the chamfer 12 of the semiconductor package 100 disposed thereon. In order to implement this, when the four semiconductor packages 100 are stacked, it is preferable that each chip select pad 30 is stacked in a state of being rotated by 90 ° with the chip select pads of the neighboring semiconductor packages.

본 실시예에서, 하부에 배치된 반도체 패키지(100)의 제2 모서리 그룹(4) 및 상부에 배치된 반도체 패키지(100)의 제2 모서리 그룹(4)은 상호 일치하지 않게 배치되고, 하부에 배치된 반도체 패키지(100)의 제2 모서리 그룹(4)은 상부에 배치된 반도체 패키지(100)의 제1 모서리 그룹(1,2,3)들 중 어느 하나와 정렬된다.In the present embodiment, the second corner group 4 of the semiconductor package 100 disposed below and the second corner group 4 of the semiconductor package 100 disposed above are arranged so as not to coincide with each other. The second corner group 4 of the semiconductor package 100 disposed is aligned with any one of the first corner groups 1, 2 and 3 of the semiconductor package 100 disposed thereon.

본 실시예에서, 적층된 4 개의 반도체 패키지(100)들의 칩 선택 패드(30)는, 도 6에 도시된 바와 같이, 평면상 다른 반도체 패키지의 면취부(12)에 의하여 완전히 노출될 수 있다. 이와 다르게, 적층된 4개의 반도체 패키지(100)들의 칩 선택 패드(30)의 일부만이 다른 반도체 패키지의 면취부(12)에 의하여 노출되어도 무방하다.In the present embodiment, the chip select pads 30 of the four stacked semiconductor packages 100 may be completely exposed by the chamfers 12 of other semiconductor packages on a plane, as shown in FIG. 6. Alternatively, only a part of the chip select pads 30 of the four stacked semiconductor packages 100 may be exposed by the chamfers 12 of the other semiconductor packages.

한편, 적층된 4개의 반도체 패키지(100)들에 포함된 각 관통 전극(25)들은 상호 솔더와 같은 접속 부재(27)에 의하여 전기적으로 연결되고, 적층된 4개의 반도체 패키지(100)들은 기판(70)에 실장된다.Meanwhile, the through electrodes 25 included in the four stacked semiconductor packages 100 are electrically connected to each other by a connection member 27 such as solder, and the four stacked semiconductor packages 100 may be formed of a substrate ( 70).

기판(70)은 몸체(71), 칩 선택용 접속 패드(72), 데이터 접속 패드(74), 볼 랜드(76) 및 솔더볼(78)을 포함한다.The substrate 70 includes a body 71, a chip selection connection pad 72, a data connection pad 74, a ball land 76 and a solder ball 78.

몸체(71)는 플레이트 형상을 갖고, 몸체(71)의 상면 상에는 적층된 4개의 반도체 패키지(100)들이 배치된다.The body 71 has a plate shape and four semiconductor packages 100 stacked on the upper surface of the body 71 are disposed.

데이터 접속 패드(74)는 몸체(71)의 상면 상에 배치되며, 데이터 접속 패드(74)는 반도체 패키지(100)의 관통 전극(25)들과 전기적으로 연결된다.The data connection pad 74 is disposed on an upper surface of the body 71, and the data connection pad 74 is electrically connected to the through electrodes 25 of the semiconductor package 100.

칩 선택용 접속 패드(72)는 몸체(71)의 상면 상에 배치되며, 칩 선택용 접속 패드(72)는 적층된 반도체 패키지(100)의 외곽에 배치된다. 칩 선택용 접속 패드(72)는 각 반도체 패키지(100)의 각 반도체 칩(10)에 형성된 칩 선택 패드(30)와 인접한 위치에 배치된다.The chip selection connection pad 72 is disposed on an upper surface of the body 71, and the chip selection connection pad 72 is disposed outside the stacked semiconductor package 100. The chip select connection pad 72 is disposed at a position adjacent to the chip select pad 30 formed on each semiconductor chip 10 of each semiconductor package 100.

볼 랜드(76)들은 몸체(71)의 하면에 배치되며, 볼 랜드(76)들은 데이터 접속 패드(74) 및 칩 선택용 접속 패드(72)와 전기적으로 연결되고, 솔더볼(78)들은 각 볼 랜드(76)와 전기적으로 접속된다.The ball lands 76 are disposed on the lower surface of the body 71, and the ball lands 76 are electrically connected to the data connection pad 74 and the chip selection connection pad 72, and the solder balls 78 are connected to each ball. It is electrically connected to the land 76.

연결 부재(60)는 각 반도체 패키지(100)의 칩 선택 패드(30) 및 기판(70)의 칩 선택용 접속 패드(72)를 전기적으로 연결한다. 본 실시예에서, 연결 부재(60)는, 예를 들어, 실 형상을 갖는 본딩 와이어이다.The connection member 60 electrically connects the chip select pad 30 of each semiconductor package 100 and the chip select connection pad 72 of the substrate 70. In this embodiment, the connecting member 60 is, for example, a bonding wire having a thread shape.

본 실시예에서, 본딩 와이어와 같은 연결 부재(60)에 의하여 칩 선택용 접속 패드(72) 및 칩 선택 패드(30)를 와이어 본딩 할 때, 특정 반도체 패키지의 칩 선택 패드(30)는 그 이외의 반도체 패키지의 면취부(12)에 의하여 노출되기 때문에 쉽게 와이어 본딩이 가능할 뿐만 아니라 반도체 패키지(100)들 사이에 스페이서를 배치하지 않아도 되기 때문에 반도체 패키지의 부피를 크게 감소시킬 수 있다.In the present embodiment, when wire bonding the chip select connecting pad 72 and the chip select pad 30 by a connecting member 60 such as a bonding wire, the chip select pad 30 of the specific semiconductor package is other than that. Since the semiconductor package is exposed by the chamfer 12 of the semiconductor package, not only wire bonding is possible but also the spacers are not disposed between the semiconductor packages 100, thereby greatly reducing the volume of the semiconductor package.

본 실시예에서, 연결 부재(60)를 통해 각 반도체 패키지(100)에 칩 선택 신호를 제공함으로써 복수개의 반도체 패키지(100)들로부터 특정 반도체 패키지(100)를 선택할 수 있다.In the present exemplary embodiment, the specific semiconductor package 100 may be selected from the plurality of semiconductor packages 100 by providing a chip select signal to each semiconductor package 100 through the connection member 60.

한편, 몰딩 부재(80)는 적층된 4 개의 반도체 패키지(100)들, 기판(100)의 상면 및 연결 부재(60)를 감싼다. 몰딩 부재(80)는 외부로부터 인가된 충격 및/또 는 진동으로부터 적층된 반도체 패키지(100)들, 연결 부재(60)를 보호한다.Meanwhile, the molding member 80 surrounds four stacked semiconductor packages 100, an upper surface of the substrate 100, and a connection member 60. The molding member 80 protects the stacked semiconductor packages 100 and the connection member 60 from shocks and / or vibrations applied from the outside.

이상에서 상세하게 설명한 바와 같이, 본 발명은 반도체 칩의 일부를 절단 또는 제거하고 반도체 칩 중 제거된 부분을 이용하여 도전성 와이어로 반도체 패키지와 기판을 연결함으로써 복수개의 반도체 패키지들 중 특정 반도체를 쉽게 선택할 수 있는 효과를 갖는다.As described in detail above, the present invention can easily select a specific semiconductor from among a plurality of semiconductor packages by cutting or removing a portion of the semiconductor chip and connecting the semiconductor package and the substrate with a conductive wire using the removed portion of the semiconductor chip. Has the effect.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다. As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

도 1은 본 발명의 일실시예에 따른 반도체 패키지를 도시한 평면도이다.1 is a plan view illustrating a semiconductor package according to an embodiment of the present invention.

도 2는 본 발명의 다른 실시예에 따른 반도체 패키지의 평면도이다.2 is a plan view of a semiconductor package according to another embodiment of the present invention.

도 3은 본 발명의 또 다른 실시예에 따른 반도체 패키지의 평면도이다.3 is a plan view of a semiconductor package according to another embodiment of the present invention.

도 4는 본 발명의 또 다른 실시예에 따른 반도체 패키지의 평면도이다.4 is a plan view of a semiconductor package according to still another embodiment of the present invention.

도 5는 본 발명의 일실시예에 따른 적층 반도체 패키지를 도시한 단면도이다.5 is a cross-sectional view illustrating a multilayer semiconductor package according to an embodiment of the present invention.

도 6은 도 5의 적층 반도체 패키지의 평면도이다.6 is a plan view of the multilayer semiconductor package of FIG. 5.

Claims (18)

4개의 모서리를 갖는 플레이트 형상을 갖고, 상기 4개의 모서리들 중 1개 이상 3개 이하의 모서리에 형성된 면취부(chamfering portion) 및 데이터를 처리하고 저장하는 회로부를 갖는 반도체 칩;A semiconductor chip having a plate shape having four corners, and having a chamfering portion formed at one or more three or less corners of the four corners and a circuit unit for processing and storing data; 상기 반도체 칩 상에 배치되며 상기 회로부와 전기적으로 연결된 데이터 본딩 패드들; 및Data bonding pads disposed on the semiconductor chip and electrically connected to the circuit unit; And 상기 면취부가 형성되지 않은 나머지 모서리에 인접하게 배치되며 상기 회로부와 전기적으로 연결된 칩 선택 패드;A chip select pad disposed adjacent to the other corner where the chamfer is not formed and electrically connected to the circuit unit; 를 포함하는 반도체 패키지.Semiconductor package comprising a. 제 1 항에 있어서, The method of claim 1, 상기 면취부 및 상기 면취부와 만나는 상기 반도체 칩의 에지는 둔각을 형성하는 것을 특징으로 하는 반도체 패키지.And the edge of the semiconductor chip which meets the chamfer and the chamfer forms an obtuse angle. 제 1 항에 있어서, The method of claim 1, 상기 면취부 및 상기 면취부와 만나는 상기 반도체 칩의 에지는 직각을 형성하는 것을 특징으로 하는 반도체 패키지.And the edge of the semiconductor chip which meets the chamfer and the chamfer forms a right angle. 제 1 항에 있어서, The method of claim 1, 상기 면취부는, 평면상에서 보았을 때, 오목한 곡선 형상을 갖는 것을 특징으로 하는 반도체 패키지.The chamfered portion has a concave curved shape when viewed in plan view. 제 1 항에 있어서,The method of claim 1, 상기 칩 선택 패드는 면취부가 형성되지 않은 모서리에 적어도 2개가 인접하게 배치된 것을 특징으로 하는 반도체 패키지.And at least two chip select pads are disposed adjacent to corners where the chamfer is not formed. 제 1 항에 있어서,The method of claim 1, 상기 데이터 본딩 패드 및 상기 반도체 칩 중 상기 데이터 본딩 패드의 대응하는 위치를 관통하는 관통 전극을 더 포함하는 것을 특징으로 하는 반도체 패키지.And a through electrode penetrating a corresponding position of the data bonding pad and the data bonding pad among the semiconductor chips. 제 1 항에 있어서,The method of claim 1, 상기 데이터 본딩 패드들은, 평면상에서 보았을 때, 정방 행렬(square matrix) 형상으로 형성되며, 상기 데이터 본딩 패드들 사이의 간격은 상호 동일한 것을 특징으로 하는 반도체 패키지.The data bonding pads are formed in a square matrix shape when viewed in plan view, and the spacing between the data bonding pads is the same. 4개의 모서리를 갖는 플레이트 형상을 갖고, 상기 4개의 모서리들 중 1개 이상 3개 이하의 모서리에 형성된 면취부(chamfering portion) 및 데이터를 처리하고 저장하는 회로부를 갖는 반도체 칩, 상기 반도체 칩 상에 배치되며 상기 회로부와 전기적으로 연결된 데이터 본딩 패드들 및 상기 면취부가 형성되지 않은 나머지 모서리에 인접하게 배치되며 상기 회로부와 전기적으로 연결된 칩 선택 패드를 포함하는 복수 개의 반도체 패키지들을 포함하며,A semiconductor chip having a plate shape having four corners, and having a chamfering portion formed at one or more three or less corners of the four corners and a circuit portion for processing and storing data, on the semiconductor chip. A plurality of semiconductor packages, the plurality of semiconductor packages being disposed adjacent to the data bonding pads electrically connected to the circuit unit and the remaining corners of the chamfered portion, the chip select pads being electrically connected to the circuit unit. 상기 각 반도체 패키지들은 수직하게 적층되고, 평면상 상기 칩 선택 패드들은 이웃한 반도체 패키지들의 면취부에 의하여 노출되며, 상기 각 반도체 패키지들의 데이터 본딩 패드들은 상호 전기적으로 연결된 것을 특징으로 하는 적층 반도체 패키지.Wherein each of the semiconductor packages is vertically stacked, and planar chip select pads are exposed by chamfers of neighboring semiconductor packages, and data bonding pads of the semiconductor packages are electrically connected to each other. 제 8 항에 있어서,The method of claim 8, 상기 각 반도체 패키지들은 상기 각 반도체 칩들을 관통하여 상기 각 반도체 칩들의 상기 데이터 본딩 패드들을 전기적으로 연결하는 관통 전극들을 포함하는 것을 특징으로 하는 적층 반도체 패키지. And each of the semiconductor packages includes through electrodes electrically connecting the data bonding pads of the semiconductor chips through the semiconductor chips. 제 9 항에 있어서,The method of claim 9, 적층된 상기 반도체 패키지들이 실장되며 상기 각 관통 전극들과 접속되는 데이터 접속 패드들 및 상기 칩 선택 패드의 외곽에 상기 칩 선택 패드와 인접하게 배치된 칩 선택용 접속 패드를 포함하는 기판; 및A substrate on which the semiconductor packages stacked are mounted and including data connection pads connected to the through electrodes, and a chip selection connection pad disposed adjacent to the chip selection pad outside the chip selection pad; And 상기 면취부를 통해 노출된 상기 칩 선택 패드 및 상기 칩 선택 패드와 대응하는 칩 선택용 접속 패드를 전기적으로 연결하는 연결 부재;A connection member electrically connecting the chip select pad exposed through the chamfer and the chip select connection pad corresponding to the chip select pad; 를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지.Laminated semiconductor package, characterized in that it further comprises. 제 8 항에 있어서,The method of claim 8, 상기 칩 선택 패드는 이웃한 반도체 패키지의 면취부에 의하여 완전히 노출되는 것을 특징으로 하는 적층 반도체 패키지.And the chip select pad is completely exposed by chamfers of neighboring semiconductor packages. 제 8 항에 있어서,The method of claim 8, 상기 칩 선택 패드는 이웃한 반도체 패키지의 면취부에 의하여 일부분만 노출되는 것을 특징으로 하는 적층 반도체 패키지.And the chip select pad is partially exposed by chamfers of neighboring semiconductor packages. 제 8 항에 있어서,The method of claim 8, 상기 면취부 및 상기 면취부와 만나는 상기 각 반도체 패키지의 상기 반도체 칩의 에지는 둔각을 형성하는 것을 특징으로 하는 적층 반도체 패키지.The chamfered portion and the edge of the semiconductor chip of each semiconductor package that meets the chamfered portion is a laminated semiconductor package, characterized in that forming an obtuse angle. 제 8 항에 있어서,The method of claim 8, 상기 면취부 및 상기 면취부와 만나는 상기 각 반도체 패키지의 상기 반도체 칩의 에지는 직각을 형성하는 것을 특징으로 하는 적층 반도체 패키지.The chamfered portion and the edge of the semiconductor chip of each semiconductor package that meets the chamfered portion is a laminated semiconductor package, characterized in that forming a right angle. 제 8 항에 있어서,The method of claim 8, 상기 면취부는, 평면상에서 보았을 때, 상기 칩 선택 패드를 노출하기 위해 오목한 곡선 형상을 갖는 것을 특징으로 하는 적층 반도체 패키지.The chamfered portion has a concave curved shape to expose the chip select pad when viewed in plan view. 제 10 항에 있어서,11. The method of claim 10, 상기 칩 선택 패드는 상기 면취부가 형성되지 않은 모서리에 적어도 2개가 인접하게 배치되고, 상기 칩 선택용 접속 패드들은 상기 칩 선택 패드들의 개수에 대응하는 개수를 갖는 것을 특징으로 하는 적층 반도체 패키지.At least two chip select pads are disposed adjacent to corners where the chamfers are not formed, and the chip select connection pads have a number corresponding to the number of the chip select pads. 제 8 항에 있어서,The method of claim 8, 상기 데이터 본딩 패드들은, 평면상에서 보았을 때, 정방 행렬(square matrix) 형상으로 형성되며, 상기 데이터 본딩 패드들 사이의 간격은 상호 동일한 것을 특징으로 하는 적층 반도체 패키지.The data bonding pads are formed in a square matrix shape when viewed in plan view, and the spacing between the data bonding pads is equal to each other. 제 8 항에 있어서,The method of claim 8, 상기 각 반도체 패키지들의 상기 각 반도체 칩들은 이웃한 칩 선택 패드 간에 상호 90°각도가 되도록 적층되는 것을 특징으로 하는 적층 반도체 패키지.Wherein each of the semiconductor chips of each of the semiconductor packages is stacked to have a 90 ° angle between adjacent chip select pads.
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Citations (2)

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US20040026768A1 (en) 2002-08-08 2004-02-12 Taar Reginald T. Semiconductor dice with edge cavities
US7214568B2 (en) 2004-02-06 2007-05-08 Agere Systems Inc. Semiconductor device configured for reducing post-fabrication damage

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040026768A1 (en) 2002-08-08 2004-02-12 Taar Reginald T. Semiconductor dice with edge cavities
US7214568B2 (en) 2004-02-06 2007-05-08 Agere Systems Inc. Semiconductor device configured for reducing post-fabrication damage

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