KR101074383B1 - Lipuid crystal display device and method for fabricating the same - Google Patents

Abstract

The present invention is to provide a liquid crystal display device and a method of manufacturing the liquid crystal display comprising a seal line mixed with conductive ball spacers in place of the conventional silver contact point in order to connect the common electrodes of the upper and lower substrates. The liquid crystal display device comprises: a liquid crystal panel comprising upper and lower substrates and a liquid crystal layer filled therebetween; A gate driver mounted on one side or both sides of the lower substrate; A data driver comprising a plurality of data drivers respectively connected to the source printed circuit board; A timing controller which outputs a control signal and image information to the gate driver and the data driver; Control signal lines arranged in one direction to input a control signal output from the timing controller to the gate driver; A transparent conductive film formed in one direction on the control signal line or the gate driver; An insulating film stacked on the transparent conductive film; And a seal line formed along an outer portion between the bonded upper and lower substrates and overlapping the control signal line or the gate driver, and including a conductive ball spacer. It is done.

Seal line, conductive ball spacer, insulating film

Description

Liquid crystal display and its manufacturing method {LIPUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

1 is a layout diagram of a liquid crystal display according to the related art.

2 is a layout diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a cross-sectional view of a circuit portion and a pixel region disposed in an edge region of a liquid crystal panel according to the present invention.

FIG. 4 is a cross-sectional view of a circuit portion and a pixel region disposed in an edge region of a liquid crystal panel which is a problem when an insulating film is not formed on a transparent conductive film in FIG.

5A through 5K are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

30: upper substrate 31: gate driver

32: data TCP 33: source printed circuit board

34: data driver 35: control signal line

40: liquid crystal panel 41: pixel portion

42: seal line 43: sealant

43a: conductive ball spacer 50: lower substrate

51a: drive wiring 51b: clock line

51c: gate electrode 51d: conductive pattern

52: gate insulating film 53: amorphous silicon layer

53a: active layer 54: n + amorphous silicon layer

54a: ohmic contact layer 55: first metal layer

55a: first metal pattern 55b: second metal pattern

55c: input signal line 55d: data line

55e: source electrode 55f: drain electrode

56: first photoresist pattern 57: protective film

58: second photoresist pattern

58a, 58b, 58c, 58d, 58e: 1st, 2nd, 3rd, 4th, 5th contact hole

59: transparent conductive film 59a, 59b: 1st, 2nd transparent conductive film

59c: pixel electrode 60: insulating film

61: third photoresist pattern 71: black matrix layer

72: color filter layer 73: common electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device. In particular, in a liquid crystal panel in which a gate driver is embedded in a lower substrate, when the common electrode of the upper and lower substrates is formed of a seal line in which conductive ball spacers are mixed, an electrical short circuit between the upper plate and the driving circuit is performed. It relates to a liquid crystal display device and a method of manufacturing the same that can prevent the.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, the LCD (Lipuid Crystal Display Device), PDP (Plasma Display Panel), ELD (Electro Luminescent Display), and VFD (Vacuum Fluorescent) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for mobile image display because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention, a variety of applications such as a television, a computer monitor, and the like for receiving and displaying broadcast signals have been developed.

Hereinafter, a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

1 is a layout diagram of a liquid crystal display according to the prior art.

As shown in FIG. 1, the liquid crystal display according to the related art includes an upper and lower substrates 10 and 11 and a liquid crystal panel 20 and a lower substrate 11 including liquid crystal layers (not shown) filled therebetween. A gate driver 12 composed of a plurality of gate drivers in the edge region of the N-axis), a data driver 15 composed of a plurality of drivers connected to the source printed circuit board 14 by the data TCP 13, It is composed of a seal line (16) formed at the edge between the upper and lower substrates (10, 11) to join the upper and lower substrates (10, 11).

The IC connecting the gate driver 12 and the data driver 15 uses a method such as an FPC or a COF. 1 illustrates an example of applying a gate COF.

A timing controller (not shown) for outputting control signals and image information to the gate driver 12 and the data driver 15 is further provided.

In the liquid crystal panel 20, a pixel portion 21 for displaying an image is defined, and the lower substrate 11 includes a plurality of gate lines and data lines that vertically intersect to define a pixel area in a matrix form. And a plurality of pixel electrodes formed in each pixel region defined by each of the gate lines and the data lines, and a plurality of TFTs applying the signal of the data line to each pixel electrode according to the signal of the gate line. The gate line and the data line intersect each other.

The thin film transistor includes a gate electrode protruding from one side of a gate line, a gate insulating film formed on the front surface including the gate electrode, an active layer overlapping an upper portion including the gate electrode, and a gate electrode overlapping at one side of the data line. And a source electrode overlapping each other, and a drain electrode spaced apart from the source electrode.

In addition, a passivation layer is formed on the drain electrode including the data line to have a first contact hole, and the drain electrode and the pixel electrode are contacted through the first contact hole.

Although not shown in the drawing, the upper substrate 10 includes a color filter layer coated separately by pixel region by a black matrix, and a common electrode serving as a counter electrode of the pixel electrode.

In the liquid crystal display having the above configuration, the liquid crystal is driven by applying a voltage to the common electrode and the pixel electrode formed between the upper and lower substrates 10 and 11. Therefore, in order to apply voltage to the common electrode and the pixel electrode of the upper and lower substrates 10 and 11, the common electrode must be connected to the pixel electrode. To this end, a silver contact point (Ag-Dot) 17 is generally provided between the upper and lower substrates 10 and 11. In FIG. 1, the silver contact point 17 is positioned at the corners of the top, bottom, left and right four parts.

However, the process of forming the silver contact 17 has a problem that the process is complicated and requires a lot of time.

The present invention has been made to solve the above problems, and in particular, in order to connect the common electrodes of the upper and lower substrates, a liquid crystal display device comprising a seal line in which conductive ball spacers are mixed instead of a conventional silver contact point and a manufacturing method thereof. The purpose is to provide.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal panel including upper and lower substrates and a liquid crystal layer filled therebetween; A gate driver mounted on one side or both sides of the lower substrate; A data driver comprising a plurality of data drivers respectively connected to the source printed circuit board; A timing controller which outputs a control signal and image information to the gate driver and the data driver; Control signal lines arranged in one direction to input a control signal output from the timing controller to the gate driver; A transparent conductive film formed in one direction on the control signal line or the gate driver; An insulating film stacked on the transparent conductive film; And a seal line formed along an outer portion between the bonded upper and lower substrates and overlapping the control signal line or the gate driver, and including a conductive ball spacer. It is done.

A pixel portion for displaying an image is defined in the liquid crystal panel to which the upper and lower substrates are bonded; a plurality of gate lines and data lines vertically intersecting to define pixel regions in the pixel portion of the lower substrate; A plurality of pixel electrodes formed in each pixel region defined by each gate line and data line, an insulating film stacked on the pixel electrode, a plurality of thin film transistors formed at an intersection portion of each gate line and data line, The pixel portion of the upper substrate is provided with a color filter layer separated and applied to each pixel region by a black matrix, and a common electrode serving as a counter electrode of the pixel electrode.

The manufacturing method of the liquid crystal display according to the present invention having the above configuration includes a gate driver mounted on one side or both sides of a lower substrate, and a control signal line for outputting a control signal to the gate driver. In the method of manufacturing a liquid crystal display device in which a driving circuit portion and a pixel portion are defined as first and second regions on a substrate, a gate driving wiring and a control signal line are formed in one direction in the first region by using a first mask, Forming a gate line and a gate electrode in the second region; An input signal line in the first region using a second mask, and a data line arranged vertically and horizontally with the gate line in the second region to define a pixel region, a second electrode forming a source electrode and a drain electrode; step; Forming a passivation layer on the entire surface of the substrate; A first contact hole is formed in the driving wiring of the first region by using a third mask, second and third contact holes are formed on both sides of the input signal line, and a fourth contact hole is formed in the control signal line; A fourth step of forming a fifth contact hole on the drain electrode of the second region; A first transparent conductive film and an insulating film are formed in the second contact hole in the first contact hole of the first region by using a fourth mask, and a second transparent hole is formed in the fourth contact hole in the third contact hole. A fifth step of stacking a conductive film and an insulating film, and stacking a pixel electrode and an insulating film on the pixel area of the second area so as to contact the fifth contact hole; And a sixth step of forming a seal material in which conductive ball spacers are mixed so as to surround an outer portion of the lower substrate.

In the sixth step, the seal member may be formed to overlap the control signal line or the gate driver outside the pixel unit.

The second step may include sequentially forming an amorphous silicon layer, an n + amorphous silicon layer, and a first metal layer on the lower substrate; It has a diffraction exposure portion in the channel portion of the thin film transistor on the first metal layer, and has a thin thickness only in the channel portion in the photolithography process using the second mask formed on the input signal line formation of the first region. Forming a photoresist pattern; Patterning the first metal layer by a wet etching process using the photoresist pattern to form a source / drain pattern including the data line, the source electrode, and a drain electrode integrated with the source electrode; Patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern to form an ohmic contact layer and an active layer in the first region and the second region; Ashing the photoresist pattern and then dry etching the mask with the mask to etch the source / drain pattern and the ohmic contact layer of the channel part to separate the source electrode and the drain electrode; And removing the photoresist pattern.

After forming the seal material, further comprising the step of bonding the upper substrate on the lower substrate and the upper surface opposite thereto.

Referring to the accompanying drawings, a liquid crystal display and a manufacturing method thereof according to an exemplary embodiment of the present invention will be described.

FIG. 2 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view of a circuit part and a pixel area disposed in an edge area of a liquid crystal panel according to the present invention.

FIG. 4 is a cross-sectional view of the circuit part and the pixel area disposed in the edge area of the liquid crystal panel, which is a problem when the insulating film is not formed on the first and second transparent conductive films in FIG. 3.

As shown in FIG. 3, the liquid crystal display according to the present invention includes a liquid crystal panel 40 including upper and lower substrates 30 and 50 and a liquid crystal layer (not shown) filled therebetween, and the lower substrate ( A gate driver 31 comprising a plurality of gate drivers mounted on one side or both upper portions of 50), and a plurality of data drivers connected to the source printed circuit board 33 by the data TCP 32, respectively. And a timing controller (not shown) for outputting control signals and image information to the data driver 34 and the gate driver 31 and the data driver 34.

The data driver 34 may be mounted on the lower substrate 50 like the gate driver 31 without being connected to the source printed circuit board 33 using the data TCP 32.

In addition, a plurality of control signal lines 35 for inputting a control signal output from the timing controller to each gate driver 31 are arranged in one direction. At this time, the timing controller supplies a predetermined clock signal, a gate start signal, and a timing signal as a control signal to control the driving timing of the gate driver 31 and the data driver 34.

A plurality of input signal lines (not shown) connected to the control signal lines 35 and inputting signals to the gate drivers of the gate driver 31 are arranged. Although not shown in the drawing, output signal lines are connected from the gate driver 31 to each gate pad portion of the pixel portion 41 in order to sequentially output the scanning signals to the gate pad portions of the lower substrate 50.

In the liquid crystal panel 40, a pixel portion 41 in which an image is displayed is defined, and a plurality of gate lines and data lines vertically intersecting in the lower substrate 50 to define a pixel area, and the angles A plurality of pixel electrodes formed in each pixel region defined by a gate line and a data line, and a plurality of thin film transistors for applying a signal of the data line to each pixel electrode in accordance with a signal of the gate line, respectively The line is formed at the intersection. In addition, the upper substrate 30 includes a color filter layer coated and separated by pixel regions by a black matrix, and a common electrode serving as a counter electrode of the pixel electrode.

When a turn on signal is sequentially applied to the gate line, an image is displayed because a data signal is applied to the pixel electrode of the corresponding line.

A seal line 42 is formed along the outer portion where the upper and lower substrates 30 and 50 are bonded to each other, and the seal line 42 is the control signal line 35 or / and the gate driver. It overlaps on the upper part of 31.

The seal line 42 is formed by mixing a conductive ball spacer 43a with a sealant 43 to electrically connect the common electrodes (transparent conductive layers) of the upper and lower substrates 30 and 60. 2 and 3, the common line of the upper and lower substrates 30 is connected to the seal line 42 in the upper portion of the pixel portion 41. For example, in the 'B' area it is connected like this.

As a result, the seal line 42 is replaced by the conventional silver contact point Ag-Dot.

In this case, it is important to consider that since the seal line 42 formed by mixing the conductive ball spacers is conductive, the control line 35 or the gate driver 31 overlaps with the control signal line 35 or / and the gate driver 31. 31 is electrically connected to the upper substrate 30 so that circuit driving is impossible.

In order to form the seal line 42 by mixing the conductive ball spacers in the sealant without the above problems, the entire driving circuit, that is, the gate driver 31 and the control signal line 35 are disposed inside the seal line 42. It is also conceivable, but this configuration causes a problem that the size of the entire liquid crystal panel increases. The size of the liquid crystal panel is defined in international standards, and arbitrary changes are not possible. Therefore, in the case of a liquid crystal panel with a driving circuit, an area for embedding a circuit will be limited. For example, in the case of a liquid crystal panel for a 14-17 "XGA class notebook computer, it is impossible to implement the entire driving circuit inside the seal line 42, and the seal line 42 is positioned so as to overlap the control signal line or the gate driver. Done.

In order to form the seal line 42 by mixing the conductive ball spacers in the sealant as described above, the control signal is controlled by the conductive ball spacers in the seal line 42 located above the control signal line 35 or / and the gate driver 31. The line 35 and the gate driver 31 are not connected to the common electrode of the upper substrate 30 and must be insulated from each other.

However, as shown in FIG. 4, since the transparent conductive film ITO is used to connect the signal lines, the transparent conductive film ITO is exposed at the top of the signal line, so that the common electrode of the upper substrate 30 is exposed by the conductive ball spacer. It is electrically connected to this control signal line.

The present invention is to solve the problem that the upper substrate 30 and the control signal line 35 is electrically connected when the conductive ball spacer is mixed with the sealant to form the seal line 42, as shown in FIG. 3. As shown in FIG. 6, an insulating film is formed on the transparent conductive film ITO overlapped with the control signal line 35 to insulate the control signal line 35 and the transparent conductive film from the upper substrate 30. The common electrode 73 of the 30 and the pixel electrode of the lower substrate 50 may be connected to each other.

Hereinafter, a cross-sectional structure of the driving circuit unit and the pixel unit of the liquid crystal panel edge, that is, the region 'A' of FIG. 2 will be described in detail with reference to the drawings.

In the above description, the driving circuit unit cuts portions of the control signal line (hereinafter, exemplarily described as a clock line) and the gate driver.

For convenience of description, the driving circuit unit is defined as a first region and the pixel unit is defined as a second region.

As shown in FIG. 3, the gate driving wiring 51a arranged in one direction and the clock line 51b constituting the control signal line are formed in the first region of the lower substrate 50. In the second region, gate lines are arranged in one direction, and the gate electrode 51c protruding from one side thereof is provided.

The gate insulating layer 52 is formed on the lower substrate 50 including the driving wiring 51a, the clock line 51b, and the gate electrode 51c.

The gate insulating layer 52 may be formed of a silicon nitride layer (SiNx) or a silicon oxide layer (SiO ₂ ).

A conductive pattern 51d on the lower substrate 50 between the driving wiring 51a and the clock line 51b of the first region, a gate insulating film 52 on the entire upper surface of the conductive pattern 51d, and the conductive pattern An input signal line 55c in which an amorphous silicon layer 53, an n + amorphous silicon layer 54, and a first metal pattern 55a are stacked is formed on the gate insulating film 52 including 51d.

An active layer 53a formed of an amorphous silicon layer is formed on one region of the gate insulating layer 52 including the gate electrode 51c of the second region.

In addition, a data line 55d is formed to vertically cross the gate line (not shown) to define a pixel area, protrude from one side of the data line 55d, and overlap a source on one side of the gate electrode 51c. The electrode 55e is formed, and the drain electrode 55f is formed so as to be spaced apart from the source electrode 55e and overlap the upper portion of the gate electrode 51c. An ohmic contact layer 54a made of an n + amorphous silicon layer is formed between the active layer 53a, the source electrode 55e, and the drain electrode 55f.

The input signal line 55c of the first region is formed on the same layer as the data line.

The passivation layer 57 is formed on the entire surface of the lower substrate 50 including the data line 55d and the input signal line 55c. The first contact hole 58a is formed in the driving wiring 51a of the first region. The second and third contact holes 58b and 58c are formed at both sides of the input signal line 55c, and the fourth contact hole 58d is formed in the clock line 51b. The fifth contact hole 58e is formed on the drain electrode 55f in the two regions.

A first transparent conductive film 59a is formed in the second contact hole 58b in the first contact hole 58a of the first region, and the fourth contact hole in the third contact hole 58c of the first region. A second transparent conductive film 59b is formed at 58d. The pixel electrode 59c is formed in the fifth contact hole 58e of the second region.

The input signal line 55c connects the first transparent conductive film 59a and the second transparent conductive film 59b to connect the driving wiring 51a and the clock line 51b to each other.

In the above, an insulating film 60 is laminated on the first and second transparent conductive films 59a and 59b and the pixel electrode 59c, respectively.

In addition, a black matrix layer 71 is formed on an area of the upper substrate 30 except for the pixel region, and a common electrode 73 is formed on an entire surface of the upper substrate 30 including the black matrix layer 71. .

A seal line 42 is formed along the outer portion of the liquid crystal panel 40 (see FIG. 2) on the passivation layer 57 and the insulating layer 60 of the lower substrate 50.

In this case, the seal line 42 overlaps the clock line 51b and the driving wiring 51a.

The seal line 42 includes a conductive ball spacer 43a in the sealant 43. At this time, since the insulating film 60 is further provided on the first and second transparent conductive films 59a and 59b and the pixel electrode 59c, the seal line 42 is connected to the driving wiring 51a and the clock in the first region. Even if the upper portion of the line 51b overlaps, the problem that the lower substrate 50 and the upper substrate 30 are connected does not occur, so the embedded circuit operates normally.

In addition, since the common lines of the upper and lower substrates 30 and 50 may be connected to the seal line 42 except for the portions of the first and second transparent conductive layers 59a and 59b for driving the internal circuits, the conventional silver contacts Can be configured by removing

FIG. 4 is a diagram illustrating a problem when no insulating film is provided on the first and second transparent conductive films 59a and 59b and the pixel electrode 59c, except for the absence of the insulating film. Are all the same, and are denoted by the same reference numerals. When the seal line 42 is configured to overlap the control signal line or / and the gate driver, the control line is controlled by the conductive ball spacer of the seal line in this part. The signal line or / and gate driver may be shorted with the common electrode of the upper substrate.

Since other parts are the same, the description thereof will be omitted.

Next, a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention will be described.

5A through 5K are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention.

First, in the method of manufacturing the liquid crystal display of the present invention, as shown in FIG. 5A, the conductive metal is deposited on the lower substrate 50, and the conductive metal is patterned by using a photo and etching process using a first mask. In the first region of the lower substrate 50, the gate driving wiring 51a arranged in one direction, the clock line 51b constituting the control signal line are formed, and the gate region arranged in one direction in the second region, A gate electrode 51c protruding from one side thereof is formed. The conductive pattern 51d is formed on the lower substrate 50 between the drive wiring 51a and the clock line 51b.

Next, as shown in FIG. 5B, a gate insulating film 52, an amorphous silicon layer 53, and an upper portion of the lower substrate 50 including the driving wiring 51a, the clock line 51b, and the gate electrode 51c are formed. The n + amorphous silicon layer 54 and the first metal layer 55 for source / drain formation are sequentially formed.

The gate insulating layer 52 may be formed of a silicon nitride layer (SiNx) or a silicon oxide layer (SiO ₂ ).

Subsequently, as illustrated in FIG. 5C, the first photoresist pattern 56 is formed by a photolithography process using a second mask. In this case, the second mask is formed on the input signal line in the first region and on the thin film transistor in the first region, and the first photoresist pattern of the channel portion is formed by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor. 56) has a lower height than other source / drain pattern portions.

Subsequently, as illustrated in FIG. 5D, the first metal layer 55 is patterned by a wet etching process using the first photoresist pattern 56, and the first metal pattern 55a for input signal line formation is formed in the first region. The second metal pattern 55b for forming the data line, the source electrode, and the drain electrode is formed in the second region.

Next, the n + amorphous silicon layer 54 and the amorphous silicon layer 53 are simultaneously patterned by a dry etching process using the same first photoresist pattern 56.

As a result, an input signal line 55c in which the amorphous silicon layer 53, the n + amorphous silicon layer 54, and the first metal pattern 55a are stacked is formed in the first region.

As shown in FIG. 5E, the ashing process is performed such that the first photoresist pattern 56 is removed from the channel portion so that the first photoresist pattern 56 having a relatively low height is removed. In the etching process, the second metal pattern 55b and the n + amorphous silicon layer 54 are etched. As a result, the active layer 53a, the source electrode 55e, and the drain electrode 55f are electrically separated. The data line 55d is formed to intersect with the gate line to define the pixel area. An ohmic contact layer 54a is formed between the source electrode 55e and the active layer 53a and between the drain electrode 55d and the active layer 53a.

Subsequently, the first photoresist pattern 56 remaining on the second metal pattern 55b is removed by a stripping process.

Through this process, a thin film transistor (TFT) including a gate electrode 51a, an active layer 53a, a source electrode 55e, and a drain electrode 55f is formed.

Subsequently, as shown in FIG. 5F, the passivation layer 57 is formed on the entire surface of the lower substrate 50 including the TFT by a deposition method such as PECVD.

Thereafter, after the photoresist is applied on the passivation layer 57, the second photoresist pattern 58 is formed by a photo-etching process using a third mask.

The protective layer 57 is etched using the second photoresist pattern 58 as a mask, so that the first contact hole 58a is formed in the driving wiring 51a of the first region, and the second and second portions are formed at both sides of the input signal line 55c. A fourth contact hole 58d is formed in the third contact holes 58b and 58c and the clock line 51b, and a fifth contact hole 58e is formed on the drain electrode 55f of the second region.

Thereafter, the second photoresist pattern 58 is removed.

Next, as shown in FIG. 5G, after the transparent conductive film 59 and the insulating film 60 are sequentially deposited on the entire surface, a photoresist is applied on the insulating film 60, and then a photo and etching process is performed using a fourth mask. The third photoresist pattern 61 is formed by the process.

As shown in FIG. 5H, the insulating film 60 and the transparent conductive film 59 are sequentially etched using the third photoresist pattern 61 as a mask, and the second contact hole 58a in the first region is second-etched. A first transparent conductive film 59a is formed in the contact hole 58b, and a second transparent conductive film 59b is formed in the fourth contact hole 58d in the third contact hole 58c of the first region. The pixel electrode 59c is formed in the fifth contact hole 58e of the second region.

The driving wiring 51a and the clock line 51b are connected to each other through the input signal line 55c, the first transparent conductive film 59a, and the second transparent conductive film 59c.

As described above, the insulating film 60 is further provided on the first and second transparent conductive films 59a and 59b and the pixel electrode 59c, respectively.

Although not shown in the figure, a first alignment layer is formed on the protective layer of the lower substrate 50.

As shown in FIG. 5I, the components are formed on the lower substrate 50 and the upper substrate 30 facing the lower substrate 50 is common to the black matrix 71 and the color filter layer 72. The electrode 73 and the second alignment layer (not shown) are sequentially formed in the process order.

Subsequently, as shown in FIG. 5J, in order to prevent the liquid crystal between the upper and lower substrates 30 and 50 from leaking out, and to assist the adhesion of the upper and lower substrates 30 and 50 during the bonding process, The seal line 42 is formed to surround the outer portion of the substrate 50. The seal line 42 is formed by mixing the conductive ball spacers 43a in the sealant 43.

At this time, the seal line 42 overlaps the control signal line () or the gate driver () outside the pixel portion (see FIG. 2).

Next, as shown in FIG. 5K, the upper and lower substrates 30 and 50 are bonded together and heated to cure the seal member to bond the upper and lower substrates 30 and 50 together.

When the conductive ball spacers 43a are mixed and formed on the seal line 42 as described above, the first and second transparent conductive films 59a and 59b for connecting the driving wiring 51a and the clock line 51b and By forming an insulating film 60 on the pixel electrode 59c, the control signal line 35 and the gate driver 31 are shorted to the common electrode of the upper substrate 30 by the seal line 42. To prevent it.

That is, when the gate driver is embedded in the liquid crystal panel, even though the seal line is formed to overlap the gate driver or the control signal line for applying the signal, the gate driver is not electrically connected and the embedded gate driver operates normally.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention.

Accordingly, the technical scope of the present invention should not be limited to the contents described in the above embodiments, but should be determined by the claims.

The liquid crystal display according to the present invention as described above and a manufacturing method thereof have the following effects.

First, since the common electrode of the upper and lower substrates may be connected by a seal line formed by mixing the conductive ball spacers, the process may be simplified since the conventional silver contact process may not be performed.

Second, even if the seal gate including the conductive ball spacer is mixed on the embedded gate driver or / and the control signal line, the insulating film is stacked on the control signal line and the pixel electrode. By forming, the gate driver and the control signal line embedded by the conductive ball spacer can be prevented from being electrically connected to the common electrode of the upper substrate.

Claims (6)

A liquid crystal panel comprising upper and lower substrates and a liquid crystal layer filled therebetween; A gate driver mounted on one side or both sides of the lower substrate; A data driver comprising a plurality of data drivers respectively connected to the source printed circuit board; A timing controller which outputs a control signal and image information to the gate driver and the data driver; Control signal lines arranged in one direction to input a control signal output from the timing controller to the gate driver; A transparent conductive film formed in one direction on the control signal line or the gate driver; An insulating film stacked on the transparent conductive film; And a seal line formed along an outer portion between the bonded upper and lower substrates and overlapping the control signal line or the gate driver, and including a conductive ball spacer. A liquid crystal display device. The method of claim 1, In the liquid crystal panel to which the upper and lower substrates are bonded, a pixel portion for displaying an image is defined. A plurality of gate lines and data lines vertically intersecting at the pixel portion of the lower substrate to define a pixel area; A plurality of pixel electrodes formed in each pixel region defined by each of the gate lines and the data lines; An insulating film stacked on the pixel electrode; A plurality of thin film transistors formed at portions where the gate lines and the data lines cross each other; A color filter layer coated and separated for each pixel region by a black matrix on the pixel portion of the upper substrate; And a common electrode serving as a counter electrode of the pixel electrode. A liquid crystal device including a gate driver mounted on one side or both sides of a lower substrate, and a control signal line for outputting a control signal to the gate driver, wherein the driving circuit part and the pixel part are defined as first and second regions on the lower substrate; In the manufacturing method of the display device, Forming a gate driving wiring and a control signal line in one direction in the first region by using a first mask, and forming a gate line and a gate electrode in the second region; An input signal line in the first region using a second mask, and a data line arranged vertically and horizontally with the gate line in the second region to define a pixel region, a second electrode forming a source electrode and a drain electrode; step; Forming a passivation layer on the entire surface of the substrate; A first contact hole is formed in the driving wiring of the first region by using a third mask, second and third contact holes are formed on both sides of the input signal line, and a fourth contact hole is formed in the control signal line; A fourth step of forming a fifth contact hole on the drain electrode of the second region; A first transparent conductive film and an insulating film are formed in the second contact hole in the first contact hole of the first region by using a fourth mask, and a second transparent hole is formed in the fourth contact hole in the third contact hole. A fifth step of stacking a conductive film and an insulating film, and stacking a pixel electrode and an insulating film on the pixel area of the second area so as to contact the fifth contact hole; And a sixth step of forming a sealing material in which conductive ball spacers are mixed so as to surround an outer portion of the lower substrate. The method of claim 3, wherein In the sixth step, the seal member is formed so as to overlap the upper portion of the control signal line or the gate driver outside the pixel portion. The method of claim 3, wherein The second step, Sequentially forming an amorphous silicon layer, an n + amorphous silicon layer, and a first metal layer on the lower substrate; A photolithography process having a diffraction exposure portion in the channel portion of the thin film transistor on the first metal layer, and having a thin thickness only in the channel portion in a photolithography process using the second mask formed on the input signal line formation in the first region. Forming a resist pattern; Patterning the first metal layer by a wet etching process using the photoresist pattern to form a source / drain pattern including the data line, the source electrode, and a drain electrode integrated with the source electrode; Patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern to form an ohmic contact layer and an active layer in the first region and the second region; Ashing the photoresist pattern and then dry etching the mask with the mask to etch the source / drain pattern and the ohmic contact layer of the channel part to separate the source electrode and the drain electrode; And removing the photoresist pattern. The method of claim 3, wherein And forming an upper substrate on the lower substrate and an upper surface opposite to the lower substrate after forming the seal material.

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