KR101009680B1 - Lipuid crystal display device and method for fabricating the same - Google Patents

Lipuid crystal display device and method for fabricating the same Download PDF

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KR101009680B1
KR101009680B1 KR1020040030625A KR20040030625A KR101009680B1 KR 101009680 B1 KR101009680 B1 KR 101009680B1 KR 1020040030625 A KR1020040030625 A KR 1020040030625A KR 20040030625 A KR20040030625 A KR 20040030625A KR 101009680 B1 KR101009680 B1 KR 101009680B1
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pixel
gate
line
layer
signal line
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KR1020040030625A
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Korean (ko)
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KR20050105596A (en
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김빈
윤수영
전민두
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엘지디스플레이 주식회사
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Abstract

The present invention is to provide a liquid crystal display device and a method of manufacturing the same that can maximize the effective area of the driving circuit portion outside the pixel portion, and improve the productivity by reducing the number of masks, the present invention for achieving the above object The liquid crystal display according to claim 1 includes a gate line having a sandwich structure of first, second and third conductive layers, wherein the second conductive layer protrudes from the first and third conductive layers, and the gate line. A data line defining a pixel area perpendicular to the data line and a first substrate on which the pixel part is defined; A second substrate opposed to the first substrate; A gate driver mounted on the first substrate outside the pixel unit; A data driver formed outside or inside a first substrate to apply a signal to the data line; A timing controller which outputs an image signal to the data driver and outputs a control signal to the gate driver through a control signal line having a sandwich structure in which first, second and third conductive layers are stacked; And a seal line formed between the first and second substrates and overlapping the control signal line outside the pixel portion or overlapping the control signal line and the gate driver.
Figure R1020040030625
Seal Line, Gate Drive, Sandwich

Description

Liquid crystal display and its manufacturing method {LIPUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

1 is a layout diagram of a liquid crystal display according to the related art.

2A and 2B are enlarged views of portions 'A' and 'B' of FIG. 1.

3 is a cross-sectional view taken along line II ′ and II-II ′ of FIGS. 2A and 2B.

4A is a cross-sectional view illustrating a structure in which a seal material overlaps an upper portion of a control signal line and an input signal line outside the pixel unit in FIG.

4B and 4C are photographs showing the problem according to FIG. 4A

5 is a layout diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

6A and 6B are enlarged views of portions 'C' and 'D' of FIG. 5.

7 is a cross-sectional view of a structure of a liquid crystal display according to a first exemplary embodiment of the present invention, taken along lines III-III 'and IV-IV' of FIGS. 6A and 6B.

8A to 8F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention.

9 is a cross-sectional view of a structure of a liquid crystal display according to a second exemplary embodiment of the present invention, taken along lines III-III 'and IV-IV' of FIGS. 6A and 6B.

10A through 10F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a second embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

50: upper substrate 51: lower substrate

52: gate driver 53: data TCP

54: source printed circuit board 55: data driver

56: timing control unit 57, 95, 115: seal line

58 pixel unit 60 liquid crystal panel

80, 100: lower substrate 81, 101: first transparent metal layer

82, 102: gate metal layer 83, 103: second transparent metal layer

84, 104: First photosensitive film 85, 105: First mask

86, 106: gate line 86a, 106a: gate electrode

86b and 106b: control signal lines 87 and 107: gate insulating film

88, 108 amorphous silicon layer 88a, 108a active layer

89, 109: n + amorphous silicon layer 89a, 109a: ohmic contact layer

90, 110: Second photosensitive film 91a, 111a: First contact hole

91b, 111b: second contact holes 92, 112: pixel electrodes

93, 113: data lines 93a, 113a: source electrode

93b and 113b drain electrodes 93c and 113c input signal lines

94, 114: protective film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a manufacturing method thereof configured to maximize the effective area when a gate driver is mounted on a lower substrate.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, the LCD (Lipuid Crystal Display Device), PDP (Plasma Display Panel), ELD (Electro Luminescent Display), and VFD (Vacuum Fluorescent) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for mobile image display because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention, a variety of applications such as a television, a computer monitor, and the like for receiving and displaying broadcast signals have been developed.

Hereinafter, a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

FIG. 1 is a layout view of a liquid crystal display according to the related art, and FIGS. 2A and 2B are enlarged views of portions 'A' and 'B' of FIG. 1, and FIG. 3 is I-I of FIGS. 2A and 2B. It is a structural cross section which cut the 'and II-II' line.                         

4A is a cross-sectional view illustrating a structure in which a seal material overlaps an upper portion of a control signal line and an input signal line outside the pixel unit in FIG. 3, and FIGS. 4B and 4C are photographs illustrating a problem according to FIG. 4A.

As shown in FIG. 1, the LCD according to the related art includes a liquid crystal panel 20 including upper and lower substrates 10 and 11 and a liquid crystal layer (not shown) filled therebetween, and the lower substrate ( 11 and a plurality of drivers connected to the source printed circuit board 14 by the data TCP 13 and the gate driver 12 composed of a plurality of gate drivers 12_1 to 12_n mounted on one side of the upper part 11. And a timing controller 16 for outputting control signals and image information to the gate driver 12 and the data driver 15.

A plurality of control signal lines CS1, CS2, CS3, CS4, and CS5 for inputting the control signal output from the timing controller 16 to each gate driver IC 12 are arranged. At this time, the timing controller 16 controls the driving timing of the gate driver 12 and the data driver 15 by supplying a predetermined clock signal, a gate start signal, and a timing signal as control signals.

A plurality of input signal lines IN1, IN2, IN3, IN4, and IN5 connected to the control signal lines and inputting signals to the gate drivers 12_1 to 12_n of the gate driver 12 are arranged. . Although not shown in the drawing, scan signals are sequentially output to the gate pad portions of the lower substrate 11 through the output signal lines of the gate driver 52. In the above description, the control signal lines and the input signal lines are arbitrarily given by five.

A seal line 7 is formed at the outer side between the upper and lower substrates 10 and 11, and the seal line 7 does not overlap the gate driver, the control signal line, and the input signal line. So that it is formed on the outside. At this time, the upper and lower substrates 10 and 11 are formed in the same size as shown in FIG.

In the liquid crystal panel 20, as illustrated in FIGS. 1, 2B, and 3, the pixel portion 8 displaying an image is defined, and the lower substrates 11 and 30 are vertically intersected. A plurality of gate lines 31 and data lines 34 defining a pixel area in a matrix form, and a plurality of pixel electrodes formed in each pixel area defined by the gate lines 31 and data lines 34 ( 37a and a plurality of thin film transistors TFT for applying the signal of the data line 34 to each pixel electrode 37a according to the signal of the gate line 31. 34 is formed at the intersection.

The thin film transistor overlaps the gate electrode 31a protruding from one side of the gate line 31, the gate insulating layer 32 formed on the entire surface including the gate electrode 31a, and the upper portion including the gate electrode 31a. An active layer 33a, a source electrode 34a overlapping at one side of the data line 34 and overlapping at one side of the gate electrode 31a, and a drain electrode 34b spaced apart from the source electrode 34a. It consists of. Reference numeral 33b denotes an ohmic contact layer.

In addition, a passivation layer 35 is formed on the drain electrode 34b including the data line 34 to have the first contact hole 36a, and the drain electrode 34b is formed through the first contact hole 36a. The pixel electrode 37a is in contact.

Although not shown in the drawing, the upper substrate 10 includes a color filter layer coated separately by pixel region by a black matrix, and a common electrode serving as a counter electrode of the pixel electrode 37a.

When a turn on signal is sequentially applied to the gate line, an image is displayed because a data signal is applied to the pixel electrode of the corresponding line.

1, 2A and 3, the control signal line 31b (CS1, CS2, CS3, CS4, CS5) is disposed on the same layer as the gate electrode 31a on one side of the pixel portion of the lower substrate. Are formed in one direction, the gate insulating film 32 is formed on the upper portion including the control signal line 31b, and the input signal line 34c is formed so as to overlap on one region of the control signal line 31b. . In this case, the control signal line 31b is formed on the same layer as the source electrode 34a and the drain electrode 34b.

Second and third contact holes 36b and 36c are formed in the control signal line 31b and the input signal lines 34c (IN1, IN2, IN3, IN4, and IN5). The signal connection part 37b formed of a transparent metal layer is formed to connect the control signal line 31b and the input signal line 34c through the contact holes 36b and 36c.

Although not shown in the figure, the gate driver 12 and the data driver 15 are composed of a plurality of buffer TFTs.                         

When mounting the driving circuit (gate driver) on the lower substrates 11 and 30 as in the above-described structure, the area of the driving circuit becomes an important problem, in particular, the driving circuit using a-Si: H TFTs. In the case of configuring the buffer TFT, the size of the buffer TFT of the driving circuit becomes very large due to the low mobility of a-Si: H. According to the design, the buffer TFT has a channel width of several thousand [mu] m or more, and accordingly, the area of the gate driver is large. However, due to the design of the product, the gate driver must be implemented in a finite area.

For example, in the case of 2.2 "QVGA, since the pixel portion 8 to the scribe line of the lower substrate 11 is 2.2 mm, when the gate driver is implemented on the lower substrate 11, the area occupied by the circuit must be reduced to 2.2 mm or less. do.

On the other hand, since the seal line 7 is formed outside the pixel portion in the cell process for bonding the upper and lower substrates, the effective area for mounting the gate driver 12 varies depending on the position of the seal line 7. Therefore, the position of the seal line 7 is an important factor in product development.

That is, in the conventional liquid crystal display having the above configuration, as shown in FIGS. 1, 2A, and 3, the seal line 7 is formed outside the gate driver 12, the control signal line, and the input signal line. Therefore, there is a problem that the effective area that can be used as the gate driver 12 is reduced.

In order to solve the above problem, as shown in FIG. 4A, a structure in which the seal line 38 overlaps the signal connection part 37b connecting the control signal line 31b and the input signal line 34c may be applied. In this case, as shown in FIGS. 4B and 4C, the signal connection part 37b formed of the transparent metal layer may be damaged by the glass fiber constituting the seal line, and thus disconnected to the control signal line. Problems may arise.

When such a problem occurs, a fatal problem may occur in signal transmission for driving the liquid crystal panel.

The present invention has been made to solve the above problems, and in particular, it is possible to maximize the effective area of the driving circuit portion outside the pixel portion, and to provide a liquid crystal display device and a method of manufacturing the same, which can improve productivity by reducing the number of masks. Its purpose is to.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a gate line having a sandwich structure of first, second, and third conductive layers; a data line defining a pixel region perpendicular to the gate line; A first substrate on which a pixel portion is defined; A second substrate opposed to the first substrate; A gate driver mounted on the first substrate outside the pixel unit; A data driver formed outside or inside a first substrate to apply a signal to the data line; A timing controller which outputs an image signal to the data driver and outputs a control signal to the gate driver through a control signal line having a sandwich structure in which first, second and third conductive layers are stacked; And a seal line formed between the first and second substrates and formed along a circumference of the pixel portion to overlap the control signal line outside the pixel portion and / or the eastern part of the gate hole.

A gate line of a sandwich structure in which first, second and third conductive layers are stacked, a gate electrode protruding from one side of the gate line, a pixel electrode formed in the pixel region, and a pixel portion of the first substrate; A gate insulating film formed on the entire surface of the first substrate to have a first contact hole in the pixel electrode, an active layer including an amorphous silicon layer on one region including the gate electrode, and protruding from one side of the data line; A source electrode overlapping one side of the source electrode, a drain electrode spaced apart from the source electrode and overlapping the other side of the gate electrode and contacting the pixel electrode through the first contact hole, the active layer, the source electrode, and the The first substrate including the data line and an ohmic contact layer including an n + amorphous silicon layer between the drain electrodes It is characterized by consisting of a protective film formed on the front.

The first and third conductive layers are composed of a transparent metal layer such as ITO, IZO, ITZO, and the second conductive layer is composed of a metal layer of Mo / AlNd or Mo.

The second conductive layer is characterized in that it further comprises protruding than the first, third conductive layer.

In the manufacturing method of the liquid crystal display device according to the embodiment of the present invention having the configuration as described above in the manufacturing method of the liquid crystal display device having a first substrate having a pixel portion is defined, the gate driver is mounted on the outside of the pixel portion, A control signal line outside the pixel portion of the first substrate is formed to have a sandwich structure in which the first, second and third conductive layers are stacked using the first mask, and a gate line and a gate electrode are formed in the pixel portion. Forming a pixel pattern layer in the pixel region; Etching the third conductive layer to expose one region of the second conductive layer of the pixel pattern layer; Forming a gate insulating film over the first substrate; A fourth step of forming a semiconductor pattern over the gate electrode by using a second mask; A fifth step of forming first and second contact holes in the second conductive layer and the control signal line of the pixel pattern layer using a third mask; A sixth step of forming a pixel electrode in the pixel region by removing the second conductive layer of the pixel pattern layer; A data line vertically intersecting with the gate line to define the pixel region using a fourth mask, a source electrode protruding from one side of the data line, and a spaced apart from the source electrode, and the pixel electrode and the first contact hole Forming a drain electrode contacted through the second electrode and forming an input signal line contacting the control signal line through the second contact hole; An eighth step of depositing a protective film on the entire surface of the first substrate; And a ninth step of forming a seal line along the periphery of the pixel portion so as to overlap the control signal line, the input signal line, and / or the gate driver.

The first and second steps may include sequentially depositing first, second and third conductive layers on the entire surface of the first substrate, applying a first photoresist layer on the third conductive layer, and forming the pixel region. Patterning the first photoresist layer using the first mask having a region corresponding to an upper portion of the one region using half-tones, and the control signal line and the gate having a sandwich structure using the patterned first photoresist layer as a mask Forming a line, a gate electrode, and a pixel pattern layer, ashing the first photoresist layer to expose a portion of the third conductive layer of the pixel region portion, and below the exposed third conductive layer And etching the third conductive layer to expose the second conductive layer, and removing the first photosensitive film.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device having a first substrate including a pixel portion and a gate driver mounted outside the pixel portion. And a control signal line outside the pixel portion, a gate line and a gate portion outside the pixel portion to have a sandwich structure in which the second conductive layer among the first, second, and third conductive layers is protrudingly stacked using a first mask. Forming a pixel pattern layer on the electrode and the pixel region; Forming a gate insulating film on the entire surface of the first substrate; A third step of forming a semiconductor pattern on the top including the gate electrode using a second mask; A fourth step of forming first and second contact holes to expose the second conductive layer of the pixel pattern layer and the third conductive layer of the control signal line by using a third mask; A fifth step of forming a pixel electrode in the pixel region by removing the second conductive layer of the pixel pattern layer; A data line vertically intersecting with the gate line to define the pixel region using a fourth mask, a source electrode protruding from one side of the data line, and a spaced apart from the source electrode, and the pixel electrode and the first contact hole Forming a drain electrode contacted through the second electrode and forming an input signal line contacted with the control signal line through the second contact hole; Depositing a passivation layer on the entire surface of the first substrate; And an eighth step of forming a seal line along the periphery of the pixel portion so as to overlap the control signal line, the input signal line, and / or the gate driver.

The first step may include depositing first, second, and third conductive layers on the entire surface of the first substrate, applying a first photosensitive film on the third conductive layer, and using the first mask. Patterning the first photoresist layer, sequentially etching the third, second and first conductive layers using the patterned first photoresist layer as a mask, and excessively etching the first and third conductive layers to form the second conductive layer. And forming the control signal line, the gate line, the gate electrode, and the pixel pattern layer such that the edge portion of the layer has a protruding sandwich structure, and removing the first photoresist layer.

The first and third conductive layers are formed of a transparent metal layer such as ITO, IZO, or ITZO, and the second conductive layer is formed of a metal layer of Mo / AlNd or Mo.

The second conductive layer of the pixel pattern layer may be removed using an etchant of H 3 PO 4 + HNO 3 + CH 3 COOH.

Hereinafter, a liquid crystal display and a method of manufacturing the same according to the present invention will be described with reference to the accompanying drawings.

5 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 6A and 6B are enlarged views of portions 'C' and 'D' of FIG. 5.

As shown in FIG. 5, the liquid crystal display according to the present invention includes a liquid crystal panel 60 including upper and lower substrates 50 and 51 and a liquid crystal layer (not shown) filled therebetween, and the lower substrate. A plurality of data connected to the source printed circuit board 54 by the gate driver 52 made up of a plurality of gate drivers 52_1 to 52_n mounted on one side of the 51 and the data TCP 53, respectively. And a timing controller 56 for outputting control signals and image information to the gate driver 52 and the data driver 55.

The data driver 55 may be mounted on the lower substrate 51 like the gate driver 52 without being connected to the source printed circuit board 54 by using the data TCP 53.

In addition, a plurality of control signal lines CS1, CS2, CS3, CS4, and CS5 for inputting a control signal output from the timing controller 56 to each gate driver 52 are arranged in one direction. At this time, the timing controller 56 controls the driving timing of the gate driver 52 and the data driver 55 by supplying a predetermined clock signal, a gate start signal, and a timing signal as control signals.

A plurality of input signal lines IN1, IN2, IN3, IN4, and IN5 connected to the control signal lines and inputting signals to the gate drivers 52_1 to 52_n of the gate driver 52 are arranged. Although not shown in the drawing, output signal lines are connected from the gate driver 52 to each gate pad portion of the pixel portion in order to sequentially output the scanning signals to the gate pad portions of the lower substrate 51.

In the above description, the control signal lines and the input signal lines are arbitrarily inputted by five.

A seal line 57 is formed outside the pixel portion between the upper and lower substrates 50 and 51, and the seal line 57 overlaps the control signal line or the input signal line. have. In this case, the upper and lower substrates 50 and 51 show examples of the same size.

In the liquid crystal panel 60, a pixel portion 58 for displaying an image is defined, and the lower substrate 51 includes a plurality of gate lines and data lines vertically intersecting to define a pixel region. A plurality of pixel electrodes formed in each pixel region defined by a gate line and a data line, and a plurality of thin film transistors for applying a signal of the data line to each pixel electrode in accordance with a signal of the gate line, respectively The line is formed at the intersection. In addition, the upper substrate 50 is provided with a color filter layer separated and coated for each pixel region by a black matrix, and a common electrode serving as a counter electrode of the pixel electrode.

When a turn on signal is sequentially applied to the gate line, an image is displayed because a data signal is applied to the pixel electrode of the corresponding line.

Although not shown in the drawing, the gate driver 52 and the data driver 55 are composed of a plurality of buffer TFTs.

As described above, when mounting the driving circuit (gate driver) on the lower substrate 51, the area of the driving circuit is an important problem. In particular, when the buffer TFT of the driving circuit is configured by using a-Si: H TFT, the size of the buffer TFT of the driving circuit becomes very large due to the low mobility of a-Si: H. It has no choice but to have a channel width of several thousand μm or more. Therefore, the area of the gate driver is inevitably large, but it must be implemented in a finite area due to the design characteristics of the product.

For example, in the case of 2.2 "QVGA, since the pixel portion 58 to the scribe line of the lower substrate is 2.2 mm, when the gate driver is implemented on the lower substrate, the area occupied by the circuit should be reduced to 2.2 mm or less.

On the other hand, since the effective area of the gate driver 52 varies depending on the position of the seal line 57 in the cell process of joining the upper and lower substrates, the position of the seal line 57 has emerged as an important factor in product development. .

According to the present invention, the signal line may be overlapped regardless of the position of the seal line 57, i.e., when the seal line 57 is overlapped on any portion (control signal line, input signal line or / and gate driver) outside the pixel portion 58. The present invention relates to a liquid crystal display device and a method of manufacturing the same, which do not cause corrosion or defects.

First embodiment

A liquid crystal display and a manufacturing method thereof according to the first embodiment of the present invention will be described below.

First, a liquid crystal display according to a first embodiment of the present invention will be described.

FIG. 7 is a structural cross-sectional view of the liquid crystal display according to the first exemplary embodiment of the present invention, taken along line III-III ′ and IV-IV ′ of FIGS. 6A and 6B.

As shown in FIG. 5, a liquid crystal panel 60 including upper and lower substrates 50 and 51 and a liquid crystal layer having a pixel portion defined therein, a gate driver 52, a source printed circuit board 54, and a data driver 55. And the timing controller 56, the control signal lines, the input signal lines, and the seal line 57, the liquid crystal display device according to the first embodiment of the present invention comprises: the control signal line; It is characterized by the structure of the seal line portion overlapped on the input signal line and the unit pixel region of the pixel portion, which will be described below with emphasis on the portion.

Prior to the description, III-III 'of FIG. 7 shows contact portions of control signal lines and input signal lines outside the pixel portion, and IV-IV' shows the thin film transistor and the pixel electrode portion in the pixel region of the pixel portion. Hereinafter, parts III-III 'and IV-IV' will be described as first and second regions.

6A, 6B, and 7, a sandwich structure in which a first transparent metal layer 81, a gate metal layer 82, and a second transparent metal layer 83 are stacked in a first region of the lower substrate 80. Control signal lines 86b are arranged in one direction.

In the second region, a gate line 86 having a sandwich structure in which the first transparent metal layer 81, the gate metal layer 82, and the second transparent metal layer 83 are stacked is arranged in one direction. The gate electrode 86a protrudes from one side.

The first and second transparent metal layers 81 and 83 are formed of ITO, IZO, or ITZO, and the gate metal layer 82 is formed of a double layer of Mo / AlNd or a single layer of Mo.

The pixel electrode 92 formed of a transparent metal layer is formed in the pixel region of the lower substrate 80, and the first and second contact holes 91a and 91b are formed in the pixel electrode 92 and the control signal line 86b. The gate insulating film 87 is formed on the entire surface of the lower substrate 80 so as to have a shape.

An active layer 88a formed of an amorphous silicon layer is formed on one region including the gate electrode 86a.

In addition, a data line 93 is formed to vertically cross the gate line 86 to define a pixel area, protrude from one side of the data line 93, and overlap the source electrode so as to overlap one side of the gate electrode 86a. A 93a is formed, and the drain electrode 93b is spaced apart from the source electrode 93a and overlaps the other side of the gate electrode 86b and contacts the pixel electrode 92 through the first contact hole 91a. .

An ohmic contact layer 89a formed of an n + amorphous silicon layer is formed between the active layer 88a, the source electrode 93a, and the drain electrode 93b.

An input signal line 93c is formed on the same layer as the data line 93 so as to contact the control signal line 86b through a second contact hole 91b. At this time, the input signal line 93c is a signal line input to the gate driver 52 (see FIG. 5).

The passivation layer 94 is formed on an entire surface of the lower substrate 80 including the data line 93 and the input signal line 93c.

Seal lines 57 and 95 (see FIG. 5) are formed on the protection film 94 to surround the pixel portion.

In this case, the seal lines 57 and 95 overlap the control signal line 86b and the input signal line 93c.                     

The seal line may overlap an upper portion of the gate driver mounted outside the pixel portion.

Next, a manufacturing method of the liquid crystal display device according to the first embodiment of the present invention having the above configuration will be described.

8A to 8F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention.

In FIGS. 8A to 8F, III-III ′ shows a contact portion between a control signal line and an input signal line outside the pixel portion, and IV-IV ′ shows a thin film transistor and a pixel electrode portion in the pixel region of the pixel portion. Hereinafter, the III-III 'and IV-IV' portions will be described as first and second regions.

In the method of manufacturing the liquid crystal display device according to the first embodiment of the present invention, as shown in FIG. 2, the transparent metal layer 83 is formed in order. In this case, the first and second transparent metal layers 81 and 83 are formed of ITO, IZO, or ITZO, and the gate metal layer 82 is formed of a double layer of Mo / AlNd or a single layer of Mo.

Subsequently, after the first photosensitive film 84 is applied to the entire lower substrate 80, the first photosensitive film 84 is selectively patterned by an exposure and development process using the first mask 85.

At this time, the first mask 85 is formed in half-tone in order to remove the gate metal layer 82 of the pixel region later and leave only the transparent metal layer, and the first photoresist film 84 of this portion is diffracted and exposed to lighter than other portions. It develops and forms a step.

Next, as shown in FIG. 8B, the second transparent metal layer 83, the gate metal layer 82, and the first transparent metal layer 81 having a sand position structure are sequentially etched using the patterned first photosensitive film 84 as a mask. The control signal line 86b is formed in the first region, and the gate line 86 (see FIG. 7) arranged in one direction is formed in the second region, and the gate electrode 86a and the pixel region portion protruded from one side thereof. The pixel pattern layer including the first transparent metal layer 81, the gate metal layer 82, and the second transparent metal layer 83 is formed.

Subsequently, the first photoresist layer 84 is ashed so that a part of the second transparent metal layer 83 of the pixel region is exposed, and then the gate metal layer 82 under the exposed second transparent metal layer 83 is exposed. The second transparent metal layer 83 is etched. Thereafter, the first photosensitive film 84 is removed.

Next, as shown in FIG. 8C, the gate insulating film 87, the amorphous silicon layer 88, and the n + amorphous silicon layer 89 are sequentially formed on the entire lower substrate 80. At this time, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film 87.

Subsequently, the n + amorphous silicon layer 89 and the amorphous silicon layer 88 are simultaneously patterned by a photolithography process and an etching process using a second mask.

Next, as shown in FIG. 8D, the second photoresist film 90 is coated on the entire lower substrate 80, and then the second photoresist film 90 is selectively patterned by an exposure and development process using a third mask. First and second contact holes 91a and 91b are formed on the gate metal layer 82 and the control signal line 86b of the region.

Subsequently, as shown in FIG. 8E, the gate metal layer 82 of the pixel region is removed by using an etchant as the mask for the second photosensitive film 90. At this time, H 3 PO 4 + HNO 3 + CH 3 COOH is used as an etchant for removing the gate metal layer 82. As a result, the pixel electrode 92 formed of the transparent metal layer is formed in the pixel region. Next, the second photosensitive film 90 is removed.

Subsequently, after depositing a metal layer on the entire lower substrate 80, the metal layer is etched by a photolithography process and an etching process using a fourth mask.

As a result, an input signal line 93c contacting the control signal line 86b is formed in the first region through the second contact hole 91b. At this time, the input signal line 93c is a signal line input to the gate driver.

In the second region, the data line 93 vertically intersects the gate line 86 to define a pixel region, and the source electrode 93a protruding from one side of the data line 93 and the source electrode 93a are spaced apart from each other. As a result, the drain electrode 93b is formed to contact the pixel electrode 92 and the first contact hole 91a.

When the metal layer is etched, the active layer 88a and the ohmic contact layer 89a are formed by overetching the n + amorphous silicon layer 89 so that the amorphous silicon layer 88 of the channel region is exposed.

Next, as shown in FIG. 8F, a protective film 94 is deposited on the entire lower substrate 80.

Thereafter, the seal lines 57 and 95 are formed to surround the pixel portion 58 (see FIG. 5). The seal lines 57 and 95 are formed on the upper portion of the control signal line 86b and the input signal line 93c. It is formed so that it overlaps.

Although not shown in the drawing, a plurality of switching transistors are formed in the gate driver 52 to transmit a signal input from the control signal line to the pixel unit through the input signal line and the output signal line. In this case, the switching transistors are formed using an a-Si: H amorphous silicon layer, and the size of the buffer TFT becomes very large due to the low mobility of the amorphous silicon layer.

In applying the technique of mounting the driving unit on the lower substrate using the a-Si: H amorphous silicon layer as described above, when the seal line can be overlapped on each signal line, the effective area of the gate driving unit 52 is increased. You can make the most of it.

In addition, even when the seal lines overlap each signal line as described above, a problem in which the seal lines are in direct contact with the signal lines as in the prior art does not occur. Therefore, defects in the signal lines are caused by the glass fibers constituting the seal lines. The problem does not occur.

Second embodiment

First, a liquid crystal display according to a second embodiment of the present invention will be described.

FIG. 9 is a cross-sectional view of a liquid crystal display according to a second exemplary embodiment of the present invention, taken along lines III-III 'and IV-IV' of FIGS. 6A and 6B.

In the liquid crystal display according to the second exemplary embodiment of the present invention, as shown in FIGS. 6A, 6B, and 9, the first transparent metal layer 101 / the gate metal layer 102 / the second transparent metal layer 103 are stacked. Among the control signal lines 106b, the gate lines 106 and the gate electrodes 106a having the sandwich structure, the gate metal layer 102, which is an intermediate layer, is formed to protrude from the first and second transparent metal layers 101 and 103. Since the configuration is the same as the liquid crystal display according to the first embodiment of the present invention, it will be omitted below.

Next, a method of manufacturing a liquid crystal display device according to a second embodiment of the present invention having the above configuration will be described.

10A through 10F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a second embodiment of the present invention.

In the method of manufacturing the liquid crystal display according to the second exemplary embodiment of the present invention, as shown in FIG. 10A, the first transparent metal layer 101, the gate metal layer 102, and the first metal layer 102 have a sandwich structure on the lower substrate 100. 2, the transparent metal layer 103 is formed in sequence. In this case, the first and second transparent metal layers 101 and 103 are formed of ITO, IZO, or ITZO, and the gate metal layer 102 is formed of a double layer of Mo / AlNd or a single layer of Mo.

Subsequently, after the first photosensitive film 104 is applied to the entire lower substrate 100, the first photosensitive film 104 is selectively patterned by an exposure and development process using a first mask.

In this case, the patterned first photoresist layer 104 is patterned to remain on the control signal line, the gate line and the gate electrode, and the pixel area.

Next, as shown in FIG. 10B, the second transparent metal layer 103, the gate metal layer 102, and the first transparent metal layer 101 having the sand position structure are sequentially etched using the patterned first photosensitive film 104 as a mask. . In this case, when the first transparent metal layer 101 is etched, the edge portion of the gate metal layer 102 is protruded by over-etching using an etchant in which the transparent metal layer is etched.

As a result, control signal lines 106b are formed in the first region, and gate lines arranged in one direction in the second region so that the gate metal layer 102 has a sandwich structure protruding from the first and second transparent metal layers 101 and 103. 9 (see FIG. 9) and a pixel pattern including a first transparent metal layer 101, a gate metal layer 102, and a second transparent metal layer 103 at a gate electrode 106a protruding from one side thereof and a pixel region portion thereof. A layer is formed. Thereafter, the first photosensitive film 104 is removed.

Next, as shown in FIG. 10C, the gate insulating film 107, the amorphous silicon layer 108, and the n + amorphous silicon layer 109 are sequentially deposited on the entire lower substrate 100. In this case, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film 107.

Subsequently, the n + amorphous silicon layer 109 and the amorphous silicon layer 108 are simultaneously patterned by a photolithography process and an etching process using a second mask.

Next, as shown in FIG. 10D, the second photoresist film 110 is coated on the entire lower substrate 100, and then the second photoresist film 110 is selectively patterned by an exposure and development process using a third mask. The first contact hole 111b is formed to expose the upper portion of the gate metal layer 102 in the region, and the second contact hole 111b is formed on the control signal line 106b.

Thereafter, as illustrated in FIG. 10E, the gate metal layer 102 of the pixel region is removed using an etchant as the mask for the second photosensitive film 110. At this time, H 3 PO 4 + HNO 3 + CH 3 COOH is used as an etchant for removing the gate metal layer 102. As a result, the pixel electrode 112 formed of the transparent metal layer is formed in the pixel region. Next, the second photosensitive film 110 is removed.

Subsequently, after depositing a metal layer on the entire lower substrate 100, the metal layer is etched by a photolithography process and an etching process using a fourth mask.

As a result, an input signal line 113c contacting the control signal line 106b is formed in the first region through the second contact hole 111b. At this time, the input signal line 113c is a signal line input to the gate driver.

In the second region, the data line 113 (refer to FIG. 9) defining the pixel area vertically intersecting with the gate line 106, the source electrode 113a protruding from one side of the data line 113, and the source electrode. A drain electrode 113b which is spaced apart from the 113a and contacts the pixel electrode 112 and the first contact hole 111a is formed.

When the metal layer is etched, the active layer 108a and the ohmic contact layer 109a are formed by overetching the n + amorphous silicon layer 109 so that the amorphous silicon layer 108 of the channel region is exposed.

Next, as shown in FIG. 10F, a protective film 114 is deposited on the entire lower substrate 100.

Thereafter, the seal lines 57 and 115 are formed to surround the pixel portion 58 (see FIG. 5). The seal lines 57 and 115 are formed on the upper portion of the control signal line 106b and the input signal line 113c. It is formed so that it overlaps.

Although not shown in the drawing, a plurality of switching transistors are formed in the gate driver 52 to transmit a signal input from the control signal line to the pixel unit through the input signal line and the output signal line. In this case, the switching transistors are formed using an a-Si: H amorphous silicon layer, and the size of the buffer TFT becomes very large due to the low mobility of the amorphous silicon layer.

In applying the technique of mounting the driving unit on the lower substrate using the a-Si: H amorphous silicon layer as described above, when the seal line can overlap each signal line, the effective area of the gate driving unit 52 is maximized. It can be utilized.

In addition, even if the seal lines overlap each signal line as described above, the problem is that the seal lines are not directly in contact with the signal lines as in the prior art. Therefore, defects in the signal lines are caused by the glass fibers constituting the seal lines. The problem does not occur.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the above embodiments, but should be defined by the claims.

The liquid crystal display of the present invention as described above and a manufacturing method thereof have the following effects.                     

First, even if the seal line is overlapped with the control signal line, the input signal line or / and the gate driver outside the pixel portion, no defect occurs in the signal line, so that the effective area of the driving circuit portion outside the pixel portion can be utilized to the maximum. have.

Second, since the number of masks can be reduced by one compared to the conventional five mask process, productivity can be improved.

Claims (10)

  1. A sandwich structure of first, second, and third conductive layers, the second conductive layer protruding from the first and third conductive layers, and vertically crossing the gate line to form a pixel region. A first substrate on which a data line and a pixel portion are defined;
    A second substrate opposed to the first substrate;
    A gate driver mounted on the first substrate outside the pixel unit;
    A data driver formed outside or inside a first substrate to apply a signal to the data line;
    A timing controller which outputs an image signal to the data driver and outputs a control signal to the gate driver through a control signal line having a sandwich structure in which first, second and third conductive layers are stacked; And
    A seal line formed between the first and second substrates and overlapping the control signal line outside the pixel portion or overlapping the control signal line and the gate driver; A liquid crystal display device.
  2. The method of claim 1,
    The pixel portion of the first substrate may include a gate line having a sandwich structure in which first, second and third conductive layers are stacked;
    A gate electrode protruding from one side of the gate line;
    A pixel electrode formed in the pixel region;
    A gate insulating film formed on the entire surface of the first substrate to have a first contact hole in the pixel electrode;
    An active layer formed of an amorphous silicon layer on one region including the gate electrode;
    A source electrode protruding from one side of the data line and overlapping an upper portion of one side of the gate electrode;
    A drain electrode spaced apart from the source electrode and overlapping the upper portion of the gate electrode to be in contact with the pixel electrode through the first contact hole;
    An ohmic contact layer including an n + amorphous silicon layer between the active layer, the source electrode, and the drain electrode; And
    And a passivation layer formed on the entire surface of the first substrate including the data line.
  3. The method according to claim 1 or 2,
    And the first and third conductive layers are made of a transparent metal layer, and the second conductive layer is made of a metal layer.
  4. delete
  5. In the method of manufacturing a liquid crystal display device having a pixel portion defined, and having a first substrate in which a gate driver is mounted outside the pixel portion,
    A control signal line is formed outside the pixel portion of the first substrate to form a sandwich structure in which the first, second, and third conductive layers are stacked using the first mask, and gate lines and gate electrodes are formed on the pixel portion. Forming a pixel pattern layer in the pixel region;
    Etching the third conductive layer to expose one region of the second conductive layer of the pixel pattern layer;
    Forming a gate insulating film over the first substrate;
    A fourth step of forming a semiconductor pattern over the gate electrode by using a second mask;
    A fifth step of forming first and second contact holes in the second conductive layer and the control signal line of the pixel pattern layer using a third mask;
    A sixth step of forming a pixel electrode in the pixel region by removing the second conductive layer of the pixel pattern layer;
    A data line vertically intersecting with the gate line to define the pixel region using a fourth mask, a source electrode protruding from one side of the data line, and a spaced apart from the source electrode, and the pixel electrode and the first contact hole Forming a drain electrode contacted through the second electrode and forming an input signal line contacting the control signal line through the second contact hole;
    An eighth step of depositing a protective film on the entire surface of the first substrate; And
    And a ninth step of forming a seal line along the periphery of the pixel portion so as to overlap the control signal line, the input signal line, or overlap the control signal line, the input signal line and the gate driver. Manufacturing method.
  6. The method of claim 5,
    The first and second steps may include sequentially depositing first, second and third conductive layers on the entire surface of the first substrate;
    Applying a first photoresist film on the third conductive layer;
    Patterning the first photoresist film using the first mask having a region corresponding to an upper portion of one region of the pixel region formed in half-tones;
    Forming the control signal line, the gate line, the gate electrode, and the pixel pattern layer having a sandwich structure using the patterned first photoresist film as a mask;
    Ashing the first photoresist layer to expose a portion of the third conductive layer in the pixel region;
    Etching the third conductive layer to expose the second conductive layer below the exposed third conductive layer; And
    And removing the first photosensitive film.
  7. In the method of manufacturing a liquid crystal display device having a pixel portion defined, and having a first substrate in which a gate driver is mounted outside the pixel portion,
    A control signal line outside the pixel portion, a gate line and a gate electrode in the pixel portion to have a sandwich structure in which the second conductive layer among the first, second, and third conductive layers is protrudingly stacked using a first mask. And a first step of forming a pixel pattern layer in the pixel region;
    Forming a gate insulating film on the entire surface of the first substrate;
    A third step of forming a semiconductor pattern on the top including the gate electrode using a second mask;
    A fourth step of forming first and second contact holes to expose the second conductive layer of the pixel pattern layer and the third conductive layer of the control signal line by using a third mask;
    A fifth step of forming a pixel electrode in the pixel region by removing the second conductive layer of the pixel pattern layer;
    A data line vertically intersecting with the gate line to define the pixel region using a fourth mask, a source electrode protruding from one side of the data line, and a spaced apart from the source electrode, and the pixel electrode and the first contact hole Forming a drain electrode contacted through the second electrode and forming an input signal line contacted with the control signal line through the second contact hole;
    Depositing a passivation layer on the entire surface of the first substrate; And
    And an eighth step of forming a seal line along the periphery of the pixel portion so as to overlap the control signal line and the input signal line or overlap the control signal line, the input signal line and the gate driver. Manufacturing method.
  8. The method of claim 7, wherein
    The first step may include depositing first, second and third conductive layers sequentially on the entire surface of the first substrate;
    Applying a first photoresist film on the third conductive layer;
    Patterning the first photoresist film using the first mask;
    A sandwich structure in which the third, second and first conductive layers are sequentially etched using the patterned first photoresist film as a mask, and the first and third conductive layers are excessively etched to protrude edge portions of the second conductive layer. Forming the control signal line, the gate line, the gate electrode, and the pixel pattern layer to have a; And
    And removing the first photosensitive film.
  9. The method according to claim 5 or 7,
    The first and third conductive layers are formed of a transparent metal layer, and the second conductive layer is formed of a metal layer.
  10. The method according to claim 5 or 7,
    And the second conductive layer of the pixel pattern layer is removed using an etchant of H 3 PO 4 + HNO 3 + CH 3 COOH.
KR1020040030625A 2004-04-30 2004-04-30 Lipuid crystal display device and method for fabricating the same KR101009680B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010053696A (en) * 1999-12-01 2001-07-02 윤종용 Thin film transistor array panel for liquid crystal display
KR100435347B1 (en) * 1996-03-23 2004-12-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method of manufacturing liquid crystal device and method of manufacturing active matrix type display device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100435347B1 (en) * 1996-03-23 2004-12-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method of manufacturing liquid crystal device and method of manufacturing active matrix type display device
KR20010053696A (en) * 1999-12-01 2001-07-02 윤종용 Thin film transistor array panel for liquid crystal display
KR100635945B1 (en) 1999-12-01 2006-10-18 삼성전자주식회사 Thin film transistor array panel for liquid crystal display and method for manufacturing the same

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