KR101073009B1 - Capacitor and method for fabricating the same - Google Patents

Abstract

The present invention is to provide a capacitor and a method of manufacturing the capacitor that can reduce the manufacturing cost by simplifying the manufacturing process in the capacitor manufacturing process of the semiconductor memory device, the present invention is a storage node contact plug formed by a selective growth method, A capacitor includes a storage node formed on the storage node contact plug, a dielectric film formed along a step surface of the storage node, and a plate formed on the dielectric film.

Capacitors, Cylindrical Storage Nodes, Storage Node Contact Plugs

Description

Capacitor and Method for Manufacturing the Same {CAPACITOR AND METHOD FOR FABRICATING THE SAME}

TECHNICAL FIELD The present invention relates to semiconductor manufacturing techniques, and more particularly, to a capacitor and a method for manufacturing the same, and more particularly, a capacitor including a storage node contact plug and a method for manufacturing the same.

Semiconductor memory devices require a capacitor to implement a memory function. In general, capacitors have become common to form storage nodes cylindrically to increase capacitance per unit area. The storage node used as the lower electrode of the capacitor is electrically connected to the lower semiconductor structure through the storage node contact plug. In general, the storage node contact plug forms a contact hole in the insulating film, and forms a contact hole in the contact hole, and then forms an etchback process so that the process becomes more complicated and the manufacturing cost increases accordingly. have.

Therefore, the present invention has been proposed to solve the problems according to the prior art, and has the following objects.

First, it is an object of the present invention to provide a capacitor and a method of manufacturing the same that can reduce the manufacturing cost by simplifying the manufacturing process in the capacitor manufacturing process of the semiconductor memory device.

Second, an object of the present invention is to provide a capacitor and a method of manufacturing the same, which can increase the capacitance per unit area without increasing the height of the storage node while increasing the density of the semiconductor memory device.

According to an aspect of the present invention, a storage node contact plug formed by a selective growth method, a storage node formed on the storage node contact plug, a dielectric film formed along a step surface of the storage node, A capacitor including a plate formed on the dielectric film is provided.

According to another aspect of the present invention, there is provided a method of forming a storage node contact plug using a selective growth method on a substrate, forming a storage node on the storage node contact plug, A method of manufacturing a capacitor includes forming a dielectric film along a stepped surface of the storage node, and forming a plate on the dielectric film.

According to the present invention including the above-described configuration, the following effects can be obtained.

First, according to the present invention, by forming a storage node contact plug by a selective growth method rather than a deposition process, a deposition process and an etch back process, which require a deposition process, can be omitted, thereby simplifying a manufacturing process. The unit price can be lowered.

Second, according to the present invention, it is possible to increase the area of the storage node of the capacitor per unit area without increasing the height of the storage node by extending the connection layer connecting the storage node contact plug and the storage node between the storage node larger than the width of the storage node. A high capacitance can be obtained while improving the high integration of the device.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described.

In the drawings, the thicknesses and spacings of layers (areas) are exaggerated for ease of explanation and clarity, and when referred to as being on another layer or substrate 'top' it may be a different layer or It may be formed directly on the substrate, or a third layer may be interposed therebetween without departing from the technical spirit of the present invention. In addition, parts denoted by the same reference numerals represent the same layer, and when the reference numerals include English, it means that the same layer is partially deformed through an etching or polishing process.

Example

1 is a cross-sectional view illustrating a capacitor according to an embodiment of the present invention.

Referring to FIG. 1, a capacitor according to an exemplary embodiment of the present invention includes a storage node contact plug 107 formed by Selective Epitaxial Growing (SEG).

The storage node contact plug 107 may be grown from the semiconductor substrate 101 by a selective growth method or from a landing plug made of a polysilicon film formed on the semiconductor substrate 101. Here, the term “landing plug” refers to a contact plug electrically connecting the junction region (source region or drain region) formed in the semiconductor substrate 101 to the storage node contact plug 107. Depending on the manufacturing process, the landing plug may not be formed. When the landing plug is not formed, it is grown and formed on the semiconductor substrate 101. The storage node contact plug 107 is formed of Si or SiGe doped with a P-type or N-type dopant.

In addition, the capacitor according to the embodiment of the present invention includes the storage node 111A formed on the storage node contact plug 107, the dielectric film 113 formed along the step surface of the storage node 111A, and the dielectric film 113. It further comprises a plate 114 formed on). In addition, the semiconductor device may further include a connection layer 108 formed to cover the storage node contact plug 107.

The connection layer 108 is formed between the storage node contact plug 107 and the storage node 111A. The connection layer 108 is formed to be wider than the storage node 111A. The connection layer 108 is connected to the storage node 111A and becomes part of the storage node 111A. Accordingly, the area of the storage node 111A per unit area can be expanded (see A and B original drawings) without increasing the height of the storage node 111A as the connection layer 108 is expanded.

The connection layer 108 may be formed of the same material as the storage node 111A. Furthermore, the storage node contact plug 107 may be formed of the same material. In addition, the plate 114 may be formed of the same material. Preferably, the connection layer 108 is formed of a polycrystalline silicon film. More preferably, a dopant is formed of a doped polysilicon film. The connection layer 108 is doped at a concentration of 1 × 10 ²⁰ to 3 × 10 ²² atoms / cm ³ .

Hereinafter, a method of manufacturing a capacitor according to an embodiment of the present invention shown in FIG. 1 will be described.

2A to 2J are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.

First, as shown in FIG. 2A, a semiconductor substrate 101 on which a structure is formed is prepared through a series of manufacturing processes. The structure may include a doped region, a junction region (source region and drain region), a contact plug, an active element, a passive element, an insulating layer, a conductive layer, and the like. In this case, the contact plug may be a landing plug and may be formed of a polysilicon film doped with a dopant.

Next, an insulating layer 105 for forming a storage node contact plug pattern is formed to cover the structure. The insulating film 105 is formed in a multilayer insulating film structure in which an oxide film and a nitride film are mixed. For example, BPSG (BoroPhosphoSilicate Glass) 102, TEOS (Tetra Ethyle Ortho Silicate) 103, and nitride film 104 are formed as a laminated film sequentially stacked.

Subsequently, as illustrated in FIG. 2B, the insulating layer 105 (see FIG. 2A) is etched to expose the top surface of the semiconductor substrate 101 to form a contact hole 106 in which a storage node contact plug is to be formed. Hereinafter, in order to match the reference numerals shown in the drawings, the insulating film is referred to as '105A', the BPSG is '102A', the TEOS is 103A and the nitride film is referred to as '104A'.

Subsequently, a cleaning process may be performed on the upper surface of the semiconductor substrate 101 exposed through the contact hole 106. The cleaning process is performed using a hydrofluoric acid solution to remove an oxide film remaining on the upper surface of the semiconductor substrate 101, and an aqueous ammonia solution (SC (Standard Cleaning-1) to remove particles). And a third step of using a hydrochloric acid aqueous solution (SC-2) to remove metal contamination.

Subsequently, as illustrated in FIG. 2C, the storage node contact plug 107 is formed using a selective growth method so that the contact hole 107 is buried. At this time, the storage node contact plug 107 is formed by growing Si doped with dopants or by growing SiGe.

First, the contact hole 106 may be buried in-situ doped with Si or SiGe. In both cases growth rate is very important. Since the height of the contact hole 106 is high enough to correspond to thousands to tens of thousands of kPa when the landing plug is not formed, mass productivity may be degraded when the epitaxial growth rate is low.

When growing Si, it is preferable to use DCS (DiChloroSilane (SiH ₂ Cl ₂ )) rather than SiH ₄ or Si ₂ H ₆ as the silicon source. In addition, it is preferable to use a dopant source as an additive in order to increase the growth rate. As the dopant source, any one of PH ₃ , AsH ₃ or B ₂ H ₆ is selected and used. The injection amount of the dopant is 10 ppm or more, preferably 10 to 100 ppm. During Si growth, a silicon source and a dopant source are implanted together into a growth chamber to grow in-situ. At this time, it is preferable to perform process progress temperature at 600-750 degreeC. As described above, the reason why the Si growth process is performed at a high temperature and the dopant is added is that as the temperature increases, the Si growth rate increases, and when the dopant gas is added to the DCS gas, the growth rate increases. . However, in the case of DRAM devices, since the capacitor manufacturing process is performed after the transistor manufacturing process is completed, it is a reality that a high temperature process cannot be performed during the growth process in order to prevent deterioration of device characteristics due to subsequent thermal processes. Therefore, the temperature during the growth step is preferably carried out at 750 ℃ or less. If the temperature is lowered, the growth rate decreases, and in order to compensate for this, a sufficient amount of dopant source must be supplied, thereby increasing the growth rate to several hundreds / min.

In order to further increase the growth rate, it is preferable to grow SiGe instead of Si. SiGe varies in growth rate depending on the content of Ge. As shown in Figure 4, it can be seen that the growth rate increases exponentially as the Ge content increases during the SiGe growth process. When the content of Ge is 50%, the growth rate reaches 800 mW / min at 700 ° C. In addition, the addition of the dopant additive can further increase the growth rate to grow at a rate of 1000 kW / min or more.

In the case of growing SiGe, DCS is used as the silicon source as in Si growth. As the dopant source, any one of PH ₃ , AsH ₃ or B ₂ H ₆ is selected and used. The injection amount of the dopant is 10 ppm or more, preferably 10 to 100 ppm. These sources are then injected in-situ together into the growth chamber to grow SiGe. The higher the content of Ge in the SiGe growth layer relative to Si, the better the property may be. Preferably it is 20% or more, More preferably, it is 20%-80%. SiGe growth is performed at a lower temperature than Si growth. For example, it performs at the temperature of 500-750 degreeC.

Subsequently, as shown in FIG. 2D, a connection layer 108 that becomes part of the storage node may be further formed on the substrate 101 including the nitride film 104A and the storage node contact plug 107. The connection layer 108 is formed of the same material as the storage node contact plug 107. The connection layer 108 is formed using a furnace (furnace) equipment or sheet-type chemical vapor deposition (CVD) equipment. The connection layer 108 is formed to a thickness of 300 GPa or more, preferably 300 to 1000 GPa. The connection layer 108 is formed of a polysilicon film, and the source gas during the deposition process, that is, SiH ₄ Together with the gas, a PH ₃ or AsH ₃ gas is injected into the dopant source in an in-situ process to form a doped polycrystalline silicon film.

Next, an insulating film 109 (hereinafter referred to as a first sacrificial film) is formed on the connection layer 108. The first sacrificial layer 109 has a high etching selectivity with the connection layer 108 and the storage node 111A (see FIG. 2G) in a subsequent removal process, and is formed of a material that can be selectively removed by an etching solution. Preferably, it is formed of an oxide film. More preferably, it is formed of TEOS.

Subsequently, the first sacrificial layer 109 is etched to form the pattern holes 110 on which the storage node 111A is to be formed. In this case, the etching process is performed by a dry etching process, and the connection layer 108 is exposed. The pattern hole 110 may be formed in a circle (including a semi-circle, an ellipse) or a polygon (including a triangle, a rectangle, a pentagon, a hexagon, an octagon, etc.) according to the shape of a mask used in an etching process, and the storage node contact plug 107. It is formed in the area opposite to). Preferably, it is formed to have a wider width than the storage node contact plug 107.

Subsequently, as illustrated in FIG. 2E, the conductive layer 111 is formed on the first sacrificial layer 109 including the pattern hole 110 along the stepped surface of the pattern hole 110. The conductive layer 111 is formed along the outer surface of the first sacrificial layer 109 including the pattern hole 110. The conductive film 111 is formed of the same material as the connection layer 108. Preferably, it is formed of a polycrystalline silicon film. More preferably, a polycrystalline silicon film doped with impurity ions is formed.

Subsequently, as shown in FIG. 2F, an insulating film 112 (hereinafter referred to as a second sacrificial film) is formed on the conductive film 111 so that the pattern hole 110 is filled. The second sacrificial layer 112 is formed of the same material as the first sacrificial layer 109 so that the second sacrificial layer 112 may be removed together during the subsequent process of removing the first sacrificial layer 109. Preferably, it is formed of an oxide film. More preferably, it is formed of TEOS.

Subsequently, the second sacrificial layer 112 is recessed to a predetermined depth to expose the conductive layer 111 formed on the first sacrificial layer 109. In other words, an etchback process is performed until the conductive film 111 is exposed. Accordingly, the second sacrificial layer 112 is isolated inside the pattern hole 110.

Subsequently, as illustrated in FIG. 2G, the conductive film 111 (see FIG. 2F) exposed without being covered by the second sacrificial layer 112 is selectively etched to form a cylindrical storage node 111A. In this case, the etching process is performed by an etch back process, which is a dry etching process, and the etch back process is performed until the first sacrificial layer 109 is exposed using the conductive layer 111 as an etching target.

Next, as shown in FIG. 2H, the second sacrificial layer 112 (see FIG. 2G) and the first sacrificial layer 109 (see FIG. 2G) are etched and removed. At this time, the etching process is performed by a wet etching process. The wet etching process is formed of an etching solution having a high etching selectivity between the oxide film and the polycrystalline silicon film. Preferably, the oxide film may be selectively etched, more preferably, using a BOE (Buffered Oxide Etch), BHF (Buffered HF) or DHF (Diluted HF) solution. As a result, the storage node 111A and the connection layer 108 are exposed.

Subsequently, as shown in FIG. 2I, the dielectric film 113 is formed along the stepped surface of the substrate 101 including the storage node 111A and the connection layer 108. The dielectric film 113 is formed of an oxide film or a laminated film in which an oxide film and a nitride film are alternately stacked (for example, an oxide film / nitride film / oxide film) or a metal oxide film having a dielectric constant of 3.9 or more. As the metal oxide film, an aluminum oxide film (Al ₂ O ₃ ), a hafnium oxide film (HfO ₂ ), a zirconium oxide film (ZrO ₂ ), a tantalum oxide film (Ta ₂ O ₅ ) or a mixed film in which these are mixed, or a laminated film in which they are sequentially stacked To form.

Subsequently, as shown in FIG. 2J, a plate 114 is formed on the dielectric layer 113 to cover the storage node 111A and the connection layer 108. The plate 114 is formed of the same material as the storage node 111A and the connection layer 108. For example, it is formed of a transition metal film or a polycrystalline silicon film. Preferably, it is formed of a polysilicon film doped with impurity ions.

Subsequently, the plate 114, the dielectric film 113, and the connection layer 108 may be etched to finally form a desired profile, thereby implementing the same profile as in FIG.

As described above, although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not for the purpose of limitation. As such, those skilled in the art may understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a cross-sectional view showing a capacitor according to an embodiment of the present invention.

2A to 2J are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.

3 is a graph showing growth rate with respect to the amount of dopant added during the Si growth process.

4 is a graph showing growth rate with respect to the amount of dopant added during the SiGe growth process.

<Explanation of symbols for the main parts of the drawings>

101: substrate

102, 102A: BPSG

103, 103A: TEOS

104, 104A: nitride film

105, 105A: insulating film

106: contact hole

107: storage node contact plug

108: connection layer

109: first sacrificial film

110: pattern hole

111: conductive film (for storage node)

111A: Storage Node

112: second sacrificial film

113: dielectric film

114: plate

Claims (24)

A storage node contact plug formed by a selective growth method; A connection layer formed to cover the storage node contact plug; A storage node formed on the connection layer to have a narrower width than the connection layer to expose a portion of the connection layer; A dielectric film formed on the stepped surface of the storage node and the exposed connection layer; And A plate formed on the dielectric film Capacitor comprising a. delete delete delete The method of claim 1, The storage node contact plug is a capacitor consisting of Si or SiGe doped with dopants. Forming a storage node contact plug on the substrate using a selective growth method; Forming a connection layer formed to cover the storage node contact plug; Forming a storage node on a top surface of the connection layer with a narrower width than the connection layer; Forming a dielectric film to cover the connection layer and the top surface of the storage node along the stepped surface of the storage node; And Forming a plate on the dielectric film Method of manufacturing a capacitor comprising a. delete The method of claim 6, Forming the storage node, The manufacturing method of a capacitor formed in a cylindrical shape on the said connection layer so that a part of said connection layer may be exposed. The method of claim 8, Forming the storage node, Forming a first sacrificial layer on the connection layer; Etching the first sacrificial layer to form a pattern hole through which a portion of the connection layer is exposed; Forming a conductive film on the first sacrificial layer and the connection layer along the stepped surface of the pattern hole; Forming a second sacrificial layer on the conductive layer to fill the pattern hole; Recessing the second sacrificial layer to expose the conductive layer formed on the first sacrificial layer; Etching the conductive layer formed on the first sacrificial layer to form a cylindrical storage node; And Removing the first and second sacrificial layers Method of manufacturing a capacitor comprising a. The method of claim 9, And the storage node is formed of the same material as the connection layer. 11. The method of claim 10, And the conductive film is formed of a polysilicon film. The method of claim 11, The first and second sacrificial films are formed of an oxide film. The method of claim 8, Forming the dielectric film, And a capacitor formed along the stepped surfaces of the exposed connection layer and the storage node. The method of claim 13, And the connection layer is formed of a polysilicon film doped with a dopant. The method according to any one of claims 6 and 8 to 14, Before forming the storage node contact plug, And performing a cleaning process on the surface of the substrate. The method of claim 15, The washing step, A first step of cleaning the surface of the substrate using an aqueous hydrofluoric acid solution; A second step of cleaning the surface of the substrate using an aqueous ammonia solution; And A third step of cleaning the surface of the substrate using an aqueous hydrochloric acid solution Method of manufacturing a capacitor comprising a. The method according to any one of claims 6 and 8 to 14, The storage node contact plug is formed of Si or SiGe. The method of claim 17, The selective growth method is a capacitor manufacturing method using a DCS (DiChloroSilane (SiH ₂ Cl ₂ )) as a silicon source. The method of claim 18, The selective growth method is PH ₃ , AsH ₃ as a dopant source Or a method for producing a capacitor using any one of B ₂ H ₆ . The method of claim 19, The dopant source injection amount is 10ppm ~ 100ppm manufacturing method of the capacitor. The method of claim 17, When forming with said Si, the manufacturing method of the capacitor performed at the temperature of 600-750 degreeC. The method of claim 17, When forming with said SiGe, the manufacturing method of a capacitor performed at the temperature of 500-750 degreeC. The method of claim 17, When formed of the SiGe, the content of Ge is 20% to 80% of the manufacturing method of the capacitor. The method of claim 17, And the storage node and the plate are formed of a polysilicon film doped with a dopant of the same conductivity type as the storage node contact plug.

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