KR101070974B1

KR101070974B1 - Wafer level light emitting diode package

Info

Publication number: KR101070974B1
Application number: KR1020090068694A
Authority: KR
Inventors: 이광철; 김재필; 송상빈; 김상묵
Original assignee: 한국광기술원
Priority date: 2009-07-28
Filing date: 2009-07-28
Publication date: 2011-10-06
Also published as: KR20110011171A

Abstract

A wafer level light emitting diode package is provided. The light emitting diode package is disposed on an upper surface of the substrate, and exposes an edge portion of the upper surface of the substrate, and a first type semiconductor layer disposed on the first type semiconductor layer, the upper surface of the first type semiconductor layer. A light emitting structure having a second type semiconductor layer exposing at least a portion thereof, a first type electrode disposed on the first type semiconductor layer, and a top surface of the first type electrode disposed on the second type semiconductor layer; A second type electrode having a top surface of the same level, a heat sink layer disposed on the second type semiconductor layer, and having a top surface of the same level as the top surface of the electrodes, and the first type electrode and the second type And an insulating film disposed on the substrate except for an electrode and the heat sink layer and having an upper surface at the same level as the top surface of the electrodes and the heat sink layer.

Wafer Level Light Emitting Diode Package, Radiator Layer, Wavelength Pillar

Description

Wafer level light emitting diode package

The present invention relates to light emitting diodes, and more particularly, to a wafer level light emitting diode package.

A light emitting diode (LED) is a semiconductor device that converts current into light and is mainly used as a light source of a display device. These light emitting diodes are very small compared to the conventional light sources, have very low power consumption, long lifespan, and fast reaction speed. In addition, it does not emit harmful electromagnetic waves such as ultraviolet rays, and is environmentally friendly since it does not use mercury and other discharge gases.

However, such a light emitting diode is accompanied with a problem that heat is generated when light is generated. Since the heat is directed to the inside of the module, there is a problem of shortening the life of the light emitting diode by causing breakage and deformation of a circuit board such as a light emitting diode chip or a PCB.

In addition, when heat is concentrated in a part of the light emitting diode chip, there is a problem in that the color temperature difference between the light emitting diode chips is generated due to low luminous efficiency. Accordingly, a method for reducing such heat and improving luminous efficiency is required.

In addition, LED packages are increasingly required to be highly efficient and inexpensive. Therefore, for this purpose, there is a need for a light emitting diode package in which a structure using technology for high efficiency and a structure in which technology for low cost is applied.

The present invention has been made in an effort to provide a light emitting diode package capable of efficiently removing heat in the light emitting diode package.

In addition, the technical problem to be solved by the present invention is to provide a light emitting diode package with improved luminous efficiency.

In addition, the technical problem to be solved by the present invention is to provide a wafer-level light emitting diode package that can reduce the manufacturing cost.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, an aspect of the present invention provides a wafer level light emitting diode package. The light emitting diode package is disposed on an upper surface of the substrate, and exposes an edge portion of the upper surface of the substrate, and a first type semiconductor layer disposed on the first type semiconductor layer, the upper surface of the first type semiconductor layer. A light emitting structure having a second type semiconductor layer exposing at least a portion thereof, a first type electrode disposed on the first type semiconductor layer, and a top surface of the first type electrode disposed on the second type semiconductor layer; A second type electrode having a top surface of the same level, a heat sink layer disposed on the second type semiconductor layer, and having a top surface of the same level as the top surface of the electrodes, and the first type electrode and the second type And an insulating film disposed on the substrate except for an electrode and the heat sink layer and having an upper surface at the same level as the top surface of the electrodes and the heat sink layer.

The first type electrode includes a first type upper electrode and a first type lower electrode, and the first type lower electrode includes main part electrodes and both main part electrodes positioned on both side edges of the first type semiconductor layer. A plurality of branch electrodes may be provided from each of the electrodes to a central portion of the upper surface of the first type semiconductor layer.

The second type semiconductor layer is spaced apart from the first type electrode and is located between the main part semiconductors and the branched electrodes of the first type lower electrode from the main part semiconductors positioned in the center portion of the first type semiconductor layer. It may have a plurality of branched semiconductors extending.

The method may further include a first type electrode connector layer disposed between the first type upper electrode and the main electrode of the first type lower electrode. The first type electrode connector layer may be a mixed layer of any one of Cr, Ni, or Ti, and any one of Au, Al, Cu, Mo, W, Ag, Sn, or Pd.

The second type electrode includes a second type top electrode and a second type bottom electrode, and the second type bottom electrode is formed from a main part electrode and a main part electrode located on one side edge of the second type semiconductor layer. A plurality of branch electrodes extending to the center portion of the upper surface of the second type semiconductor layer may be provided.

The display device may further include a second type electrode connector layer disposed between the main part electrode of the second type upper electrode and the second type lower electrode. The second type electrode connector layer may be spaced apart from the branch electrodes and may have a plurality of rod shapes.

The second type electrode connector layer may be a mixed layer of any one of Cr, Ni, or Ti, and any one of Au, Al, Cu, Mo, W, Ag, Sn, or Pd.

The radiator connection layer may be further provided between the second type semiconductor layer and the radiator layer. The radiator connection layer may be a mixed layer of any one of Cr, Ni, or Ti, and any one of Au, Al, Cu, Mo, W, Ag, Sn, or Pd.

The light emitting diode package may further include a wavelength conversion pillar disposed in the insulating layer and the plurality of through holes penetrating the edges of the substrate, and a wavelength conversion layer disposed on the lower surface of the substrate. The insulating film may contain a wavelength conversion material.

The light emitting diode package may further include a reflective layer disposed between the second type semiconductor layer and the heat sink layer. The reflective layer may be an Ag layer or an Al layer. The semiconductor device may further include a transparent conductive film disposed between the second type semiconductor layer and the reflective layer. The transparent conductive film may contain ITO, IZO or AZO.

As described above, the light emitting diode package according to the present invention includes a heat sink layer thermally connected to the light emitting structure, thereby rapidly dissipating heat generated from the light emitting structure to the outside.

In addition, since the electrode electrically connected to the first type semiconductor layer or the second type semiconductor layer has a branched shape, it is possible to smoothly flow the current of the first type semiconductor layer or the second type semiconductor layer, so that the luminous efficiency is improved. This can be improved.

Further, a wafer or a wafer-level light emitting diode package (wafer-level) is used by using a substrate or wafer for forming the first type semiconductor layer, the second type semiconductor layer, or the like as a frame for the skeleton of the package. Since the light-emitting diode package can be implemented, the manufacturing cost can be greatly reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

1 is a cross-sectional view showing a light emitting diode package according to the present invention.

Referring to FIG. 1, a first type semiconductor layer 22 disposed on an upper surface of the light emitting diode substrate 10 and exposing an edge of an upper surface of the substrate 10, and the first type semiconductor layer ( A light emitting structure having a second type semiconductor layer 26 disposed on the substrate 22 and exposing at least a portion of an upper surface of the first type semiconductor layer 22.

The first type electrode 31 is disposed on the first type semiconductor layer 22 of the light emitting structure, and the first type electrode 31 is disposed on the second type semiconductor layer 26 at the same level as the top surface of the first type electrode 31. A second type electrode 32 having an upper surface is disposed. In this case, the first type electrode 31 and the second type electrode 32 may include a first type upper electrode and a first type lower electrode, and a second type upper electrode and a second type lower electrode, respectively. In addition, a first type electrode connector and a second type electrode connector may be included between the first type upper electrode and the first type lower electrode and the second type upper electrode and the second type lower electrode, respectively.

In addition, a heat sink layer 44 having an upper surface at the same level as the first type electrode 31 and the second type electrode 32 is disposed on the second type semiconductor layer 26. In this case, the radiator layer 44 may be in contact with the second type semiconductor layer 26 by a radiator connection layer.

On the substrate 10 except for the first type electrode 31, the second type electrode 32, and the heat sink layer 44, the upper surface has the same level as the upper surface of the electrodes 31 and 32. An insulating film 48 is disposed, and the insulating film 48 may contain a wavelength conversion material.

In addition, the light emitting diode package may include a wavelength conversion pillar disposed in a plurality of through holes passing through the insulating layer 48 and the edge of the substrate 10 and a wavelength conversion layer disposed on the bottom surface of the substrate 10. It may be further provided.

Hereinafter, a method of manufacturing a light emitting diode package according to an embodiment of the present invention will be described in detail.

2A to 2L are cross-sectional views illustrating a method of manufacturing a light emitting diode package according to an embodiment of the present invention, and FIGS. 3A to 3L are plan views illustrating top surfaces of FIGS. 2A to 2L, respectively. In this case, the cross-sectional views of FIGS. 2A to 2L correspond to cross-sections taken along the cutting line II ′ of FIGS. 3A to 3L.

2A and 3A, a first type semiconductor layer 22 is formed on the substrate 10. The substrate 10 may be a substrate made of a light transmissive material. The substrate 10 may be an Al ₂ O ₃ (sapphire), SiC, GaAs, InP, AlN or GaN substrate. Preferably, the substrate 10 may be an Al ₂ O ₃ substrate.

An upper surface of the substrate 10 on which the first type semiconductor layer 22 is formed may have a flat surface, and a lower surface of the substrate 10 may be provided with a flat shape or a plurality of grooves. It can have a surface. When the lower surface of the substrate 10 has a concave-convex surface, when the light emitting structure S is mounted in a flip chip form, total reflection can be prevented, thereby improving external quantum efficiency.

The first type semiconductor layer 22 may be a group III-V compound semiconductor layer or a group II-VI compound semiconductor layer implanted with a first type impurity, for example, an n-type impurity. Specifically, the first type semiconductor layer 22 may be a GaN layer, a GaAs layer, or an InGaAs layer.

A buffer layer (not shown) may be further disposed between the substrate 10 and the first type semiconductor layer 22 to reduce the lattice defect between the substrate 10 and the first type semiconductor layer 22. The buffer layer may be an AlN layer, an InP layer, or a GaN layer.

An active layer 24 may be formed on the first type semiconductor layer 22. The active layer 24 may have a quantum dot structure or a multi quantum well structure.

The second type semiconductor layer 26 may be formed on the active layer 24. The second type semiconductor layer 26 may be a III-V compound semiconductor layer or a II-VI compound semiconductor layer implanted with a second type impurity, that is, a p-type impurity. In detail, the second type semiconductor layer 26 may be a GaN layer, a GaAs layer, or an InGaAs layer.

The reflective layer 28 may be formed on the second semiconductor layer 26. The reflective layer 28 may be an Ag layer or an Al layer. In addition, a transparent conductive film may be further provided between the second type semiconductor layer 26 and the reflective layer 28. The transparent conductive film may contain ITO, IZO or AZO.

The first type semiconductor layer 22, the active layer 24, the second type semiconductor layer 26, and the reflective layer 28 may use a metal organic chemical vapor deposition (MOCVD) technique or a molecular beam epitaxy (MBE) technique. Can be used.

2B and 3B, the second type semiconductor layer 26, the active layer 24, the first type semiconductor layer 22, and the reflective layer 28 are sequentially patterned to form an upper surface of the substrate 10. Exposing an edge portion of the semiconductor substrate, and etching part of the reflective layer 28, the second type semiconductor layer 26, and the active layer 24 to expose at least a portion of an upper surface of the first type semiconductor layer 22. You can.

Accordingly, the light emitting diode is disposed on the top surface of the substrate 10, but exposes the first type semiconductor layer 22 and the first type semiconductor layer 22 to expose edge portions of the top surface of the substrate 10. A second type semiconductor layer 26 disposed on the second semiconductor layer 26 to expose at least a portion of an upper surface of the first type semiconductor layer 22 and a reflective layer 28 disposed on the second type semiconductor layer 26. The light emitting structure S may be provided.

2C and 3C, a first lower electrode 31 and a second lower electrode 32 are formed on the first type semiconductor layer 22 and the reflective layer 28. In this case, the second type lower electrode 32 may have a branch shape. In other words, the main electrode may be provided on one edge of the upper surface of the reflective layer 28 and a plurality of branch electrodes may extend from the main electrode to the center portion of the upper surface of the reflective layer 28.

When the second type lower electrode 32 has a branch shape as described above, when a voltage is applied to the light emitting diode package, current may be smoothly supplied over the entire area of the second type semiconductor layer 26. , The luminous efficiency can be improved.

The lower electrodes 31 and 32 may have an ohmic contact property and adhesion to dissimilar compounds and metals, and may be layers of an electrically conductive material having a diffusion preventing function that prevents electrical and thermal diffusion. As an example, the lower electrodes 31 and 32 may be a mixed layer of any one of Cr, Ni, or Ti, and any one of Au, Al, Cu, Mo, W, Ag, Sn, or Pd.

In this case, when the reflective layer 28 is omitted, the second type lower electrode 32 may be formed on the second type semiconductor layer 26.

2D and 3D, branch portions of the first lower electrode 31, the main electrode of the second lower electrode 32, and the second lower electrode 32 of the reflective layer 28 are illustrated. A photoresist pattern 29 is formed to expose the exposed areas adjacent to the electrode.

2E and 3E, the adhesive layer 30 is formed on the regions exposed by the photoresist pattern 29. The adhesive layer 30 has good adhesion to heterogeneous compounds, metals, and the like, and may be a material layer having a diffusion preventing function that prevents electrical and thermal diffusion. As an example, the adhesive layer 30 may be a mixed layer of any one of Cr, Ni, or Ti, and any one of Au, Al, Cu, Mo, W, Ag, Sn, or Pd.

In this case, the adhesive layer 30 may be formed on the photoresist pattern 29 as well as the regions exposed by the photoresist pattern 29.

The adhesive layer 30 and the lower electrodes 31 and 32 may be formed using sputtering, electron beam deposition, thermal deposition, pulsed laser deposition, or laser molecular beam deposition. However, the adhesive layer 30 may be omitted.

Referring to FIGS. 2F and 3F, the first and second first and second electrodes 31 and 31 are respectively connected to the first lower electrode 31, the main electrode of the second type lower electrode 32, and the reflective layer 28 on the adhesive layer 30. Second type electrode connection layers 33 and 35 and a heat sink connection layer 34 are formed. In this case, the second type electrode connection layer 35 may be spaced apart from the branch electrodes of the second type lower electrode 32 to have a plurality of bar shapes.

The electrode connection layers 33 and 35 and the heat sink connection layer 34 may be a mixed layer of an electrically conductive material and a thermally conductive material. As an example, any one of the electrode connection layers 33 and 35 and the heat sink connection layer 34 Cr, Ni, or Ti, and any of Au, Al, Cu, Mo, W, Ag, Sn, or Pd It may be one mixed layer. Materials of the electrode connection layers 33 and 35 and the heat sink connection layer 34 may be the same or different.

The first and second electrode connection layers 33 and 35 and the heat sink connection layer 34 may be formed by disposing a mask in a region where the photoresist pattern 29 is formed and depositing the mask. The deposition may be formed using sputtering, electron beam deposition, thermal deposition, pulsed laser deposition or laser molecular beam deposition.

2G and 3G, the photoresist pattern 29 and the adhesive layer 30 formed on the upper surface of the photoresist pattern 29 are removed.

As a result, electrode connection layers 33 and 35 fixed by the adhesive layer 30 may be positioned on the first type semiconductor layer 22 and the reflective layer 28, respectively, and on the reflective layer 28. The radiator connection layer 34 spaced apart from the second type electrode connection layer 35 may be located. In this case, the heat dissipation connection layer 34 may have a plurality of rod shapes.

2H and 3H, the substrate 10, the first type semiconductor layer 22, and the reflective layer 28 exposed between the electrode connection layers 33 and 35 and the heat sink connection layer 34. The lower insulating film 36 is formed on it. The lower insulating layer 48 may electrically insulate the first and second type semiconductor layers 22 and 26 from each other. The lower insulating layer 36 may be formed using an electrically insulating inorganic or organic material.

The lower insulating layer 36 may contain a wavelength change material. The wavelength conversion material may contain red, green, and blue wavelength conversion materials when the light emitting structure S generates ultraviolet light, and yellow wavelength conversion material when the light emitting structure S generates blue light. It may contain. Accordingly, the LED package of the final structure may emit white light.

The wavelength conversion material may include a translucent curable resin and a fluorescent material. The translucent curable resin may be a silicone resin, an epoxy resin, an acrylic resin, a urethane resin, or a photoresist. The phosphor may include a phosphor, a pigment or a dye. Specifically, the blue phosphor is Sr (PO) Cl: Eu, SrMgSiO: Eu, BaMgSiO: Eu, BaMgAlO: Eu, SrPO: Eu, SrSiAlON: Eu or the like, or a blue wire (Fe ₄ [Fe (CN) ₆ ] ₃ ), And a pigment such as cobalt blue (CoO-Al ₂ O ₃ ).

The green phosphor is BaSiO: Eu, SrSiO: Eu, SrAlO: Eu, SrAlO: Eu, SrGaS: Eu, SrSiAlON: Eu, (Ca, Sr, Ba) SiNO: Eu, YSiON: Tb, YSiON: Tb, GdSiON: Phosphor of Tn or chromium oxide (Cr ₂ O ₃ ), chromium hydroxide (Cr ₂ O (OH) ₄ ), basic copper acetate (Cu (C ₂ H ₃ O ₂ ) -2Cu (OH) ₂ ), cobalt green ( It may be a pigment such as Cr ₂ O ₃ -Al ₂ O ₃ -CoO).

The red phosphor may be a sulfide-based, nitride-based phosphor, or a pigment such as iron oxide (Fe ₂ O ₃ ), lead tetraoxide (Pb ₃ O ₄ ), mercury sulfide (HgS), or the like. Specifically, the sulfide phosphor may be SrS: Eu or CaS: Eu, and the nitride phosphor is SrSiN: Eu, CaSiN: Eu, CaAlSiN, (Ca, Sr, Ba) SiN: Eu, LaSiN: Eu or Sr -α-SiAlON.

The yellow fluorescent substance may be a pigment such as YAG-based (yttrium aluminum garnet), silicate-based phosphor or lead chromate (PbCrO ₄ ), zinc chromate (ZnCrO ₄ ), sulfide-cadmium-zinc sulfide (CdS-ZnS), or the like. Specifically, the YAG-based phosphor may be YAG: Ce, TbYAG: Ce, GdYAG: Ce or GdTbYAG: Ce, and the silicate-based phosphor may be methyl silicate, ethyl silicate, magnesium aluminum silicate, or aluminum silicate.

The insulating film 36 may be formed using sputtering, electron beam deposition, thermal deposition, pulsed laser deposition, laser molecular beam deposition, spray coating, dip coating, blade coating, or spin coating.

The lower insulating layer 36 may not be totally reflected on the reflective layer 28 to convert light that is leaked or emitted into the lower portion into other wavelength light.

2I and 3I, an upper insulating film 48 may be formed on the lower insulating film 36. The upper insulating layer 48 may contain a wavelength conversion material. The wavelength conversion material may be the same as the wavelength conversion material contained in the lower insulating layer 36 described above. The upper insulating film 48 may be formed using a photolithography method and a wet coating method.

2J and 3J, the first and second electrode connection layers 33 and 35 and the radiator connection layer 34 may be formed on the first and second type electrode connection layers 33 and 35, respectively, outside the region where the lower insulating layer 48 is formed. The second type upper electrodes 42 and 46 and the radiator layer 44 are formed, and the upper surface is planarized to form the upper insulating layer 28, the first and second type electrode connection layers 33 and 35, and the radiator. The upper surface level of the connection layer 34 may be formed to be the same.

The upper electrodes 42 and 46 may include a thermally conductive material and an electrically conductive material. As an example, the upper electrodes 42 and 46 may be a mixed layer of any one of Cr, Ni, or Ti, and any one of Au, Al, Cu, Mo, W, Ag, Sn, or Pd.

The heat sink layer 44 may include a thermally conductive material and an electrically conductive material. As an example, the heat sink layer 44 may be any one of Cr, Ni, or Ti, a single layer of Al, Au, Cu, Mo, W, Ag, Sn, or Pd, or a mixed layer thereof.

In this case, an electrically conductive material wet to a shoulder may be formed on the surfaces of the upper electrodes 42 and 46 and the heat sink layer 44. The electrically conductive material wet well to the shoulder may be SnBi, PbSn, SnAgCu, SnAgCuBi, AuSn, Sn, or In.

The radiator layer 44 may be thermally connected to the light emitting structures S by the radiator connection layer 34 to receive heat generated from the light emitting structures S. Accordingly, heat generated in the light emitting structures S may be quickly released to the outside.

The upper electrodes 42 and 46 and the heat sink layer 44 may be formed using a vacuum deposition method or a plating method.

2K and 3K, wavelength converting columns 52 penetrating the edges of the insulating layers 36 and 48 and the substrate 10 are formed.

The wavelength conversion pillar 52 may be formed by forming a plurality of through holes penetrating through the insulating layers 36 and 48 and the edge of the substrate 10, and introducing a liquid wavelength conversion material into the through holes. have. In this case, the liquid wavelength converting material may be filled in the through holes by capillary action.

The through holes may be formed using a laser drill or an etching process. The wavelength conversion pillar 52 may be formed using the same material as the wavelength conversion material contained in the insulating layers 36 and 48 described above.

2L and 3L, a wavelength conversion film 54 is formed on the bottom surface of the substrate 10. The wavelength conversion film 54 may be formed using a wet coating process. The wavelength conversion film 54 may be formed using the same material as the above-described wavelength conversion column 52.

The light emitting diode manufactured as described above may be flipped and connected to a printed circuit board (PCB) or bonding pads on the substrate. In this case, the bonding pads may be electrically connected to the upper electrodes 42 and 46 and the heat sink layer 44 of the unit light emitting diode.

As described above, the light emitting diode package according to the present invention includes a heat sink layer in direct contact with the first type semiconductor layer or the second type semiconductor layer, thereby rapidly dissipating heat generated from the light emitting structure to the outside. Problems such as shortening of life due to deterioration of reliability due to heat generation can be solved.

In addition, since the second type lower electrode in direct contact with the second type semiconductor layer has a branched shape, the current flows smoothly, thereby improving luminous efficiency.

In addition, since the wavelength conversion pillar located on the side of the light emitting structure and the wavelength conversion film located under the light emitting structure can be manufactured through a fab process, the light emitting diode manufacturing time can be reduced and mass production can be possible.

In addition, since the substrate 10 is used as a frame that is a skeleton of the package and all processes can be performed in the substrate or wafer state, the wafer level LED package can be implemented. As a result, manufacturing cost can be reduced.

4A to 4I are cross-sectional views illustrating a method of manufacturing a light emitting diode package according to another exemplary embodiment of the present invention, and FIGS. 5A to 5I are plan views illustrating upper surfaces of FIGS. 4A to 4I, respectively. In this case, the cross-sectional views of FIGS. 4A to 4I correspond to cross-sections taken along the cutting line II-II ′ of FIGS. 5A to 5I. Except for the following description, it is the same as the LED package described with reference to FIGS. 2A to 2L and FIGS. 3A to 3L.

4A and 5A, the first type semiconductor layer 22, the active layer 24, the second type semiconductor layer 26, and the reflective layer 28 that are sequentially disposed on the substrate 10 are patterned to form the substrate. An edge portion of the upper surface of 10 is exposed, and a portion of the reflective layer 28, the second type semiconductor layer and the reflective layer 28 is patterned, so that at least a portion of the upper surface of the first type semiconductor layer 22 is removed. May be exposed.

In this case, the active layer 24, the second type semiconductor layer 26, and the reflective layer 28 may be patterned to have a branch shape. In other words, the branch shape includes a main part positioned at the center of the upper surface of the first type semiconductor layer 22 and a plurality of branch parts extending from the main part to both edges of the second type semiconductor layer 22. It can be provided.

4B and 5B, a lower electrode 31 having a lower level than the upper surface level of the first type semiconductor layer 22 is formed on the exposed first type semiconductor layer 22. The lower electrode 31 may have a branch shape.

In other words, the lower electrode 31 is formed from the main part electrodes positioned on both edges of the first type semiconductor layer 22 and the active part 24 and the second type semiconductor layer from each of the main part electrodes. A plurality of branch electrodes extending between the branches of the 26 and the reflective layer 28 may be provided. In this case, the lower electrode 31 is formed at a level lower than the upper surface level of the first type semiconductor layer 22 to be spaced apart from the active layer 24, the second type semiconductor layer 26, and the reflective layer 28. Can be.

As described above, when the lower electrodes 31 and 32 have a branched shape, it helps to spread current, thereby improving luminous efficiency. In addition, when the first type semiconductor layer 22 is an n-type semiconductor layer, it is possible to improve the current flow characteristics of the n-type semiconductor layer having poor current flow characteristics. Accordingly, the luminous efficiency of the light emitting diode can be improved.

4C and 5C, regions exposed to the main electrode of the lower electrode 31 and the branch electrodes of the lower electrode 31 of the reflective layer 28 of the reflective layer 28 are exposed. The photoresist pattern 29 can be formed to be exposed.

4D and 5D, an adhesive layer 30 is formed on regions exposed by the photoresist pattern 29, and the first and second type lower electrodes on the adhesive layer 30 are formed. 31 and 32, and first and second electrode connection layers 33 and 35 and a heat sink connection layer 34 connected to the reflector layer 28, respectively.

4E and 5E, the photoresist pattern 29 and the adhesive layer 30 formed on the photoresist pattern 29 are removed.

As a result, an electrode connection layer 33 fixed by the adhesive layer 30 may be positioned on the first type semiconductor layer 22 and the reflective layer 28, respectively, and on the second type semiconductor layer 26. The heat dissipation connection layer 34 spaced apart from the second type electrode connection layer 35 may be located.

4F and 5F, the substrate 10 exposed through the electrode connection layers 33 and 35 and the heat sink connection layer 34, the first type lower electrode 31, and the second type lower part. The lower insulating film 36 is formed on the electrode 32.

Referring to FIGS. 4G and 5G, an upper insulating film 48 is formed on the lower insulating film 36 in an area except for the region in which the electrode connection layers 33 and 35 and the heat sink connection layer 34 are disposed. can do. In this case, the upper insulating layer 48 may be formed to be exposed to the peripheral region of the heat dissipation connection layer 34.

Referring to FIGS. 4H and 5H, the first and second electrode connection layers 33 and 35 and the heat dissipation connection layer 34 including the peripheral area, other than the region where the upper insulating film 48 is formed, are disposed on the radiator connection layer 34. The first and second type upper electrodes 42 and 46 and the heat dissipation layer 44 may be formed on the substrates.

4I and 5I, the wavelength conversion pillars 52 penetrating the edges of the insulating layers 36 and 48 and the substrate 10 are formed, and the wavelength conversion is performed on the lower surface of the substrate 10. A film 54 is formed. The light emitting diode package manufactured as described above may be flipped to be electrically connected to a printed circuit board (PCB) or bonding pads on the substrate. In this case, the heat dissipating layer 44 may have a heat dissipation characteristic and also serve as an electrode.

6A to 6D are plan views illustrating structures of the upper electrodes and the heat sink layers according to another embodiment of the present invention. In this case, each of the electrode connecting layers / lower electrodes and the heat dissipating layer disposed under the upper electrodes and the heat dissipating layer may have a structure and a shape corresponding to those of the upper electrodes and the heat dissipating layer. Can be.

6A to 6D, the first upper electrode 42 and the second type upper electrode 46 may be disposed opposite to both sides with the heat dissipating layer 44 interposed therebetween. In this case, the first upper electrode 42 and the second type upper electrode 46 may be disposed in a horizontal direction with the heat sink layer 44 (FIG. 6A) or in a diagonal direction (FIG. 6B). In this case, each of the first upper electrode 42 and the second type upper electrode 46 may be composed of a single electrode or a plurality of electrode structures 42a, 42b, 46a, and 46b.

The heat sink layer 44 may be disposed in contact with the first upper electrode 42 (FIG. 6C) or may be disposed in contact with the second type upper electrode 46 (FIG. 6D).

As mentioned above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes may be made by those skilled in the art within the spirit and scope of the present invention. You can change it.

2A to 2L are cross-sectional views illustrating a method of manufacturing a light emitting diode package according to an embodiment of the present invention.

3A to 3L are plan views illustrating the top surface of FIGS. 2A to 2L, respectively.

4A to 4I are cross-sectional views illustrating a method of manufacturing a light emitting diode package according to another embodiment of the present invention.

5A through 5I are plan views illustrating the top surface of FIGS. 4A through 4I, respectively.

6A to 6D are plan views illustrating structures of the upper electrodes and the heat sink layers according to another embodiment of the present invention.

Claims

A first type semiconductor layer disposed on an upper surface of the substrate and exposing an edge portion of the upper surface of the substrate, and disposed on the first type semiconductor layer to expose at least a portion of the upper surface of the first type semiconductor layer A light emitting structure having a second type semiconductor layer;

A second type electrode disposed on the first type semiconductor layer and a second type electrode disposed on the second type semiconductor layer and having an upper surface at the same level as an upper surface of the first type electrode;

A heat sink layer disposed on the second type semiconductor layer and having a top surface at the same level as the top surface of the electrodes; And

And an insulating film disposed on the substrate except for the first type electrode, the second type electrode, and the heat sink layer, and having an upper surface having the same level as a top surface of the electrodes and the heat sink layer.

The method of claim 1,

The first type electrode includes a first type upper electrode and a first type lower electrode,

The first type lower electrode may include main part electrodes positioned on both edges of the first type semiconductor layer and a plurality of branches extending from each of the main part electrodes to a central portion of the upper surface of the first type semiconductor layer. A light emitting diode package having secondary electrodes.

The method of claim 2,

The second type semiconductor layer is spaced apart from the first type electrode and is located between the main part semiconductors and the branched electrodes of the first type lower electrode from the main part semiconductors positioned in the center portion of the first type semiconductor layer. A light emitting diode package having a plurality of branched semiconductors extending.

The method of claim 2,

And a first type electrode connector layer disposed between the first type upper electrode and the main electrode of the first type lower electrode.

5. The method of claim 4,

The first type electrode connector layer is a mixed layer of any one of Cr, Ni or Ti, and any one of Au, Al, Cu, Mo, W, Ag, Sn, or Pd.

The method of claim 1,

The second type electrode includes a second type upper electrode and a second type lower electrode,

The second type lower electrode includes a main part electrode positioned on one side edge of the second type semiconductor layer and a plurality of branch electrodes extending from the main part electrode to a central portion of the upper surface of the second type semiconductor layer. LED package.

The method of claim 6,

And a second type electrode connector layer disposed between the second type upper electrode and the main electrode of the second type lower electrode.

The method of claim 7, wherein

The second type electrode connector layer is spaced apart from the plurality of branch electrodes, and has a plurality of bar-shaped light emitting diode package.

The method of claim 8,

The second type electrode connector layer is a mixed layer of any one of Cr, Ni or Ti, and any one of Au, Al, Cu, Mo, W, Ag, Sn, or Pd.

The method of claim 1,

The light emitting diode package further comprising a heat sink connection layer disposed between the second type semiconductor layer and the heat sink layer.

The method of claim 10,

The radiator connection layer is a light emitting diode package of any one of Cr, Ni or Ti, and a mixed layer of any one of Au, Al, Cu, Mo, W, Ag, Sn or Pd.

The method of claim 1,

A wavelength conversion pillar disposed in the plurality of through holes penetrating the edge portion of the insulating film and the substrate; And

The light emitting diode package further comprising a wavelength conversion film disposed on the lower surface of the substrate.

The method of claim 12,

The insulating film is a light emitting diode package containing a wavelength conversion material.

The method of claim 1,

A light emitting diode package further comprising a reflective layer disposed between the second type semiconductor layer and the heat sink layer.

The method of claim 14,

The reflective layer is an Ag layer or Al layer light emitting diode package.

The method of claim 14,

A light emitting diode package further comprising a transparent conductive film disposed between the second type semiconductor layer and the reflective layer.

The method of claim 16,

The transparent conductive film is a light emitting diode package containing ITO, IZO or AZO.