KR101068863B1 - Vertical semiconductor light emitting device and manufacturing method of the same - Google Patents

Abstract

The present invention relates to a vertical structure semiconductor light emitting device and a method of manufacturing the same, and an aspect of the present invention provides a light emitting device comprising a conductive substrate, a p-type semiconductor layer, an active layer and an n-type semiconductor layer sequentially stacked on the conductive substrate. And an n-type electrode formed on an upper surface of the n-type semiconductor layer, wherein the n-type semiconductor layer is formed of a heterogeneous material therein, and induces a current flowing between the n-type electrode and the conductive substrate in a lateral direction. Provided is a vertical structure semiconductor light emitting device comprising a current blocking region.

According to the present invention, a vertical structure semiconductor light emitting device having improved luminous efficiency and electrostatic breakdown voltage can be obtained by effectively spreading a current between the n-side and p-side electrodes. Furthermore, according to the present invention, a method of manufacturing a vertical semiconductor light emitting device capable of minimizing damage of a semiconductor layer by forming a current blocking region can be obtained.

Light emitting device, LED, vertical structure, current spreading, current spreading, current blocking

Description

Vertical semiconductor light emitting device and manufacturing method thereof

A vertical structure semiconductor light emitting device and a method of manufacturing the same. More particularly, the vertical structure semiconductor light emitting device having improved luminous efficiency and electrostatic withstand voltage by effectively spreading a current between the n-side and p-side electrodes, and a manufacturing method thereof. It is about.

BACKGROUND A light emitting diode (LED) is a semiconductor device capable of generating light of various colors based on recombination of electrons and holes at a junction portion of a p and n type semiconductor when current is applied thereto. These LEDs have a number of advantages over filament based light emitting devices, such as long life, low power, excellent initial driving characteristics, high vibration resistance, and high tolerance for repetitive power interruptions. In recent years, group III nitride semiconductors capable of emitting light in a blue short wavelength region have been in the spotlight.

The nitride single crystal constituting the light emitting device using the group III nitride semiconductor is generally formed on a specific single crystal growth substrate, such as a sapphire or SiC substrate. However, in the case of using an insulating substrate such as sapphire, the arrangement of electrodes is greatly limited. That is, in the conventional nitride semiconductor light emitting device, since the electrodes are generally arranged in the horizontal direction, the current flow becomes narrow. Due to such a narrow current flow, the forward voltage Vf of the light emitting device increases, resulting in a decrease in current efficiency, and also a problem of being vulnerable to electrostatic discharge.

In order to solve the above problem, a semiconductor light emitting device having a vertical structure is required, and in this case, electrodes are formed on upper and lower surfaces of the vertical semiconductor light emitting device.

1 is a cross-sectional view showing a vertical semiconductor light emitting device according to the prior art.

Referring to FIG. 1, a general vertical structure semiconductor light emitting device 10 includes an n-type semiconductor layer 11, an active layer 12, a p-type semiconductor layer 13, a reflective metal layer 14, a conductive substrate 15, and n. The side electrode 16 is provided, and the conductive substrate 15 functions as a p-side electrode. Although the vertical semiconductor light emitting device 10 has improved narrow current flow compared to the above-described horizontal structure, the n-side electrode 16 is still shown as indicated by an arrow (as opposed to the current direction by the flow of electrons). The current tends to concentrate in the direction immediately below.

Therefore, in the art, a method for spreading current in a direction perpendicular to the current direction is required even in a vertical structure semiconductor light emitting device.

The present invention is to solve the above problems, an object of the present invention to improve the luminous efficiency and electrostatic breakdown voltage by effectively spreading the current between the n-side and p-side electrode and a manufacturing method of the vertical structure To provide.

In order to achieve the above object, one aspect of the present invention,

A light emitting structure including a conductive substrate, a p-type semiconductor layer, an active layer, and an n-type semiconductor layer sequentially stacked on the conductive substrate, and an n-type electrode formed on an upper surface of the n-type semiconductor layer, wherein the n-type semiconductor layer Is formed of a heterogeneous material therein, and has a current blocking region for guiding a current flowing between the n-type electrode and the conductive substrate in a lateral direction.

The current interruption region employed in the present invention includes particles having elements of relatively small size, for example, elements selected from the group consisting of H, He, Li, Be, B, C, N, O, F and Ne. It is desirable to.

In addition, in order to increase the current dispersion effect, the current blocking region is preferably formed in a region through which a virtual straight line extending from the center of the lower surface of the n-type electrode passes below. In this case, the n-type electrode is more preferably formed in the central region of the upper surface of the n-type semiconductor layer. On the other hand, it may further include a highly reflective ohmic contact layer formed between the p-type semiconductor layer and the conductive substrate.

On the other hand, another aspect of the present invention,

Providing a substrate for semiconductor single crystal growth, sequentially growing an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the semiconductor single crystal growth substrate to form a light emitting structure on the p-type semiconductor layer Forming a conductive substrate, removing the semiconductor single crystal growth substrate to expose the n-type semiconductor layer to the outside, implanting particles into the n-type semiconductor layer to form a current blocking region, and It provides a method for manufacturing a vertical semiconductor light emitting device comprising forming an n-type electrode on the exposed surface of the n-type semiconductor layer.

In this case, the forming of the current blocking region is preferably performed by injecting particles in an ion state into the n-type semiconductor layer. In addition, the forming of the current blocking region may be performed by injecting particles through the exposed surface of the n-type semiconductor layer. In addition, the particles injected into the n-type semiconductor layer is preferably a particle containing an element selected from the group consisting of H, He, Li, Be, B, C, N, O, F and Ne.

Preferably, after the forming of the current blocking region, the method may further include heat-treating the region damaged by the injected particles in the n-type semiconductor layer. In this case, the heat treatment of the damaged region of the n-type semiconductor layer is preferably performed at a temperature condition of 200 ~ 1000 ℃, more preferably 400 ~ 800 ℃. In a process that can be preferably employed, the heat treatment of the damaged region of the n-type semiconductor layer may be performed by irradiating a laser to the damaged region, and in this case, the emission wavelength of the laser is preferably 400 nm or less.

As described above, according to the present invention, a vertical structure semiconductor light emitting device having improved luminous efficiency and electrostatic breakdown voltage can be obtained by effectively spreading a current between the n-side and p-side electrodes. Furthermore, according to the present invention, a method of manufacturing a vertical semiconductor light emitting device capable of minimizing damage of a semiconductor layer by forming a current blocking region can be obtained.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. In addition, the embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings are the same elements.

2 is a cross-sectional view showing a vertical semiconductor light emitting device according to one embodiment of the present invention. Referring to FIG. 2, the vertical semiconductor light emitting device 100 according to the present embodiment includes a highly reflective ohmic contact layer 104, a p-type semiconductor layer 103, and an active layer sequentially formed on a conductive substrate 105 and an upper surface thereof. 102 and n-type semiconductor layer 101 are provided. In addition, a current blocking region 107 and an n-type electrode 106 are formed in the inner and upper surfaces of the n-type semiconductor layer 101, respectively.

The conductive substrate 105 serves as a support for supporting the light emitting structure with the p-side electrode, and may include a material selected from the group consisting of Si, Cu, Ni, Au, W, and Ti. In particular, when the substrate provided for single crystal growth is removed by a laser lift-off process or the like, the light emitting structure having a relatively thin thickness can be more easily handled by the conductive support substrate 105. Although the highly reflective ohmic contact layer 104 is not a necessary component in the present invention, the n-type nitride semiconductor emits light emitted from the active layer 102 together with an ohmic contact function with the p-type nitride semiconductor layer 103. A function of reflecting toward the layer 101 may be performed to contribute to luminous efficiency. To this end, the highly reflective ohmic contact layer 104 preferably has a reflectance of 70% or more, for example, a material including Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, or the like. Is made of. In addition, although not separately illustrated, the highly reflective ohmic contact layer 104 may have a structure having two or more layers to improve reflection efficiency. Specific examples thereof include Ni / Ag, Zn / Ag, Ni / Al, and Zn /. Al, Pd / Ag, Pd / Al, Ir / Ag. Ir / Au, Pt / Ag, Pt / Al, Ni / Ag / Pt, etc. are mentioned.

The n-type and p-type semiconductor layers 101 and 103 and the active layer 102 constituting the light emitting structure may be formed of a nitride semiconductor, although not limited thereto. In the present specification, the "light emitting structure" refers to a structure formed by sequentially stacking the n-type semiconductor layer 101, the active layer 102, and the p-type semiconductor layer 103. The n-type and p-type semiconductor layers 101 and 103 may have an Al _x In _y Ga _(1-xy) N composition formula, where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and 0 ≦ x + y ≦ 1. N-type impurities and p-type impurities may be formed of a semiconductor material doped, and typically, GaN, AlGaN, InGaN. In addition, Si, Ge, Se, Te or C may be used as the n-type impurity, and the p-type impurity may be representative of Mg, Zn or Be. The active layer 102 is a layer in which light is generated by recombination of electrons and holes. In the present embodiment, the active layer 102 includes a nitride semiconductor layer having a single or multiple quantum well structure.

As shown in FIG. 2, the current blocking region 107 inserted into the n-type semiconductor layer 101 distributes the current flowing between the n-type electrode 106 and the conductive substrate 105 in the lateral direction. It is possible to alleviate the current concentration phenomenon and the electrostatic discharge, which has been pointed out in the prior art. In this case, the current blocking region 107 is injected into the n-type semiconductor layer 101 in the ion state of particles such as H, He, Li, Be, B, C, N, O, F, Ne from the outside It may be formed, more details thereof will be described later.

On the other hand, in order to smoothly distribute the current in the lateral direction, the position where the current blocking region 107 and the n-type electrode 106 are formed is, for example, the center region of the n-type semiconductor layer 101 or the like. It is preferable to almost match. That is, the current blocking region 107 is disposed so as to be located in a region through which a virtual straight line from the center of the lower surface of the n-type electrode 106-the surface in contact with the n-type semiconductor layer 101-passes. In this case, the current dissipation effect can be more pronounced.

Hereinafter, a method of manufacturing the vertical structure semiconductor light emitting device described above will be described. 3A to 3F are cross-sectional views of processes illustrating a method of manufacturing a vertical semiconductor light emitting device according to one embodiment of the present invention.

First, as shown in FIG. 3A, the sapphire substrate 200 is provided and the n-type nitride semiconductor layer 101, the active layer 102, and the p-type nitride semiconductor layer 103 are sequentially grown thereon. In this case, the n-type and p-type nitride semiconductor layers 101 and 103 and the active layer 102 may use a known process for growing the nitride semiconductor layer, for example, organometallic vapor deposition (MOCVD), molecular beam growth. This includes the Act (MBE) and Hybrid Vapor Deposition (HVPE). Although not shown separately, the nitride buffer layer may be preferentially grown before the n-type nitride semiconductor layer 101 is grown.

The sapphire substrate 200 is a crystal having hexagonal-Rhombo R3c symmetry and has a lattice constant of 13.001 Å in the c-axis direction and 4.765 Å in the a-axis direction, and C (0001). ) Surface, A (1120) surface, R (1102) surface, and the like. In this case, the C surface of the sapphire substrate 200 is relatively easy to grow a nitride thin film, and is mainly used as a nitride growth substrate because it is stable at high temperatures. However, although the nitride semiconductor is used in the present embodiment, the present invention is not limited thereto, and other kinds of semiconductor materials known in the art may be used. Further, SiC, MgAl ₂ O ₄ , MgO, LiAlO ₂ , LiGaO ₂ instead of the sapphire substrate 200 provided as a nitride semiconductor growth substrate. The substrate which consists of etc. can also be used.

Next, as shown in FIG. 3B, a highly reflective ohmic contact layer 104 and a conductive substrate 105 are formed on the p-type nitride semiconductor layer 103. Various known methods may be used to form the highly reflective ohmic contact layer 104, and examples thereof include a sputtering process and a deposition process. The conductive substrate 105 formed after the formation of the highly reflective ohmic contact layer 104 is an element included in the final light emitting device, and serves as a support for supporting the light emitting structure together with the p-side electrode. In this case, the conductive substrate 105 may include a material selected from the group consisting of Si, Cu, Ni, Au, W, and Ti, and according to the selected material, the highly reflective ohmic contact layer by a plating method or the like. It may be formed directly on the 104, or may be bonded to the highly reflective ohmic contact layer 104 via a eutectic metal layer therebetween.

Next, as shown in FIG. 3C (reversing the structure of FIG. 3B), the sapphire substrate 200 is removed to expose one surface of the n-type nitride semiconductor layer 101 to the outside. In this step, typically, a laser lift off process (LLO) may be used, but is not limited thereto, and may be separated through other mechanical or chemical processes.

Next, as illustrated in FIG. 3D, particles in an ion state are implanted into the n-type semiconductor layer 101 through the exposed surface of the n-type semiconductor layer 101. In this case, the pattern P may be formed on the exposed surface of the n-type semiconductor layer 101 so that the particles are injected into a desired region. As described above, in the present embodiment, the particles are injected from the outside so that the current blocking region is inserted into the n-type semiconductor layer 101. In this case, if the particles to be injected are in an ionic state, the particles may be accelerated with appropriate energy and inserted into the n-type semiconductor layer 101. By the implantation step for forming the current blocking region, particles enter the n-type semiconductor layer 101 and the n-type semiconductor layer 101 located in the path is damaged by crystals. FIG. 3E shows the damage region D of the n-type semiconductor layer 101 due to the injection of accelerated particles.

Since the damaged area D may adversely affect the luminous efficiency, it is necessary to remove it. In particular, when the size of the injected particles is large, the damage is so difficult to recover, the particles injected in the ionic state are relatively relatively like H, He, Li, Be, B, C, N, O, F, Ne, etc. It is preferable to select one with a small atomic size. In this case, the particles that can be most preferably employed may be referred to as deuterum ( ² H).

Subsequently, after the particle is injected, the damaged area D is removed by a method such as heat treatment. In this case, if the heat treatment temperature, method, and the like are properly adjusted, the damaged region D can be removed while maintaining the current blocking region as it is. 3F shows a state in which the damaged region is removed after the heat treatment, and details to be considered for setting the heat treatment temperature will be described in detail with reference to FIGS. 4 and 5.

First, FIGS. 4A and 4B are graphs showing a change in sheet resistance according to the heat treatment (annealing) temperature of a region damaged by the injection of particles. In this case, FIG. 4A shows that deuterium is injected into the GaN layer, while in FIG. 4B, iron (Fe) is injected into the GaN layer. Referring to FIG. 4A, when the heat treatment temperature is about 200 ° C. or more, the damaged area is gradually recovered by the injection of deuterium, and at about 400 ° C. or more, the state before the damage is almost recovered. However, as shown in FIG. 4A, this tendency is prominent in the n-type semiconductor layer, and when the p-type semiconductor layer is damaged, the desired recovery performance is not exhibited. In view of these results, in the present embodiment, the current blocking layer is inserted into the n-type semiconductor layer instead of the p-type semiconductor layer.

On the other hand, Figure 4b is a case where the injection particles are iron, unlike the graph of Figure 4a, showed an absolute sheet resistance value, instead, the reference value before the damage is presented divided by n-type and p-type. Referring to FIG. 4B, recovery of the damaged region may be initiated only by heat treatment of about 600 ° C. or higher. In particular, in the case of the n-type semiconductor layer, even if the heat treatment is performed at 800 ° C. or higher, the recovery may not be performed. This can be understood that when the iron is injected, damage of the damaged area is more severe than deuterium.

Next, FIG. 5 is a Secondary Ion Mass Spectrometry (SIMS) graph showing the distribution of deuterium according to the thickness by heat-treating the n-type semiconductor layer in the state of injecting deuterium. Here, the reference line of about 10 ¹⁹ cm ^-3 is the atomic density of the n-type semiconductor layer, and the thickness of the horizontal axis corresponds to the thickness from the n-type semiconductor layer surface. Referring to FIG. 5, it can be seen that there is no large change up to about 800 ° C., but the density (deuterium particle density) of the current blocking region is lowered at a heat treatment temperature of about 900 ° C. or more. It can be understood that the deuterium particles are diffused into the surrounding n-type semiconductor layer at about 900 ° C. or more.

Based on the results of FIGS. 4 and 5 discussed above, the range of the heat treatment temperature at which the damaged region of the n-type semiconductor layer is recovered by the particle injection and the temperature at which the density of the injected particles forming the current blocking region are diffused to decrease the density. It can be seen that the difference. Therefore, if the heat treatment temperature is properly selected, the damaged area can be recovered while maintaining the current blocking area. In consideration of this, the heat treatment temperature after the particle injection is preferably set in the range of about 200 ~ 1000 ℃. Furthermore, the heat treatment temperature range showing the most excellent effect may be about 400 ~ 800 ℃.

Meanwhile, as the heat treatment method, various heat treatment methods known in the art may be used. However, a laser can be used as a preferable method. In the case of using a laser, the damaged area can be locally heated, and the pattern P used for particle injection can be used as it is. In particular, since a laser having a wavelength of about 400 nm or less that is well absorbed by a nitride semiconductor or the like can be directly heat-treated only the damaged region, recovery is more easily possible.

After the heat treatment step described above, as shown in Figure 3g, the n-type electrode 106 is formed on the exposed surface of the n-type semiconductor layer 101 by a metal thin film deposition method such as PCVD, LPCVD, PECVD. In this case, if the n-type electrode 106 is formed in accordance with the position of the current blocking region 107, it can be more helpful to the current dispersion.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited only by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

1 is a cross-sectional view showing a vertical semiconductor light emitting device according to the prior art.

2 is a cross-sectional view showing a vertical semiconductor light emitting device according to one embodiment of the present invention.

3A to 3F are cross-sectional views of processes illustrating a method of manufacturing a vertical semiconductor light emitting device according to one embodiment of the present invention.

4A and 4B are graphs showing a change in sheet resistance according to the heat treatment (annealing) temperature of a region damaged by the injection of particles.

5 is a Secondary Ion Mass Spectrometry (SIMS) graph showing the distribution of deuterium according to the thickness by heat-treating the n-type semiconductor layer in the state of injecting deuterium.

<Description of the symbols for the main parts of the drawings>

101: n-type nitride semiconductor layer 102: active layer

103: p-type nitride semiconductor layer 104: highly reflective ohmic contact layer

105: conductive substrate 106: n-type electrode

107: current blocking region 200: sapphire substrate

Claims (14)

delete delete delete delete delete Providing a substrate for growing semiconductor single crystals; Sequentially forming an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the semiconductor single crystal growth substrate to form a light emitting structure; Forming a conductive substrate on the p-type semiconductor layer; Removing the semiconductor single crystal growth substrate to expose the n-type semiconductor layer to the outside; Forming a current blocking region by injecting particles into the n-type semiconductor layer; Heat-treating the region damaged by the implanted particles in the n-type semiconductor layer such that the current blocking region is located inside the n-type semiconductor layer; And Forming an n-type electrode on a portion of an exposed surface of the n-type semiconductor layer so as to overlap the current blocking region and at least a partial region in a stacking direction of the light emitting structure; Vertical structure semiconductor light emitting device manufacturing method comprising a. The method of claim 6, Forming the current blocking region, And implanting particles in an ion state into the n-type semiconductor layer. The method of claim 6, Forming the current blocking region, And injecting particles through the exposed surface of the n-type semiconductor layer. The method of claim 6, Particles injected into the n-type semiconductor layer is a vertical structure semiconductor light emitting device characterized in that the particles consisting of an element selected from the group consisting of H, He, Li, Be, B, C, N, O, F and Ne Way. delete The method of claim 6, The heat treatment of the damaged region of the n-type semiconductor layer is a vertical structure semiconductor light emitting device manufacturing method, characterized in that carried out at a temperature condition of 200 ~ 1000 ℃. The method of claim 11, The heat treatment of the damaged region of the n-type semiconductor layer is a vertical structure semiconductor light emitting device manufacturing method, characterized in that performed at a temperature condition of 400 ~ 800 ℃. The method of claim 6, And heat treating the damaged region of the n-type semiconductor layer by irradiating the damaged region with a laser. The method of claim 13, The emission wavelength of the laser is a manufacturing method of the vertical structure semiconductor light emitting device, characterized in that less than 400nm.

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