JP2013243202A - Manufacturing method of semiconductor light-emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor light-emitting device which has a high carrier concentration and low contact resistance with metal, in which diffusion of metal into a semiconductor is suppressed, and which is excellent in light-extraction efficiency and luminous efficiency.SOLUTION: A manufacturing method of a semiconductor light-emitting element, comprises: a process of growing on a semiconductor substrate, an n-type semiconductor layer, an active layer and a p-type conductor layer each of which has a composition (AlGa)InP, and a carbon-doped GaInP contact layer; a process of forming a dielectric layer having an opening, on the contact layer; a process of forming a metal electrode layer on the dielectric layer and the opening; a process of forming a first bonding metal layer on the metal electrode layer; a heat treatment process of forming an ohmic contact between the contact layer exposed from the opening and the metal electrode layer; and a process of bonding, by using a support medium in which a second boding metal layer is formed on a support substrate, the first and second bonding metal layers by thermocompression. A carrier concentration of the contact layer is 5×10cmor over and a temperature in the heat treatment process is 400°C or under.

Description

  The present invention relates to a method of manufacturing a semiconductor light emitting device formed by bonding a semiconductor layer grown on a growth substrate to a support substrate and then removing the growth substrate, and more particularly, an AlGaInP light emitting diode (LED: Light Emitting Diode). ) Manufacturing method.

  In order to increase the efficiency and brightness of light emitting diodes (LEDs), the semiconductor light emitting laminate grown on the growth substrate (or temporary substrate) is attached to a conductive support substrate (or permanent substrate) via a reflection mirror. Then, an LED (bonding structure or bonding structure) having a structure in which the growth substrate is removed is employed (for example, Patent Document 1 and Patent Document 2).

For example, in an AlGaInP-based LED, when an AlGaInP-based semiconductor stack is bonded to an opaque support substrate such as Si or Ge, a dielectric layer (for example, SiO ₂ layer) and an electrode metal layer are provided between the semiconductor stack and the bonding metal layer. Is provided to form a reflection mirror. Further, a part of the dielectric layer is removed to obtain electrical contact between the semiconductor laminate and the electrode metal layer.

  In order to improve the light extraction efficiency of the LED having such a structure, it is necessary to increase the area of the dielectric layer as much as possible. However, the contact area between the semiconductor and the metal is reduced accordingly, and the contact resistance is increased. On the other hand, in order to improve luminous efficiency, it is important to reduce the operating voltage by reducing the contact resistance between the semiconductor and the metal. However, if the contact area between the semiconductor and the metal is reduced, the contact resistance increases. There is. In order to reduce the contact resistance between the semiconductor and the metal, there is a method of increasing the carrier concentration of the semiconductor layer (contact layer) in contact with the metal. However, control of the carrier concentration, high concentration doping, dopant diffusion, growth inhibition, etc. (For example, patent document 3 and patent document 4).

JP 2009-4487 A JP 2010-50318 A JP 2003-243698 A JP 2007-42751 A

  The present invention has been made in view of the above-described points. The object of the present invention is to reduce the contact resistance with a metal at a high carrier concentration and suppress the diffusion of the metal into the semiconductor, and the light extraction efficiency and the light emission efficiency. An object of the present invention is to provide a method for manufacturing a semiconductor light emitting device excellent in the above.

Production method of the present invention, n-type semiconductor layer, each having a composition _{(Al y Ga 1-y)} x In 1-x P (0.4 ≦ x ≦ 0.6,0 ≦ y ≦ 1.0) on a semiconductor substrate, an active layer And growing a p-type semiconductor layer, and growing a carbon-doped Ga _1-z In _z P contact layer (0 ≦ z ≦ 0.1) on the p-type semiconductor layer;
Forming a dielectric layer on the contact layer having an opening through which the contact layer is exposed;
Forming a metal electrode layer on the dielectric layer and the opening; and
Forming a first bonding metal layer on the metal electrode layer;
Performing a heat treatment to form an ohmic contact between the contact layer exposed from the opening and the metal electrode layer;
Using a support in which a second bonding metal layer is formed on a support substrate, and bonding the first bonding metal layer and the second bonding metal layer by thermocompression bonding, and
The carrier concentration of the contact layer is 5 × 10 ¹⁹ cm ⁻³ or more, and the temperature of the heat treatment is 400 ° C. or less.

3 is a cross-sectional view schematically showing a light emitting device manufactured by the method of Example 1. FIG. 6 is a cross-sectional view schematically showing a method for manufacturing the light-emitting device of Example 1. FIG. 6 is a cross-sectional view schematically showing a method for manufacturing the light-emitting device of Example 1. FIG. It is a figure which shows the relationship between V / III ratio and carrier concentration. It is a figure which shows the relationship between growth temperature and carrier concentration. It is a figure which shows the contact resistance ((ohm) cm < ² >) with respect to heat processing temperature (alloying temperature). It is sectional drawing which shows typically the LED element of a comparative example. It is a figure which shows the change of the operating voltage Vd with respect to the drive current Id of the LED element sample of Example 1. FIG. It is a cross-sectional SEM image of the interface of a contact metal and a semiconductor when heat processing (alloying) temperature is 500 degreeC (a figure, left side) and 400 degreeC (a figure, right side). It is a figure which shows the depth direction profile by SIMS in case heat processing temperature is 500 degreeC and 400 degreeC.

  In the following, preferred embodiments of the present invention will be described, but these may be appropriately modified and combined. In the following description and the accompanying drawings, substantially the same or equivalent parts will be described with the same reference numerals.

  FIG. 1 is a cross-sectional view schematically showing a light emitting device 10 manufactured by the method of Example 1 of the present invention. The light emitting device 10 is an AlGaInP light emitting diode (LED) having a structure in which a semiconductor structure layer 11 and a support substrate 31 are bonded via a bonding layer 41.

  More specifically, the semiconductor structure layer (LED structure layer) 11 includes an n-type first semiconductor layer 12, a light emitting layer 14, a p-type second semiconductor layer 16, and a p-type contact layer 17. The semiconductor structure layer 11 is included.

A dielectric layer 20 made of a transparent insulator such as SiO ₂ or SiN is formed on the contact layer 17, and a metal electrode layer 21 is formed on the dielectric layer 20. A reflective layer that reflects light from the light emitting layer 14 is configured by the laminated structure of the dielectric layer 20 and the metal electrode layer 21. The dielectric layer 20 is provided with an opening, and the metal electrode layer 21 and the contact layer 17 are in electrical contact (contact) with the opening.

[Manufacturing Method of Light-Emitting Device 10]
The method for manufacturing the light emitting device 10 according to the first embodiment will be described in detail below by taking the case of an AlGaInP light emitting diode (LED) as an example. 2A to 2C and FIGS. 3A and 3B are cross-sectional views schematically showing a method for manufacturing the light-emitting device 10 of the first embodiment.

Crystal growth was performed using MOCVD (Metal-Organic Chemical Vapor Deposition) method to form the semiconductor structure layer 11. TMG (trimethylgallium), TMA (trimethylaluminum), and TMI (trimethylindium) were used as group III organometallic materials, and PH ₃ (phosphine) was used as group V materials. The n-type dopant was Si (silicon), SIH ₄ (silane) was used as the raw material, Mg (magnesium) was used as the p-type dopant, and Cp ₂ Mg (biscyclopentadienyl magnesium) was used as the raw material. The dopant of the p-type contact layer was carbon (C), and CBr4 (tetrabromocarbon) was used as the raw material. Hydrogen (H ₂ ) was used as a carrier gas, and growth was performed under a reduced pressure of 10 kPa (Pa: Pascal). The V / III ratio was 30 to 300, the growth temperature of the AlGaInP-based semiconductor layer was 680 ° C., and the growth temperature of the Mg-doped current diffusion layer was 750 ° C. Further, as the growth substrate 10A, an n-type GaAs substrate tilted by 15 ° from the (100) plane (off angle: 15 °) was used. Also,
More specifically, as shown in FIG. 2A, the semiconductor structure layer (LED structure layer) 11 was epitaxially grown on the (100) plane of the GaAs growth substrate 10A. Specifically, the n-type current diffusion layer 12A made of (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P with a thickness of 3 μm (micrometer) and Si-doped (carrier concentration 1 × 10 ¹⁸ cm ⁻³ ) has a thickness of An n-cladding layer 12B made of Al _0.5 In _0.5 P of _0.5 μm and Si-doped (carrier concentration 2 × 10 ¹⁷ cm ⁻³ ) was epitaxially grown in this order. The first semiconductor layer 12 is configured by the n-type current diffusion layer 12A and the n-clad layer 12B. On the first semiconductor layer _{12, (Al 0.1 Ga 0.9)} 0.5 In 0.5 P quantum well layers (thickness: 10 nm) and _{(Al 0.5 Ga 0.5) 0.5 In} 0.5 P barrier layer (thickness: 10 nm) is 20 cycles The active layer 14 made of the formed multiple quantum well (MQW) was grown. On the active layer 14, a p-cladding layer 16A (layer thickness: 1 μm) made of (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P with Mg doping (carrier concentration 3 × 10 ¹⁷ cm ⁻³ ), Mg doping (carrier concentration) A p-type current diffusion layer (layer thickness: 1 μm) 16B made of GaP of 2 × 10 ¹⁸ cm ⁻³ ) was grown. The second semiconductor layer 12 is configured by the p-cladding layer 16A and the p-type current diffusion layer 16B. Further, a p-contact layer 17 made of GaP doped with carbon (C) was grown on the p-type current diffusion layer 16B. The carrier concentration of the GaP contact layer 17 was 1 × 10 ^{19 to} 5 × 10 ²⁰ cm ⁻³ and the layer thickness was 5 to 100 nm.

  In the following description, the first semiconductor layer 12 includes an n-type current diffusion layer 12A and an n-cladding layer 12B, and the second semiconductor layer 12 includes a p-cladding layer 16A and a p-type current diffusion layer 16B. However, the first semiconductor layer 12 and / or the second semiconductor layer 12 may further include other semiconductor layers. For example, the semiconductor layer may include a carrier injection layer, a barrier layer for preventing carrier overflow, a contact layer for improving ohmic contact, a buffer layer, and the like. Alternatively, the first semiconductor layer 12 and / or the second semiconductor layer may be configured as a single layer.

Next, as shown in FIG. 2B, a dielectric layer (SiO ₂ ) was formed on the GaP contact layer 17 by sputtering. Next, patterning was performed by photolithography, and a part of the SiO ₂ film was removed by etching to form a dielectric layer 20 provided with an opening 20A. Thereafter, a metal electrode layer 21 made of contact metal (AuZn) was deposited by sputtering. The opening 20A of the dielectric layer 20 is filled by vapor deposition of the metal electrode layer 21, and electrical contact (contact) between the metal electrode layer 21 of the metal electrode layer 21 and the contact layer 17 in the opening 20A (that is, the contact portion). ) Is taken.

  Next, a TaN layer 22, a TiW layer 23, and a TaN layer 24 were sequentially formed on the metal electrode layer 21 as a barrier metal layer. Next, heat treatment (alloying treatment) was performed in a nitrogen atmosphere. The temperature conditions for alloying will be described in detail later. The contact area of the contact portion where the contact layer 17 and the electrode layer 21 contact is 5% of the element area, that is, the area occupied by the opening 20A is 5% of the total area of the dielectric layer 20 and the opening 20A. Next, a Ni layer 26 that functions as a solder absorption layer (Sn absorption layer) is formed on the TaN layer 24 by sputtering, and an Au layer 27 that functions as a wettability improving layer is formed on the Ni layer 26. It was. That is, the first bonding metal layer 28 is constituted by the metal layers 22 to 27 formed on the electrode layer 21. The formation of the metal layer of the electrode layer 21 and the first bonding metal layer 28 is not limited to the sputtering method, and for example, resistance heating vapor deposition, electron beam (EB) vapor deposition, or the like can be used as appropriate. With this process, the formation of the semiconductor light emitter 29 is completed.

Next, as shown in FIG. 2C, a support 30 for bonding to the semiconductor light emitting body 29 was formed. For example, Pt (platinum) layers 33 and 32 were formed by sputtering on the front and back surfaces of a support substrate 31 made of silicon (Si), for example. The support substrate (Si substrate) 31 is doped with, for example, boron 3 × 10 ¹⁸ cm ⁻³ or more. Next, a Ti layer 34, a Ni layer 35 functioning as a solder absorption layer (Sn absorption layer), an Au layer 36 functioning as a wettability improving layer, and an AuSn layer 37 as a solder layer are formed in this order on the Pt layer 33 by sputtering. Were sequentially formed. The solder absorption layer (Sn absorption layer) described above is not limited to Ni, and may be Pt or Pd (palladium), for example. That is, the second bonding metal layer 38 is formed by the metal layers 33 to 37 formed on the support substrate 31. The formation of these metal layers is not limited to sputtering, and for example, resistance heating vapor deposition, electron beam (EB) vapor deposition, or the like can be used as appropriate.

  Next, as shown in FIG. 3A, the outermost surface layer of the first bonding metal layer 28 of the semiconductor light emitting body 29 and the outermost surface of the second bonding metal layer 38 of the support 30. The AuSn layer 37, which is a layer, was placed in close contact with each other and thermocompression bonded in a nitrogen atmosphere. The thermocompression bonding conditions are, for example, a pressure of about 1 MPa (megapascal), a temperature of 320 ° C. to 370 ° C., and a pressure bonding time of about 10 minutes. Here, the temperature of thermocompression bonding is 400 ° C. or lower, and is preferably lower than the heat treatment temperature (alloying temperature described later) for obtaining ohmic contact. By this thermocompression bonding, the AuSn layer 37 is melted, and Au in the Au layer 27 and the Au layer 36 and Ni in the Ni layer 26 and the Ni layer 35 are dissolved in the melted AuSn layer 37. Further, Au and Sn in the Au layer 27, the Au layer 36, and the AuSn layer 37 are diffused and absorbed in the Ni layer (Sn absorption layer) 26 and the Ni layer (Sn absorption layer) 35. Furthermore, as shown in FIG. 3B, the molten AuSn layer 37 is solidified to form a bonding layer 40 made of AuSnNi. Next, the GaAs substrate 10A was removed by wet etching using a mixed solution of ammonia water and hydrogen peroxide water. The removal of the GaAs substrate 10A may be performed by dry etching, chemical mechanical polishing (CMP), mechanical grinding, or the like.

  By removing the GaAs substrate 10A, the surface of the first semiconductor layer 12, that is, the surface of the n-type current diffusion layer 12A is exposed. In order to improve the light extraction efficiency, an uneven light extraction structure 45 was formed on the surface of the n-type current diffusion layer 12A. The light extraction structure 45 can be formed by anisotropic wet etching of the n-type current diffusion layer 12A. Alternatively, the light extraction structure 45 can be formed by etching using a resist formed by photolithography, electron beam lithography, an electron beam (EB) drawing apparatus, nanoimprint, laser exposure, or the like as a mask pattern. Further, an n-electrode 43 was formed on a part of the surface of the n-type current diffusion layer 12A to form an LED device structure. Note that the Pt (platinum) layer 32 formed on the back surface of the support substrate 31 functions as a p-electrode.

[Doping of GaP layer]
As described above, CBr ₄ (tetrabromocarbon) was used as a material for doping carbon (C) into the contact layer 17 having a composition of GaP. For consideration doping carbon (C) to Cp2Mg of Mg material (biscyclopentadienyl magnesium as well as CBr ₄ are also solid at room temperature .GaP layer, it was grown GaP layer by changing the growth conditions.

Carbon (C) is a group IV element, and acts as a p-type impurity by substituting the group V site. First, growth was performed at a CBr ₄ supply rate of 10 μmol / min, the same growth temperature as the Mg-doped GaP current diffusion layer 16B (ie, 750 ° C.) and a V / III ratio of 100. Did not show. That is, it was found that p-type conductivity cannot be obtained under the same conditions as in the case of Mg doping. As described above, carbon (C) acts as a p-type impurity by substituting the group V site, so that the supply amount of phosphine as the group V raw material, that is, the V / III ratio is controlled to grow, The carrier concentration was examined. Specifically, the carrier concentration was examined by changing the V / III ratio while setting the supply amount of CBr ₄ to 10 μmol / min and the growth temperature of 685 ° C. The reason why the growth temperature is set lower than in the case of Mg doping is to improve the carbon uptake efficiency.

FIG. 4 shows the relationship between the V / III ratio and the carrier concentration. The V / III ratio was varied in the range of 2-25. In the drawings described below, En is an exponential notation, for example, 5E20 represents 5 × 10 ²⁰ . As the V / III ratio was decreased, the carrier concentration was increased. When the V / III ratio = 2, a carrier concentration of 1 × 10 ¹⁹ cm ⁻³ was obtained. However, it is preferable to further increase the carrier concentration in order to reduce the operating voltage.

Therefore, the growth temperature was examined with the V / III ratio = 2. The growth temperature was changed in the range of 550 to 685 ° C. FIG. 5 shows the relationship between the growth temperature and the carrier concentration. It has been found that the carrier concentration increases by reducing the growth temperature. Specifically, the carrier concentration of 5 × 10 ²⁰ cm ⁻³ can be obtained by lowering the growth temperature to 550 ° C. Further, if the growth temperature is lowered, GaP growth cannot be performed, so the growth temperature is preferably 550 ° C. or higher and 630 ° C. or lower. Further, it was found that when the V / III ratio is further lowered, the surface state (morphology) of the GaP layer is deteriorated, so that the V / III ratio is preferably 2 or more. When Mg or Zn is used, good crystals cannot be obtained with such a V / III ratio and growth temperature. According to this example, by reducing the growth temperature, 5 × 10 ¹⁹ cm ⁻³ is obtained even when the V / III ratio is 5. Therefore, it was found that when the growth temperature is in the range of 550 to 685 ° C. and the V / III ratio is in the range of 2 to 5, a carrier concentration of 5 × 10 ^{19 to} 5 × 10 ²⁰ cm ⁻³ can be obtained. .

[Production of LED structure and contact resistance]
Next, an LED structure was actually fabricated, and contact resistance was examined by changing the layer thickness and carrier concentration of the carbon-doped GaP contact layer 17. The growth temperature of the AlGaInP-based semiconductor layer, that is, the AlGaInP current diffusion layer 12A, the AlInP layer cladding layer 12B, the AlGaInP-based active layer 14 and the AlGaInP cladding layer 16A is 680 ° C., and the growth temperature of the Mg-doped GaP current diffusion layer 16B is 750. The epitaxial growth was performed by setting the growth temperature of the carbon-doped GaP contact layer 17 to 600 ° C.

The layer thickness of the carbon-doped GaP contact layer 17 was 50 nm, and the carrier concentration was 1 × 10 ^{19 to} 5 × 10 ²⁰ cm ⁻³ . AuZn was vapor-deposited on the sample contact layer 17 formed in this way by a vacuum vapor deposition method, and heat resistance (alloying) was performed to obtain ohmic contact, and the contact resistance was examined.

FIG. 6 shows the contact resistance (Ωcm ² ) with respect to the heat treatment temperature (alloying temperature). The case where the carrier concentration of the GaP contact layer 17 is 5 × 10 ¹⁹ and 1 × 10 ¹⁹ cm ⁻³ is shown. When the heat treatment temperature was 500 ° C., when the carrier concentration was 5 × 10 ¹⁹ cm ⁻³ or more, the contact resistance was about 1 × 10 ⁻⁶ Ωcm ² or less, and a good value could be obtained. On the other hand, when the carrier concentration was 1 × 10 ¹⁹ cm ⁻³ , the contact resistance was 2 × 10 ⁻⁵ Ωcm ² , indicating an order of magnitude higher contact resistance.

When the carrier concentration of the GaP contact layer 17 was 5 × 10 ¹⁹ cm ⁻³ or more, the contact resistance was maintained at about 1 × 10 ⁻⁶ Ωcm ² or less even when the heat treatment temperature was reduced to 400 ° C. and 350 ° C. However, it was found that when the carrier concentration is 1 × 10 ¹⁹ cm ⁻³ , the contact resistance increases rapidly at a heat treatment temperature of 400 ° C. or lower. Specifically, it was found that the contact resistance increases as 2 × 10 ⁻⁴ Ωcm ^{2 at} a heat treatment temperature of 400 ° C., and the contact resistance increases as 1 Ωcm ² (= 1E + 00 Ωcm ² ) at 350 ° C.

This is presumably because, when the carrier concentration is low, if the heat treatment temperature (alloying temperature) is low, the diffusion of impurities for obtaining ohmic contact is reduced, so that the contact resistance increases. On the other hand, it is considered that when the carrier concentration is 5 × 10 ¹⁹ cm ⁻³ or more, the contact resistance does not increase because the carrier concentration is high even if the heat treatment temperature is low and the diffusion of impurities is small. As described above, when the carrier concentration is 5 × 10 ¹⁹ cm ⁻³ or more, even when the heat treatment temperature is as low as 350 ° C., contact resistance comparable to that at 400 ° C. or more is obtained.

[Evaluation of LED elements]
Next, a light emitting device (LED element) 10 (FIG. 1, Example 1) having a bonded structure using the Si substrate described above as a supporting substrate was manufactured. As a comparative example, an LED element 90 in which the same semiconductor structure layer (LED structure layer) 91 as that of Example 1 was formed on a GaAs substrate was manufactured. More specifically, as shown in FIG. 7, the LED element 90 includes an n-type current diffusion layer 92A, an n-clad layer 92B, a quantum well active layer 94, a p-clad layer 96A, a p-type current on an n-GaAs substrate 90A. A diffusion layer 96B and a GaP contact layer 97 doped with carbon (C) were epitaxially grown. The crystal composition, layer thickness, carrier concentration, etc. of each layer are the same as those in the first embodiment. That is, the semiconductor structure layer 91 in the LED element 90 of the comparative example has the same layer structure as the semiconductor structure layer 11 of the first embodiment. A first electrode (p electrode) 98 was formed on the GaP contact layer 97, and a second electrode (n electrode) 99 was formed on the back surface of the n-GaAs substrate 90A. In addition, two types of samples each having a thickness of 50 nm and a carrier concentration of 1 × 10 ¹⁹ cm ⁻³ and 5 × 10 ¹⁹ cm ⁻³ were manufactured for the GaP contact layers 17 and 97 of Example 1 and Comparative Example. .

  As described above, in the LED element 10 having the bonded structure, the dielectric layer 20 is provided between the semiconductor structure layer 11 and the bonding metal layer, and a part of the dielectric layer 20 is removed, so that the semiconductor laminate 11 and the metal Electrical contact with the electrode layer 21 is obtained. However, in order to improve the light extraction efficiency, the area of the dielectric layer 20 is increased as much as possible (that is, the contact area between the semiconductor and the metal is reduced). In the LED element of the comparative example structure in which the semiconductor structure layer is formed on the substrate and the light is extracted from the surface of the semiconductor structure layer, the contact area (contact area) between the semiconductor and the metal is generally smaller than the LED element of the bonded structure. large. Specifically, in the LED element having the structure of the comparative example, the contact area between the semiconductor and the metal is, for example, about 25% of the element area, but in the LED element having the laminated structure, the contact is made to improve the light extraction efficiency. The area will be less than half of that. For example, in an LED element having a laminated structure, the contact area is, for example, about 3 to 15% of the element area. In the LED element 10 of Example 1, as described above, the contact area of the contact portion where the contact layer 17 and the electrode layer 21 contact is 5% of the element area. Further, in the LED element 90 of the comparative example, the contact area was set to 25% of the element area. In manufacturing the LED elements 10 and 90 of Example 1 and Comparative Example, the heat treatment (alloying) temperature was set to 400 ° C.

  The LED element 10 of Example 1 and the LED element 90 of the comparative example were mounted on a stem, and wiring by wire bonding was performed. Table 1 below shows the operating voltage Vf (@ 20 mA) when the LED element samples of Example 1 and Comparative Example are driven with a drive current of 20 mA.

As shown in Table 1, in the LED element 90 of the comparative example, when the carrier concentration of the carbon-doped contact layer 97 is 1 × 10 ¹⁹ cm ⁻³ and 5 × 10 ¹⁹ cm ⁻³ , the operating voltage is 1.95 V, 1.90V. On the other hand, the LED element 10 of Example 1 whose contact area is 1/5 of the LED element 90 also operates when the carrier concentration of the contact layer 17 is 1 × 10 ¹⁹ cm ⁻³ and 5 × 10 ¹⁹ cm ^−3. The voltages were 2.00 V and 1.92 V, which was not significantly different from the LED element 90 of the comparative example.

FIG. 8 shows a change in the operating voltage Vd with respect to the drive current Id of the LED element sample of Example 1. In addition, it has shown about the LED element sample which heat processing (alloying) temperature was 400 degreeC. In the low current driving region where the driving current Id is about 20 mA, even if the carrier concentration is different from 1 × 10 ¹⁹ cm ⁻³ and 5 × 10 ¹⁹ cm ⁻³ , there is no significant change in the operating voltage Vd of the LED element. As the drive current Id increases, a large difference appears in the operating voltage Vd due to the difference in carrier concentration of the contact layer 17. Such an increase in operating voltage causes a reduction in LED efficiency. That is, the lower the operating voltage, the higher the efficiency of the LED and the better the energy conversion efficiency. The LED device of the comparative example manufactured on the GaAs substrate and provided with the electrode does not cause a problem because it is not used in a large current driving region (for example, a current region exceeding 100 mA). However, the LED device having the bonding structure of Example 1 in which the GaAs substrate is peeled off and the Si substrate having a higher thermal conductivity is bonded is expected to be used in a large current driving region. Therefore, the increase of the operating voltage becomes a big problem. The increase in operating voltage means that more heat is generated in the LED device, which causes a decrease in efficiency.

That is, in order to improve the efficiency of the LED element 10 having a bonded structure, it is important to reduce the operating voltage in addition to the improvement of the internal quantum efficiency. In order to reduce the operating voltage, it is important to lower the contact resistance with the contact metal. However, as described above, in the case of the bonding structure, the contact area between the semiconductor layer and the metal becomes small, and therefore the carrier concentration (for example, about 1 × 10 ¹⁹ cm ⁻³⁾ of the semiconductor layer in the structure of the comparative example. ) Will increase the operating voltage. In particular, since a high-power semiconductor light emitting device is driven at a high current value, the influence of an increase in operating voltage due to a decrease in contact area becomes even more significant.

On the other hand, in order to reduce the contact resistance with the metal, it is necessary to increase the carrier concentration of the semiconductor layer in contact with the metal. However, when Mg or Zn is used as a dopant (for example, Patent Documents 3 and 4), the carrier concentration can be controlled only in the range of about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ^−3. It is difficult to produce a material having a concentration exceeding 5 × 10 ¹⁹ cm ⁻³ . Furthermore, when these doping materials are added in large quantities, the memory effect remaining in the growth furnace and Zn have a large diffusion coefficient and are easily diffused in the AlGaInP layer, and diffuse into unintended parts (active layer, etc.). Therefore, there are problems such as adversely affecting reliability. Further, since a large amount of impurities are added for high concentration doping, the growth is hindered and irregularities such as unevenness on the surface are likely to occur. Next, in the bonding structure of Example 1, the heat treatment temperature for making contact between the metal and the semiconductor layer, that is, when the alloying temperature is 500 ° C. for comparison with the case where the alloying temperature is 400 ° C. The metal-semiconductor interface was evaluated. FIG. 9 shows a cross-sectional SEM (Scanning Electron Microscope) image of the interface between the contact metal and the semiconductor when the heat treatment temperature is 500 ° C. (left side of the figure) and 400 ° C. (right side of the figure). FIGS. 10A and 10B show depth direction profiles obtained by secondary ion mass spectrometry (SIMS) when the heat treatment temperature is 500 ° C. and 400 ° C., respectively. From these figures, it can be seen that when the heat treatment temperature is 500 ° C., the metal (Au, Sn) is diffused from the metal layer into the semiconductor layer (C-doped GaP layer) (in FIG. 9, inside the broken circle). FIG. 10 (a)). Even if the barrier metal layer and the Sn absorption layer described above are provided between the electrode layer 21 that is the contact metal layer and the Sn-containing layer (AuSn layer 37) that is the bonding layer, Sn is contained from the Sn-containing layer. It turns out that it has spread | diffused in the semiconductor layer. On the other hand, when the heat treatment temperature was 400 ° C., no diffusion of the metal in the electrode layer 21 or the bonding layer into the semiconductor layer was observed (FIGS. 9 and 10B).

  In the SIMS profile (FIG. 10B) with a heat treatment temperature of 400 ° C., it seems that Au slightly penetrates the semiconductor layer (about 0.2 μm) from the interface between the semiconductor layer and the metal layer. However, the SIMS signal intensity (concentration) decreases sharply from the interface, and this state is considered to be clearly different from the case where the heat treatment temperature is 500 ° C. That is, when the heat treatment temperature is 500 ° C. (FIG. 10A), Au and Sn enter the contact layer 17 from the interface with a very high concentration and a gentle inclination, and the metal (Au and Sn) also enter the contact layer. Sn) is diffused in the contact layer 17.

  In the case of an LED element having a bonded structure, the bonded metal layer must have a bonding function and a barrier effect for preventing metal diffusion in addition to electrical conduction. If the metal used for bonding diffuses into the semiconductor by heat treatment, it causes deterioration in luminance, so that metal diffusion must be suppressed. As described above, the operating voltage Vf when the LED element 10 of Example 1 was mounted on the stem and driven with a drive current of 20 mA was 1.92V. This indicates that there is no problem even when the alloy temperature is 400 ° C.

  Further, two kinds of LED elements 10 of Example 1 having heat treatment temperatures different from 400 ° C. and 500 ° C. were mounted on the stem, wire bonding was performed, resin molding was performed, and an LED lamp was manufactured. When a 150 mA energization test was performed on the manufactured LED lamp, when the heat treatment temperature was 500 ° C., the luminance decreased with the energization, whereas when the heat treatment temperature was 400 ° C., there was almost no change in luminance due to the energization. I understood that. This is presumably because the metal in the bonding layer diffuses into the semiconductor layer due to alloying, and the luminance is deteriorated due to energization. This can also be inferred from the SEM image described above. That is, it is shown that the carbon-doped GaP contact layer 17 can lower the heat treatment (alloying) temperature without increasing the operating voltage, thereby further improving the reliability.

As described above, when the carrier concentration of the contact layer 17 is 5 × 10 ¹⁹ cm ⁻³ or more and the heat treatment temperature is 400 ° C. or less, diffusion of the metal in the bonding layer into the semiconductor is suppressed. It was found that ohmic contact can be obtained. The heat treatment temperature may be higher than the temperature at which the semiconductor of the contact layer 17 and the metal of the metal electrode layer 21 are alloyed to form an ohmic contact (alloying temperature), and is preferably 350 ° C. or higher.

In the above embodiment, it was shown that the carbon-doped GaP contact layer 17 has good characteristics when the carrier concentration is 5 × 10 ¹⁹ cm ⁻³ , but similar good characteristics are obtained even when the carrier concentration is higher than that. Obviously you get. In view of the surface state (morphology), the upper limit of the carrier concentration is about 5 × 10 ²⁰ cm ⁻³ .

In the above embodiment, an AlGaInP layer is used for the clad layer and the active layer, but it is fabricated under the condition of lattice matching with the GaAs substrate. The conditions for lattice matching with GaAs vary depending on the growth temperature. In order to lattice match with the GaAs substrate, _{x of} (Al _y Ga _1-y ) _x In _1-x P may be adjusted. When growing in the temperature range of 500 ° C. to 700 ° C., the range of (Al _y Ga _1-y ) _x In _1-x P is 0.45 ≦ x ≦ 0.55. Even in this range, the effect obtained by adjusting the carrier concentration and the layer thickness obtained in the present invention does not change. When the active layer has a quantum well structure, the well layer and the barrier layer do not need to be lattice-matched to the GaAs substrate as long as the thickness is equal to or less than the critical film thickness. The preferable composition ranges of the well layer and the barrier layer are (Al _y Ga _1-y ) _x In _1-x P (0.4 ≦ x ≦ 0.6), (Al _y Ga _1-y ) _x , respectively, considering the critical film thickness. In _1-x P (0 ≦ x ≦ 0.7).

Further, as the n-clad layer in the above embodiment uses an AlInP, n clad layer may be any composition that can effectively confined in the active layer transparent and electrons to the active layer, (Al _y Ga _{1- y} ) _x In _1-x P (0.4 ≦ x ≦ 0.6, 0 ≦ y ≦ 1.0) is acceptable.

In addition, the case where SiH ₄ (silane) is used as a dopant in order to obtain n-type conductivity has been described as an example, but DeTe (diethyl tellurium) or H ₂ Se (hydrogen selenide) may be used. . That is, the effect of the present invention is not changed by the n-type impurity, does not depend on the type of impurity in the n-type layer, and the obtained effect is not changed. Further, the layer thickness of the n-clad layer does not affect the present invention and is not limited to the above 3 μm.

  In the present embodiment, the case of a quantum well structure that emits red light (Al composition of Al in the well layer is 10%) has been described as an example. If the structure is made an embodiment of the present invention, the effect of the present invention can be obtained. The same applies to the Al composition of the well layer, and the effect of the present invention does not change even if the Al composition is changed to obtain a yellow light emitting (wavelength 590 nm) element or a crimson light emitting element (wavelength 660 nm). The same applies to the off-angle of the substrate, and the same effect can be obtained even if a GaAs substrate having a different off-angle and off-direction is used. The same effect has been confirmed when using an n-type GaAs substrate which is turned off by 4 degrees from the (100) plane.

  For the current spreading layer, GaP was used in this example. However, even when In is added to form InGaP, it is sufficient that the current spreading layer is transparent to the active layer, which affects the effect of the present invention. It is not a thing.

  In the above embodiment, Si (silicon) is used as the bonding substrate. However, the present invention is also effective for a light-emitting device that is bonded to another permanent substrate (for example, copper or glass). The electrode structure may be any structure as long as a current is injected into the active layer through a pn junction, and there is no need to dispose the electrodes above and below, and for example, a flip chip type structure may be used.

10A growth substrate 11 semiconductor structure layer 12A n-type current diffusion layer 12B n-clad layer 14 active layer 16A p-clad layer 16B p-type current diffusion layer 17 p contact layer 20A opening 20 dielectric layer 21 metal electrode layer

Claims (8)

N-type semiconductor layer, each having a composition _{(Al y Ga 1-y)} x In 1-x P (0.4 ≦ x ≦ 0.6,0 ≦ y ≦ 1.0) on a semiconductor substrate, growing an active layer and a p-type semiconductor layer And growing a carbon-doped Ga _1-z In _z P contact layer (0 ≦ z ≦ 0.1) on the p-type semiconductor layer;
Forming a dielectric layer on the contact layer having an opening through which the contact layer is exposed;
Forming a metal electrode layer on the dielectric layer and the opening;
Forming a first bonding metal layer on the metal electrode layer;
Performing a heat treatment to form an ohmic contact between the contact layer and the metal electrode layer exposed from the opening;
Using a support in which a second bonding metal layer is formed on a support substrate, and bonding the first bonding metal layer and the second bonding metal layer by thermocompression bonding, and
A method for manufacturing a light-emitting element, wherein the carrier concentration of the contact layer is 5 × 10 ¹⁹ cm ⁻³ or more, and the temperature of the heat treatment is 400 ° C. or less.   The manufacturing method according to claim 1, wherein a temperature of the heat treatment is 350 ° C. or more and 400 ° C. or less.   The manufacturing method according to claim 1, wherein a temperature of the thermocompression bonding does not exceed a temperature of the heat treatment. The manufacturing method according to claim 1, wherein the carrier concentration of the contact layer is 5 × 10 ¹⁹ cm ⁻³ or more and 5 × 10 ²⁰ cm ⁻³ or less.   5. The method according to claim 1, wherein at least one of the first bonding metal layer and the second bonding metal layer includes an AuSn layer.   6. The manufacturing method according to claim 1, wherein the first bonding metal layer includes a barrier metal layer formed on the metal electrode layer.   7. The method according to claim 1, wherein the contact layer is grown by MOCVD in a range of V / III ratio of 2 to 5.   The manufacturing method according to claim 1, wherein the n-type semiconductor layer, the active layer, and the p-type semiconductor layer constitute a light emitting diode structure layer.