KR101057754B1 - Device isolation structure manufacturing method of semiconductor device - Google Patents

Abstract

Disclosed is a method for manufacturing a device isolation structure of a semiconductor device. The method of manufacturing a device isolation structure of the semiconductor device includes forming at least one material layer on a substrate, forming a pad pattern on the material layer to define a plurality of device isolation regions, and a pad. Forming a plurality of trenches having different depths using the pattern as an etch mask, and fabricating a device isolation structure by filling a plurality of trenches through a selective oxide (SELOX) forming process, respectively. Device isolation structure manufacturing method. As a result, poor embedding such as voids can be prevented.

Trench, Element Isolation, SELOX, Landfill, Void

Description

Method for forming a isolation structure of semiconductor device

The present invention relates to a method for manufacturing a device isolation structure of a semiconductor device, and more particularly, to a method for manufacturing a device isolation structure of a semiconductor device that prevents voids due to a poor filling in the trench filling process.

BACKGROUND With the development of electronic technology, the demand for small and multifunctional electronic devices is increasing. Accordingly, System on Chip (SoC) technology is being introduced. System on chip refers to a technology in which a plurality of devices are integrated on one chip to implement a system.

In particular, with the recent development and introduction of Micro-Electro-Mechanical Systems (MEMS) technology or Nano-Electro-Mechanical Systems (NEMS) technology, efforts have been made to implement more various devices in one chip.

However, when a plurality of devices are integrated on one substrate, there is a great chance of interference between the devices. That is, heat generated when driving in one device may be transferred to another device through the substrate, thereby affecting the operation of another device. Accordingly, there was a problem that can cause a lot of malfunction.

In order to prevent this, a device isolation structure is typically manufactured to electrically isolate devices from each other on a substrate.

In order to form a device isolation structure, a trench having a predetermined depth is formed in the silicon substrate, an oxide film is embedded in the trench, and then a chemical mechanical polishing process is used to polish an unnecessary portion of the oxide film. In recent years, a TI (Trench Isolation) process for forming a device isolation structure in a silicon substrate has been widely used.

However, when the depth of the trench for forming the device isolation structure is shallow, the interference between the devices may not be sufficiently prevented. Accordingly, when the area of the device isolation structure is increased, there is a problem that the size of the entire chip is increased.

On the other hand, in consideration of these problems, when the device isolation structure is manufactured by deepening the trench, there is a problem that the device isolation structure may not be properly manufactured.

1 is a schematic view for explaining the problem of the device isolation structure manufactured according to the prior art.

As shown in FIG. 1, when the substrate 10 is etched to fabricate a deep trench, when the trench is buried (ie, gap-filled) with polysilicon 20 or the like in a subsequent process, a trench inlet is formed. The portion may be buried first to cause voids 30 and the like.

Such voids can weaken the function of the device isolation structure. In other words, neighboring active regions are shorted to each other, thereby degrading the characteristics and reliability of the device.

In addition, the void portion also increases the possibility of damage to the entire device, there was a problem that the manufacturing yield is also reduced.

Accordingly, an object of the present invention is to provide a method for manufacturing a device isolation structure of a semiconductor device that can prevent the buried defects such as voids by using the SELOX formation process during the trench buried process.

In order to achieve the above object, a method of manufacturing a device isolation structure of a semiconductor device according to the present invention may include forming at least one material layer on a substrate, and forming a plurality of device isolation regions on the material layer. Forming a pad pattern to define a shape, forming a plurality of trenches having different depths using the pad pattern as an etching mask, and filling the plurality of trenches through a selective oxide (SELOX) forming process, respectively. And manufacturing a device isolation structure.

In this case, the method of manufacturing a device isolation structure of the semiconductor device may further include removing an oxide film formed on the material layer by the SELOX forming process.

In this case, the step of removing the oxide film, it is preferable to use a hydrofluoric acid solution or BOE (Buffered Oxide Echant).

On the other hand, the device isolation structure manufacturing method of the semiconductor device may further comprise the step of forming a side wall oxide film on the inner wall of the trench.

In the manufacturing of the device isolation structure by filling the trench, it is preferable to use a tetraethylorthosilicate (TEOS) gas and an ozone gas.

In this case, the step of manufacturing the device isolation structure by filling the trench, it is preferably carried out at 400 ℃ to 900 ℃ temperature.

Meanwhile, the method of manufacturing the device isolation structure by filling the trench may be performed at 400 Torr to 760 Torr.

On the other hand, the device isolation structure manufacturing method of a semiconductor device according to another embodiment of the present invention, forming at least one material layer (material layer) on the substrate, on the material layer, for defining a device isolation region Forming a pad pattern, forming a deep trench using the pad pattern as an etch mask, and filling the deep trench through a selective oxide (SELOX) forming process to form a first device isolation structure. Fabricating, forming a new shallow trench having a shallower depth than the trench at a position spaced apart from the first device isolation structure by a predetermined distance, and oxidizing the bottom and side surfaces of the new trench. And, embedding said new trench with oxide.

In this case, it is preferable that the method of manufacturing the device isolation structure of the semiconductor device further includes removing the oxide film formed on the material layer by the SELOX forming process.

In this case, the step of removing the oxide film, it is preferable to use a hydrofluoric acid solution or BOE (Buffered Oxide Echant).

Meanwhile, in the manufacturing of the first device isolation structure by filling the deep trench, it is preferable to use a tetraethylorthosilicate (TEOS) gas and an ozone gas.

On the other hand, the step of filling the first trench to produce the first device isolation structure, it is preferably carried out at 400 ℃ to 900 ℃ temperature.

On the other hand, the step of filling the trench to manufacture the first device isolating structure, it is preferably carried out at 400 Torr to 760 Torr pressure.

According to various embodiments of the present disclosure, voids may be prevented by using the SELOX forming process in the process of filling the trench for forming the device isolation structure.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A to 2G are cross-sectional views illustrating a method of manufacturing a device isolation structure of a semiconductor device according to an embodiment of the present invention.

First, referring to FIG. 2A, the material layer 110 is formed on the substrate 100.

The substrate 100 may be a conventional silicon substrate, a high resistance silicon substrate, or the like. The material layer 110 may be formed in a film form on the upper surface of the substrate 100.

Here, the material layer 110 serves to suppress the formation of an oxide film in a subsequent SELOX forming process, and as shown in FIG. 2A, the material layer 110 may be implemented as a multilayer composed of a plurality of materials, and may be implemented as a single layer. May be Various configurations of the material layer 110 will be described later.

According to the embodiment of FIG. 2A, the material layer 110 is implemented in such a manner that the oxide film 111, the nitride film 112, and the oxide film 113 are sequentially stacked. The oxide film 111 serves to relieve stress between the substrate 100 and the nitride film 112, and serves as an etch stop film when the nitride film 112 is subsequently removed. In addition, the nitride layer 112 suppresses the formation of an oxide layer in a subsequent SELOX forming process, and functions as an etch stop layer when the subsequent oxide layer 113 is removed. The oxide film 113 may be implemented as a tetraethylorthosilicate (TEOS) oxide film, and the TEOS oxide film may be formed using a Plasma Enhancement Chemical Vapor Deposition (PECVD) method using TEOS gas.

Next, as shown in FIG. 2B, a pad pattern 120 for defining an element isolation region is formed. The device isolation region means a position where the device isolation structure is to be manufactured. In detail, the pad pattern 120 may be formed on the material layer 110 using the photoresist to expose the trench formation region on the material layer 110.

Next, as illustrated in FIG. 2C, the exposed portion of the material layers 111, 112, and 113 and the region of the substrate 100 below the substrate 100 may be etched using the pad pattern 120 as an etching mask. A trench 140 having a predetermined depth may be formed. The depth of the trench 140 may be variously set according to the embodiment. In this case, the trench 140 having a predetermined depth or more may be manufactured to improve the interference preventing performance between the devices. The shape of the trench 140 may also be variously set. For example, it may be produced in the form of a circle column, polygonal column and the like.

The trench 140 may then be buried through the SELOX forming process, as shown in FIG. 2D.

Here, a selective oxide (SELOX) formation (selective oxide deposition) process refers to a process of selectively depositing oxides using different deposition rates on nitride and silicon. Specifically, the SELOX forming process may chemically deposit an oxide film (CVD) using ozone activated tetraethylorthosilicate (O ₃ : TEOS), that is, a source of TEOS gas and ozone gas.

In this case, by adjusting the ratio of TEOS gas and ozone gas, it is possible to selectively deposit an oxide by varying the deposition rate in silicon and nitride.

In the present embodiment, the SELOX forming process may be performed by a chemical vapor deposition (CVD) method using TEOS gas and ozone gas at a pressure of about 400 Torr to 760 Torr and 400 ° C to 900 ° C. The TEOS gas and the ozone gas may be injected such that the ratio (0 ₃ / TEOS) of the ozone gas to the TEOS gas is more than 0 and 1 or less.

The oxide film produced according to this SELOX forming process depends on the characteristics of the surface film in which the oxide film is produced. That is, in FIG. 2D, the side surface a of the inlet portion of the trench 140 is made of the material layer 110, and the bottom side surface and the bottom surface b of the trench 140 are made of the substrate 100 material. In the SELOX forming process, since the oxidation rate in the nitride film 112 portion is relatively slow, the phenomenon in which the inlet portion of the trench 140 is buried first is prevented. As a result, it is possible to prevent the formation of voids.

Then, as shown in FIG. 2E, the oxide film formed on the material layer 110 is removed by the SELOX forming process. The oxide film may be removed through a cleaning process. In this case, together with the oxide film formed on the material layer 110, the TEOS oxide film 113 forming the material layer 110 may be selectively removed. The washing process may use hydrofluoric acid (HF) solution or BOE (Buffered Oxide Echant).

Next, as illustrated in FIG. 2F, an oxidation process of forming the sidewall oxide layer 151 on the inner wall of the trench 140 may be performed. Specifically, the surface grating inside the trench may be damaged in the process of forming the trench 140, that is, in the trench etching process, an oxidation process may be performed to compensate for the damage of the surface grating.

Thereafter, a pad pattern removal process and a planarization process, which are subsequent processes for forming the device isolation structure, are performed. As shown in FIG. 2G, the device isolation structure in which the oxide film 150 is embedded in the trench 140 is formed. Can be formed.

Meanwhile, a device isolation structure in which deep trench isolation (DTI) and shallow trench isolation (STI) coexist by using the above-described method for fabricating an isolation structure of a semiconductor device. In this case, a semiconductor device having a plurality of device isolation structures having different depths can be manufactured. Each device isolation structure may be simultaneously manufactured by fabricating a plurality of trenches when performing the processes of FIGS. 2A to 2G and filling each trench in a batch, or adding a separate process in addition to the processes of FIGS. 2A to 2G. It may be produced sequentially. This may be variously implemented according to an embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a device isolation structure according to another embodiment of the present invention, that is, a method of manufacturing a plurality of device isolation structures having different depths. The present embodiment may be made in such a manner that some subsequent processes are added after the processes of FIGS. 2A to 2E are performed. For the convenience of description, overlapping steps are omitted, and the same parts as those described in FIGS. 2A to 2G use the same reference numerals.

First, according to FIG. 3A, in a state in which the trench 140 is buried and the first device isolation structure (ie, the DTI structure) is manufactured as shown in FIG. 2E, at a position spaced a predetermined distance from the first device isolation structure, The photoresist pattern 160 is formed to form a new shallow trench 142 that is shallower than the trench 140. As discussed above, the DTI structure can be fabricated in a SELOX formation process.

The photoresist pattern 160 may cover the exposed surface of the device isolation structure 150 and a part of the nitride film 112 and expose only a region of the nitride film 112 where a new shallow trench 142 is to be formed. have.

Next, an etching process is performed using the photoresist pattern 160 as an etching mask to form a new shallow trench 142 having a depth shallower than that of the trench 140 as shown in FIG. 3B.

Then, as illustrated in FIG. 3C, an oxidation process is performed to form the sidewall oxide layer 170 on the bottom and side surfaces of the trench 142.

At this time, since the oxidation is performed on the entire structure being manufactured, oxidation may also proceed together at the bottom and side surfaces 151 of the trench 140 in which the DTI device isolation structure 150 is formed. Accordingly, a defect formed in the trench 140, that is, a damaged surface grating in the trench 140 generated in the trench etching process may be cured.

As shown in FIG. 3D, the oxide film 180 is embedded to completely fill the shallow trench 142. In this case, an HDP (High Density Plasma) film having good embedding characteristics may be used as the oxide film 180.

Subsequently, a pad pattern removal process, a planarization process, and the like, which are subsequent processes for forming the device isolation structure, are performed to form a plurality of device isolation structures having different depths in which oxide films are embedded, as shown in FIG. 3E. Can be. In this case, since the device isolation structure manufactured in FIGS. 3A to 3E is manufactured using the trench 142 having a depth smaller than that of the previous trench 140, the device isolation structure having a shallower depth than that of the DTI structure 150 (that is, STI) is described. (Shallow Trench Isolation) structure. As a result, a structure in which the DTI structure and the STI structure coexist can be produced.

Meanwhile, as described above, the deep trench isolation (DTI) structure and the shallow trench isolation (STI) structure may be manufactured in a batch.

4A to 4E are cross-sectional views illustrating an example of a method of fabricating a device isolation structure in which a DTI structure and an STI structure are fabricated according to another embodiment of the present invention.

First, as shown in FIG. 4A, a plurality of trenches having different depths are formed on the substrate 100 on which the material layer 110 is formed. To this end, as shown in FIG. 2A, a material layer 110 having various shapes is formed on the surface of the substrate 100, and as illustrated in FIGS. 2B and 2C, a pad pattern for defining a device isolation region is formed, and the oxide layer is formed using the same. The 111, the nitride film 112, the oxide film 113, and the substrate 100 are etched to form first trenches 140 and second trenches 142 having different depths.

Then, as illustrated in FIG. 4B, the first trenches 140 and the second trenches 142 having different depths are simultaneously buried using the SELOX forming process. In this case, since the first trench 140 and the second trench 142 have different depths, there may be a difference in time required for the filling process of each of the trenches 140 and 142. However, even if the inside of the second trench 142 having a relatively shallow depth is completely buried first, oxide deposition in the second trench 142 is suppressed by the material layer 110 positioned at the inlet of the second trench 142. Bar, only a small amount of oxide film is additionally deposited in the second trench 142 until the filling of the first trench 140 is completed after the second trench filling. Therefore, the filling process may be maintained until the filling of the relatively deep first trench 140 is completed, so that the filling of all the trenches 140 and 142 may be performed.

Next, as shown in FIG. 4C, the oxide layer formed on the material layer, particularly, the top layer 113 may be removed by the SELOX forming process. In this process, the oxide film 113, which is the uppermost layer, can also be removed.

Next, as illustrated in FIG. 4D, an oxidation process of forming sidewall oxide layers 151 may be performed on side and bottom surfaces of each of the trenches 140 and 142.

Finally, a pad pattern removal process, a planarization process, and the like, which are subsequent processes for forming the device isolation structure, are performed to form a plurality of device isolation structures having different depths, as shown in FIG. 4E.

Meanwhile, as described above, material layers of various materials may be formed on the surface of the substrate 100. 5A and 5B illustrate various forms of material layer 110 configuration that may be formed on the surface of the substrate 100.

First, as illustrated in FIG. 5A, the material layer 110 may be implemented by sequentially stacking the first oxide layer 111 and the first nitride layer 112 from the surface of the substrate 100.

5B illustrates an example in which the material layer 110 is implemented in a form in which a plurality of oxide films and a plurality of nitride films are alternately disposed. That is, according to FIG. 5B, the first oxide film 111, the first nitride film 112, the second oxide film 113, and the second nitride film 114 are sequentially stacked on the surface of the substrate 100 to form a material layer 110. ) Can be achieved.

As such, various types of material layers 110 may be implemented to slow down the oxidation rate of the trench inlet during SELOX formation.

As shown in FIGS. 3A to 3E and 4A to 4E, a structure in which a DTI structure and an STI structure coexist is easier to implement a system-on-chip integrated with various kinds of devices. That is, the STI structure is arranged between the devices driven at low power, and the DTI structure is arranged between the devices that can cause relatively high interference, and thus the overall chip size, manufacturing yield, and interference prevention performance are comprehensively integrated. Can be improved.

Meanwhile, the characteristics of the oxide film formed by the SELOX forming process used in the above-described embodiments may be described with reference to FIGS. 6A and 6B.

FIG. 6A is a cross-sectional photograph of a scanning electron microscope (SEM) showing a characteristic of an oxide film formed through a SELOX forming process on single crystal silicon, and FIG. 6B is a scan electron showing a characteristic of an oxide film formed through a SELOX forming process on a nitride film. Microscopic cross section.

Referring to FIG. 6A, when the SELOX forming process is performed on single crystal silicon, the oxide layer 150 is uniformly formed on the single crystal silicon, that is, the substrate 100.

On the other hand, referring to FIG. 6B, when the SELOX forming process is performed on a surface film such as a nitride film other than single crystal silicon, a rough and shallow oxide film is formed on the nitride film as shown. As such, it can be seen that the oxide film formation rate of the material layer 110 in the trench 140 is lower than that of the remaining parts.

In addition, a process of selectively filling oxide in the trench 140 using the SELOX forming process will be described in more detail with reference to FIGS. 7A to 7D.

7A to 7D are scanning electron microscope cross-sectional views showing a buried process by the SELOX forming process in the trench. 7A to 7D are photographs of a buried process in one trench 140 as time passes. In FIG. 7, FIGS.

As shown in FIGS. 7A-7D, when the SELOX formation process is performed, the interior of the trench (ie, bottom (b region) and bottom side surface in FIG. 2D) has a surface film such as monocrystalline silicon and relatively An oxide film is formed at a high speed. However, at the surface where the material layer 110 is formed (that is, the upper side surface (a region in FIG. 2D)), an oxide film is formed at a slow speed because it has the same surface film quality as the nitride film.

In this case, since the material layer 110 is positioned at the inlet portion of the trench 140, the inlet may be prevented from being buried first. Meanwhile, in order to prevent voids from being formed in the lower side surface and the bottom surface (b region) of the trench 140, the SELOX conditions (for example, conditions such as gas injection speed, temperature, and pressure) are appropriately applied. Can be set. As a result, embedding failure such as voids does not occur.

Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the above-described embodiments, and the present invention is well known in the art without departing from the gist of the present invention as claimed in the claims. Anyone with a variety of modifications can be made, as well as such changes are within the scope of the claims.

1 is a schematic view for explaining the problem of the device isolation structure manufactured according to the prior art,

2A to 2G are cross-sectional views illustrating a method of manufacturing a device isolation structure of a semiconductor device according to an embodiment of the present invention;

3A to 3E are cross-sectional views illustrating an example of a method of manufacturing a plurality of device isolation structures having different depths according to another embodiment of the present invention;

4A to 4E are cross-sectional views illustrating an example of a method of fabricating a device isolation structure in which a DTI structure and an STI structure are fabricated in accordance with another embodiment of the present invention;

5A and 5B illustrate various forms of the material layer shown in FIG. 2A;

6A and 6B are scanning electron microscope cross-sectional views showing the characteristics of the oxide produced according to the surface film quality, and

7A to 7D are scanning electron microscope cross-sectional views illustrating a trench filling process by the SELOX deposition process of FIG. 2D.

* Description of the symbols for the main parts of the drawings *

100: silicon substrate 110: material layer

120: pad pattern 140: trench

150: oxide film 160: pad pattern

170: sidewall oxide film 180: oxide film

Claims (13)

Forming at least one material layer on the substrate; Forming a pad pattern on the material layer to define a plurality of device isolation regions; Forming a plurality of trenches having different depths using the pad pattern as an etch mask; And And filling the plurality of trenches simultaneously through a selective oxide (SELOX) forming process to fabricate a device isolation structure. Forming the material layer (material layer), Forming a first oxide film, a first nitride film and a second oxide film sequentially on the substrate. The method of claim 1, Removing the oxide film formed on the material layer by the SELOX forming process. The method of claim 2, Removing the oxide film, Device isolation structure manufacturing method of a semiconductor device, characterized in that using a hydrofluoric acid solution or BOE (Buffered Oxide Echant). The method of claim 2, Forming a sidewall oxide film on the inner sidewall of the trench; The method of claim 1, The step of manufacturing the device isolation structure by filling the trench, A method of manufacturing a device isolation structure for a semiconductor device, comprising using a tetraethylorthosilicate (TEOS) gas and an ozone gas. 6. The method according to any one of claims 1 to 5, The step of manufacturing the device isolation structure by filling the trench, Device isolation structure manufacturing method of a semiconductor device, characterized in that carried out at 400 ℃ to 900 ℃ temperature. 6. The method according to any one of claims 1 to 5, The step of manufacturing the device isolation structure by filling the trench, Device isolation structure manufacturing method of a semiconductor device, characterized in that performed at 400 Torr to 760 Torr pressure. delete Forming at least one material layer on the substrate; Forming a pad pattern on the material layer to define a plurality of device isolation regions; Forming a plurality of trenches having different depths using the pad pattern as an etch mask; And And filling the plurality of trenches simultaneously through a selective oxide (SELOX) forming process to fabricate a device isolation structure. Forming the material layer A first isolation film, a first nitride film, a second oxide film, and a second nitride film are sequentially formed on the substrate. The method of claim 2, Removing the oxide film, And removing the second oxide layer of the material layer together. delete delete delete

Images