KR101054888B1 - Integrated chip arrangement of battery protection circuit - Google Patents

Abstract

The present invention relates to an integrated chip arrangement structure of a battery protection circuit, wherein the integrated chip arrangement structure of the battery protection circuit according to the present invention includes first to fifth connection terminals made of a conductive material spaced apart from each other at edge portions thereof. A base substrate having a chip region for chip stacking and a first conductive region and a second conductive region adjacent to the chip region; A dual FET chip stacked on the chip region of the base substrate and including a first FET and a second FET having a common drain structure; Is disposed on the upper surface of the dual FET chip, and detects the over-discharge state when the battery is discharged, and control the first FET during the over-discharge, stop the discharge operation of the battery, and detects the overcharge state when the battery is charged And a protection IC configured to stop the charging operation by controlling the second FET in an overcharge state to form a single integrated chip. According to the present invention, the size can be reduced, which is advantageous for miniaturization, less risk of breakage, and process simplification.

Battery, protection circuit, over discharge, over charge, one chip, protection IC, FET, integration, miniaturization

Description

One chip layout structure of battery protection circuits}

The present invention relates to an integrated chip (one chip) arrangement of the battery protection circuit, and more specifically, by configuring the chips and some resistors and capacitors constituting the battery protection circuit into one chip, the overall size is reduced, and the external shock is strong. The present invention relates to an integrated chip arrangement structure of a battery protection circuit, which can reduce manufacturing costs.

In general, mobile phones, PDAs, and the like have been used in batteries for portable terminals.

Lithium-ion batteries are the most widely used batteries in portable terminals and the like. They generate heat during overcharging and overcurrent, and if the heat continues to increase in temperature, performance deterioration and risk of explosion occur.

Therefore, a normal battery is equipped with a protection circuit module for detecting and blocking overcharge, overdischarge and overcurrent, or install a protection circuit for detecting overcharge, overdischarge, overheating and blocking operation of the battery outside the battery. .

This conventional protection circuit is made by soldering a protection IC and two FETs, a resistor, and a capacitor to a printed circuit board by soldering, and completing the battery pack by mounting the battery cell and overlaying the housing. . However, the space occupied by the protection IC, the two FETs, the resistors, and the capacitors is so large that there is a limit to miniaturization and weakness in external shock. In addition, since a protection IC, two FETs, at least two resistors, and at least one capacitor are disposed on a printed circuit board, a large space occupies and difficult integration.

Accordingly, an object of the present invention is to provide an integrated chip arrangement structure of a battery protection circuit that can overcome the above-mentioned conventional problems.

Another object of the present invention is to provide an integrated chip arrangement structure of a battery protection circuit, which is advantageous for miniaturization.

Another object of the present invention is to provide an integrated chip arrangement structure of a battery protection circuit that is easy to test and resistant to external shock.

Still another object of the present invention is to provide an integrated chip arrangement structure of a battery protection circuit which can achieve a process simplification.

According to an embodiment of the present invention for achieving some of the above technical problems, in the integrated chip arrangement structure of the battery protection circuit according to the present invention, the first to fifth connection terminals of the conductive material are arranged spaced apart from each other at the edge portion A base substrate having a chip region for chip stacking and a first conductive region and a second conductive region adjacent to the chip region; A dual FET chip stacked on the chip region of the base substrate and including a first FET and a second FET having a common drain structure; Is disposed on the upper surface of the dual FET chip, and detects the over-discharge state when the battery is discharged, and control the first FET during the over-discharge, stop the discharge operation of the battery, and detects the overcharge state when the battery is charged And an integrated chip having a protection IC disposed therein to control the second FET in an overcharge state to stop the charging operation, wherein the first conductive region has a charge voltage and a discharge voltage in the protection IC. The voltage applying terminal VDD is electrically connected to each other through a wire or a wire, and the second conductive region is electrically connected to a sensing terminal V- and a wire or a wire for detecting a charge / discharge state in the protection IC. The first connection terminal disposed on the base substrate is connected to the source terminal of the first FET and the reference voltage terminal VSS of the protection IC through a wire or a wire. Are electrically connected and partly protrudes out of the integrated chip to form a first external connection terminal of the integrated chip, and the second connection terminal disposed on the base substrate is connected to a source terminal of the second FET through wires or wires. An electrical connection and a part of which protrudes out of the integrated chip to form a second external connection terminal of the integrated chip, and a fifth connection terminal disposed on the base substrate is connected to the first conductive region through a first capacitor. And a part of which protrudes outwardly of the integrated chip to form a fifth external connection terminal of the integrated chip, and the fourth connection terminal disposed on the base substrate is connected to the first conductive region through a first resistor and partially Protruding to the outside of the integrated chip to form a fourth external connection terminal of the integrated chip, and the third connection terminal disposed on the base substrate is connected to the second conductive region through a second resistor. It is connected and has a layout structure which part of the projecting out of the integrated chip to form a third external connection terminal of the integrated chip.

The discharge interrupt signal output terminal DO, which outputs a discharge interrupt signal for turning off the first FET in an over discharge state in the protection IC, is electrically connected to a gate terminal of the first FET through a wire or a wire, and the protection is performed. In the IC, the charge blocking signal output terminal CO outputting the charge blocking signal for turning off the second FET in an overcharge state may have a structure electrically connected to the gate terminal of the second FET through a wire or a wire.

The first resistor is a chip type or SMD type and connects between the fourth connector and the first conductive region, and the second resistor is a chip type or SMD type and is connected to the third connection terminal. It may have a structure for connecting between the second conductive region.

A second capacitor and a third capacitor are further disposed on the integrated chip, and the second capacitor connects between the third connector and the fourth connection terminal, and the third capacitor is connected to the first connector and the first capacitor. It may have a layout structure for connecting between the two connection terminals.

According to the present invention, since the resistor or the capacitor constituting the battery protection circuit is present in the integrated chip, there is an advantage that is strong against external shock and less likely to be damaged. In addition, the space occupied by the existing resistors and capacitors and the space occupied by the protection ICs and FETs can be reduced, which is advantageous for miniaturization and integration. It also facilitates testing and reduces the soldering process for joining peripheral components.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings without intending to intend to provide a thorough understanding of the present invention to a person having ordinary skill in the art to which the present invention belongs.

1 shows a general battery protection circuit.

As shown in FIG. 1, both terminals of the battery V1 are connected to a protection circuit, the protection circuit is connected to a charging circuit through terminals (+,-) at the time of charging, and operated by battery power at the time of discharge. Electronic devices (eg, portable terminals, etc.) are attached.

The battery protection circuit has a connection structure of the switching elements 110, the protection IC 120, the resistors R1 and R2, and the capacitor C1.

The switching elements 110 include a first switching element FET1 and a second switching element FET2 having a drain common structure.

The protection IC 120 is connected to the (+) terminal of the battery V1 through a resistor R1 and is a voltage applying terminal (VDD terminal) to which the charging or discharging voltage of the first node n1 is applied, and the protection IC ( 120) the reference terminal (VSS terminal) as a reference for the internal operating voltage, the monitoring terminal (V-terminal) for detecting the charging and discharging state, the discharge interruption for turning off the first switching element (FET1) in the over-discharge state A signal output terminal DO terminal and a charge interruption signal output terminal C0 terminal for turning off the second switching element FET2 in an overcharge state.

At this time, the inside of the protection IC 120 includes a reference voltage setting unit, a comparison unit for comparing the reference voltage and the charge / discharge voltage, an overcurrent detector, and a charge / discharge detector. Here, the criterion of the charging and discharging state can be changed to the SPEC required by the customer by inputting the electrical characteristics to the wafer. Determine.

When the protection IC 120 reaches an over-discharge state during discharge, the DO terminal goes low to turn off the first switching element FET1, and when the overcharge state reaches the over-charge state, the CO terminal goes low. The switching element FET2 is turned off, and when the overcurrent flows, the second switching element FET2 is charged during charging and the first switching element FET1 is turned off when discharging.

The resistor R1 and the capacitor C1 serve to stabilize the fluctuation of the power supply of the protection IC 120. The resistor R1 is connected between the first node, which is the power supply V1 of the battery, and the VDD terminal of the protection IC 120, and the capacitor C1 is connected between the VDD terminal and the VSS terminal of the protection IC. do.

When the resistor R1 is made larger, the detection voltage is increased due to the current penetrating into the protection IC 120 during voltage detection. Therefore, the value of the resistor R1 is set to an appropriate value of 1 K? In addition, the value of the capacitor (C1) has a suitable value of 0.01μF or more for the stable operation.

In addition, the resistors R1 and R2 become current limiting resistors when the high voltage charger or the charger exceeding the absolute maximum rating of the protection IC 120 is connected upside down. The resistor R2 is connected between the V-terminal of the protection IC 120 and the second node n2 to which the source terminal S2 of the second switching element FET2 is connected. Since the resistors R1 and R2 may cause power consumption, the sum of the resistance values of the resistors R1 and R2 is usually set to be larger than 1 KΩ. If the resistor R2 is too large, the recovery may not occur after the overcharge cutoff, and thus the value of the resistor R2 is set to a value of 10 K? Or less.

The resistors R1 and R2 and the capacitor C1 together with the switching elements 110 and the protection IC 120 are essential components of the battery protection circuit, and most of the resistors R1 and R2 and the capacitor C1 are predetermined. Less room for change

Accordingly, when the general battery protection circuit as shown in FIG. 1 is integrated into one integrated chip including peripheral components such as resistors or capacitors, the area occupied by the battery protection circuit may be reduced, It will be able to protect resistors or capacitors from external shocks. In addition, the test can be facilitated, and since peripheral components such as resistors and capacitors exist inside, it may have an advantage of less damage due to bending.

Hereinafter, an integrated chip arrangement structure in which the battery protection circuit except for the battery portion V1 is one-chip in the battery protection circuit shown in FIG. 1 will be described.

FIG. 2 illustrates an arrangement structure of an integrated chip 500a according to a first embodiment of the present invention, and illustrates an arrangement structure where the resistors R1 and R2 are chip type resistors.

As shown in FIG. 2, the integrated chip 500a has a stacked structure of a base substrate 100, a dual FET chip 110, and a protection IC 120, and chip-type resistors R1 and R2. In addition, the capacitor C1 is disposed between the terminals of the chips 110 and 120 or in other regions, and the capacitor C1 is electrically connected to them by wires or wires. When connected via wires, it is also possible to connect between two terminals via multiple wires for better conductivity and faster signal transmission.

 In the base substrate 100, the first to fifth connection terminals 1, 2, 3, 4, and 5 of conductive material are spaced apart from each other at edge portions of the base substrate 100, and chip stacking is performed. The first conductive region 112 and the second conductive region 114 are disposed adjacent to the chip region and the chip region.

Some of the first to fifth connection terminals 1, 2, 3, 4, and 5 protrude to the outside of the integrated chip, so that the first to fifth external connection terminals 1, 2, 3, and 4 of the integrated chip are included. , 5). The first to fifth connection terminals 1, 2, 3, 4, and 5 are provided with first and second connection terminals 1, 2 on the left side of the base substrate 100, and a third on the right side. To fifth connection terminals 3, 4, and 5 may be arranged, and other arrangements may be possible. The first to fifth connection terminals 1, 2, 3, 4 and 5 are intended to function as external connection terminals of the integrated chip. The first to fifth connection terminals 1, 2, 3, 4, and 5 are disposed on the base substrate 100 and are represented as protruding from the base substrate 100, but this is one example. It may have a form of various types of connecting terminals generally known.

The first conductive region 112 and the second conductive region 114 may be formed on portions of the base substrate 100 excluding the chip regions and the connection regions 1, 2, 3, 4, and 5 of the connection region. Will be deployed. For example, the chip region may be disposed between the chip region and the third to fifth connection terminals 3, 4 and 5. Specifically, first and second connection terminals 1 and 2 are disposed in the left edge region of the base substrate 100, and are adjacent to the right side of the first and second connection terminals 1 and 2 to the right. A chip region is disposed, and the first conductive region 112 and the second conductive region 114 are disposed to the right adjacent to the chip region, and the right and adjacent to the first and second conductive regions 112 and 114. The third to fifth connection terminals 3, 4, and 5 may be disposed in the right edge region of the base substrate 100. Naturally, it may be possible to have various arrangements.

 The dual FET chip 110 has a structure in which the dual FET chip 110 is stacked in the chip region of the base substrate 100. The dual FET chip 110 includes a first FET and a second FET having a common drain structure, that is, two FETs, and external connection terminals include a first gate terminal G1, a first source terminal S1, and a first source terminal S1 of the first FET. The second gate terminal G2 and the second source terminal S1 of the 2FET are provided.

The protection IC 120 has a structure in which the protection IC 120 is stacked on the upper surface of the dual FET chip 110. The protection IC 120 is stacked in a region (for example, a central portion) except for a portion where external connection terminals on the dual FET chip 110 are disposed. In this case, an insulating film for insulation may be disposed between the protection IC 120 and the dual FET chip 110. Since the size of the dual FET chip 110 is generally larger than that of the protection IC 120, an arrangement structure in which the protection IC 120 is stacked on the dual FET chip 110 is adopted. In addition, since the heat is generated in the case of the dual FET chip 110, it is also possible to radiate heat through the base substrate 100, the dual FET chip 110 is disposed closest to the base substrate 100 It would be advantageous to be.

The resistor R1 is disposed on the first conductive region 112. Since the resistor R1 is a chip type, one terminal has an electrical connection structure directly connected to the first conductive region 112, and the other terminal is electrically connected to the fourth connection terminal 4 through a wire or a wire. It has a connection structure. For reference, the fourth connection terminal 4 is a connection terminal for connecting to the first node n1 on the circuit of FIG. 1.

The resistor R2 is disposed on the second conductive region 114. Since the resistor R2 is a chip type, one terminal has an electrical connection structure directly connected to the second conductive region 114, and the other terminal is electrically connected to the third connection terminal 3 through a wire or a wire. It has a connection structure. For reference, the third connection terminal 3 is a connection terminal connected to the second node n2 based on the circuit of FIG. 1.

The capacitor C1 is disposed between the first conductive region 112 and the fifth connection terminal 5. That is, the capacitor C1 is disposed to connect the first conductive region 112 and the fifth connection terminal 5. For reference, the fifth connection terminal 5 is a connection terminal for connecting to the negative terminal (or the first source terminal S1 or the VSS terminal) of the battery v1.

Here, the first conductive region 112 is electrically connected to the VDD terminal VDD of the protection IC 120 through a wire or a wire, and the second conductive region 114 is connected to the protection IC 120. It is electrically connected with V-terminal and wire or wiring. That is, the first conductive region 112 may function as a VDD region, and the second conductive region 114 may function as a V-terminal region.

The DO terminal DO is electrically connected to the first gate terminal G1 through a wire or a wire in the protection IC 120, and the CO terminal CO is connected to the second gate terminal G1 in the protection IC 120. The gate terminal G2 is electrically connected to each other through a wire or a wiring.

The first connection terminal 1 disposed on the base substrate 100 is electrically connected to the first source terminal S1 and the VSS terminal VSS of the protection IC 120 through a wire or a wire. The first external connection terminal 1 of the integrated chip 500a is configured.

The second connection terminal 2 disposed on the base substrate 100 is electrically connected to the second source terminal S2 through a wire or a wire, so that the second external connection terminal 2 of the integrated chip 500a is provided. Configure

The third connection terminal 3 disposed on the base substrate 100 is connected to the second conductive region 114 through a second resistor R2 to connect the third external connection terminal 3 of the integrated chip 500a. ) And a fourth connection terminal 4 disposed on the base substrate 100 is connected to the first conductive region 112 through a first resistor R1 to form a fourth portion of the integrated chip 500a. Configure the external connection terminal (4).

The fifth connection terminal 5 disposed on the base substrate 100 is connected to the first conductive region 112 through the first capacitor C1 to connect the fifth external connection terminal 5 of the integrated chip 500a. ).

In the first embodiment of the present invention, the arrangement form of the first to fifth connection terminals (1, 2, 3, 4, 5), the first conductive region 112, the second conductive region 114 May be modified into a form suitable for the connection of the wiring or the wire or the connection of the resistors R1 and R2 and the capacitor C1.

The protection IC 120, the dual FET chip 110, the resistors R1 and R2, the capacitor C1, and the first to fifth connection terminals 1, 2, 3, 4, and 5, respectively. The connection structure of may be variously changed and have various connection structures within the limits forming the equivalent circuit of FIG.

3 shows an arrangement structure of an integrated chip 500b according to a second embodiment of the present invention, and illustrates an arrangement structure when the resistor R1 and the resistor R2 are SMD type.

As shown in FIG. 3, the integrated chip 500b includes a base structure 100, a dual FET chip 110, and a protection IC 120 having a stacked structure, and chip type resistors R1 and R2. In addition, the capacitor C1 is disposed between the terminals of the chips 110 and 120 or in other regions, and the capacitor C1 is electrically connected to them by wires or wires. When connected via wires, it is also possible to connect between two terminals via multiple wires for better conductivity and faster signal transmission.

In the arrangement structure of the integrated chip 500b according to the second embodiment of the present invention, the arrangement of the first conductive region 112 and the second conductive region 114 is slightly different, and the resistors R1 and R2 are disposed. Except that the structure is different, it is the same as the arrangement of the integrated chip 500a according to the first embodiment of the present invention.

Therefore, only the arrangement of the first conductive region 112 and the second conductive region 114 and the arrangement structure of the resistors R1 and R2 will be described below.

Since the first conductive region 112 is connected to the fifth connection terminal 5 through a capacitor C1 and the fourth connection terminal is connected through a resistor R1, the arrangement form of the fourth conductive region 112 is fourth. And the fifth and fourth connection terminals 4 and 5 so as to be connected to the fourth and fifth connection terminals 4 and 5 to facilitate connection of the resistor R1 and the capacitor C1 of the SMD type. That is, it has a relatively wide layout structure than in the case of FIG.

In addition, since the second conductive region 114 must be connected to the third connection terminal 3 through the SMD type resistor R2, the second conductive region 114 is adjacent to the third connection terminal 3 to facilitate connection of the resistor R2. It has a structure that is disposed, and as the first conductive region 112 is enlarged, it has a relatively narrow arrangement region structure compared to the case of FIG.

The resistor R1 has an arrangement structure in which the resistor R1 is directly connected to the first conductive region 112 and the fourth connection terminal 4. That is, it has a structure that is directly connected without the need for a separate wiring or wire. The resistor R2 also has an arrangement structure in which the second conductive region 114 is directly connected to the third connection terminal 3.

Then, when packaged through a molding process, an integrated chip having five external connection terminals (or terminal pins) having an external shape is completed.

Here, the connection structure of each of the resistors R1 and R2 and the first to fifth connection terminals 1, 2, 3, 4, and 5 may have various connection structures within the limits of the equivalent circuit of FIG. 1. .

4 is a circuit diagram in which capacitors C2 and C3 are added to the battery protection circuit of FIG. 1.

As shown in FIG. 4, the capacitor C2 is added between the first node n1 and the second node n2, and the capacitor C3 is connected to the second node n2 and the first source terminal ( It has a structure added between S1) (or VSS terminal). Other than this, it has the same circuit structure as FIG.

The additional capacitors C2 and C3 do not significantly affect the characteristics of the battery protection circuit product, but are added for the user's request or stability. The capacitors C2 and C3 are for the effect of stabilizing the system by improving resistance to voltage fluctuations or external noise.

Since capacitors C2 and C3 tend to be added at the request of the user, the capacitor values may vary. In other words, the value can be changed because it is a customer option, so if one-chip is used, the value cannot be changed. However, it is advantageous to use one chip if the customer has a predetermined value or if there are many advantages that are more advantageous than changing the value.

FIG. 5 relates to an integrated chip arrangement structure according to a third embodiment of the present invention, and illustrates an integrated chip arrangement structure for the circuit of FIG. 4.

As shown in FIG. 5, the arrangement of the integrated chip 500c according to the third exemplary embodiment of the present invention is an arrangement of capacitors C2 and C3 added to the integrated chip arrangement of FIG. 2 or 3. In other words, two capacitors C2 and C3 are additionally disposed in the integrated chip. FIG. 5 illustrates an arrangement in which a resistor is an SMD type, that is, capacitors C2 and C3 are added to FIG. 3, but two capacitors C2 and C3 are additionally arranged in the arrangement of FIG. 2. May have

Since the integrated chip 500c arrangement is the same as that of FIG. 2 or 3 except for the additional arrangement of the capacitors C2 and C3, only the additional arrangement of the capacitors C2 and C3 will be described. do.

The capacitor C2 has an arrangement structure in which the third connection terminal 3 and the fourth connection terminal 4 are directly connected. The capacitor C3 has an arrangement structure in which the first connection terminal 1 and the second connection terminal 2 are directly connected to each other. Direct connection of the capacitors C2 and C3 is easy between the third connection terminal 3 and the fourth connection terminal 4 and between the first connection terminal 1 and the second connection terminal 2. The distance or the size of the area adjacent to each other can be adjusted appropriately.

The protection IC 120, the dual FET chip 110, the resistors R1 and R2, the capacitors C1, C2 and C3, and the first to fifth connection terminals 1, 2 and 3, respectively. The connection structure of 4 and 5 may be variously changed and have various connection structures within the limits of the equivalent circuit of FIG. 4.

6 is a circuit diagram of a battery protection circuit using an integrated chip (generally referred to as '500') having the arrangement of FIGS. 2, 3, and 5.

6 illustrates a case in which the capacitors C2 and C3 are not mounted in the integrated chip 500 (in the case of FIGS. 2 and 3) and the capacitors C2 and C3 are mounted in the integrated chip 500. It is shown to include all. In the integrated chip of FIGS. 2 and 3, the capacitors C2 and C3 are connected to the outside of the integrated chip 500. In the integrated chip of FIG. 5, the capacitors C2 and C3 are not connected to the outside. This is because the capacitors C2 and C3 are embedded in the integrated chip 500. Therefore, in order to display this together, in FIG. 6, the external connection structures of the capacitors C2 and C3 are indicated by dotted lines.

In the case of excluding the connection structure of the capacitors C2 and C3 in FIG. 6, the circuit of FIG. 6 becomes an equivalent circuit of the circuit of FIG. 1 and is included without excluding the connection structure of the capacitors C2 and C3 in FIG. 6. In this case, the circuit is equivalent to the circuit of FIG. 4.

As shown in FIG. 6, the integrated chip 500 having the arrangement of FIGS. 2, 3, and 5 has five external connection terminals. In this case, the first external connection terminal 1 is the first source terminal S1, the second external connection terminal 2 is the second source terminal S2, and the third external connection terminal 3 is the V- terminal V-. The fourth external connection terminal 4 may be referred to as a VDD terminal VDD, and the fifth external connection terminal 5 may be referred to as a C1 terminal C1.

Here, the VDD terminal VDD and the V-terminal V- in FIG. 6 refer to the arrangement of FIGS. 2, 3, and 5 and the same terminal as the V-terminal and the VDD terminal in FIGS. 1 and 4. It is not.

Looking at the connection structure, the first external connection terminal (1, S1) of the integrated chip 500 is connected to the negative terminal of the battery (V1) through an external wiring, the second external connection terminal (2, S2) is The second node n2 is connected to the second node through external wiring, and the third external connection terminals 3 and V− are connected to the second node n3 through external wiring. That is, the second external connection terminals 2 and S2 and the third external connection terminals 3 and V− are electrically connected to each other through external wiring. The fourth external connection terminals 4 and VDD are connected to the first node n1 through an external wiring, and the fifth external connection terminals 5 and C1 are connected to the first external connection terminals 1 and S1. ) And external wiring are connected to each other.

In this state, when the integrated chip 500 has the arrangement of FIG. 5, since the capacitors C2 and C3 are disposed therein, the integrated chip connection structure described above may configure the equivalent circuit of FIG. 4.

However, when the integrated chip 500 has the arrangement of FIG. 2 or 3, the equivalent circuit of FIG. 1 may be achieved due to the above-described connection structure.

In addition, when the capacitors C2 and C3 are connected, that is, the capacitor C2 is connected between the first node n1 and the second node n2 through an external wiring, and the capacitor C3 is connected to the first external connection. When the terminals 1 and S1 and the second external connection terminals 2 and S2 are connected through an external wiring, the equivalent circuit of FIG. 5 may be achieved.

As described above, according to the embodiments of the present invention, since a resistor or a capacitor constituting the battery protection circuit is present in the integrated chip, there is an advantage that it is resistant to external shocks and less likely to be damaged. In addition, the space occupied by the existing resistors and capacitors and the space occupied by the protection ICs and FETs can be reduced, which is advantageous for miniaturization and integration. In addition, the battery protection circuit is configured through a single integrated chip without soldering or separate connection of peripheral components (resistors, capacitors).

The foregoing description of the embodiments is merely illustrative of the present invention with reference to the drawings for a more thorough understanding of the present invention, and thus should not be construed as limiting the present invention. It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the basic principles of the present invention.

1 is a general battery protection circuit diagram.

2 shows an integrated chip arrangement structure according to a first embodiment of the present invention.

3 shows an integrated chip arrangement structure according to a second embodiment of the present invention.

4 is a battery protection circuit diagram in which capacitors C2 and C3 are added to FIG. 1.

5 shows an integrated chip arrangement structure according to a third embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of FIG. 1 or 4 using an integrated chip having the layout structure of FIGS. 2, 3, and 5.

* Description of the symbols for the main parts of the drawings *

100: base substrate 110: dual FET chip

120: protection IC n1: first node

n2: second node

Claims (4)

In the integrated chip arrangement of the battery protection circuit: A base substrate having the first to fifth connection terminals of conductive material spaced apart from each other at an edge portion thereof, and having a chip region for chip stacking and a first conductive region and a second conductive region adjacent to the chip region; A dual FET chip stacked on the chip region of the base substrate and including a first FET and a second FET having a common drain structure; Is disposed on the upper surface of the dual FET chip, and detects the over-discharge state when the battery is discharged, and control the first FET during the over-discharge, stop the discharge operation of the battery, and detects the overcharge state when the battery is charged And forming an integrated chip having a protection IC disposed therein to control the second FET in an overcharge state to stop the charging operation. The first conductive region is electrically connected to a voltage applying terminal VDD to which charge voltage and discharge voltage are applied in the protection IC through a wire or a wire, and the second conductive region detects a charge / discharge state in the protection IC. Is electrically connected to the sensing terminal (V-) and wire or wiring to The first connection terminal disposed on the base substrate is electrically connected to a source terminal of the first FET and a reference voltage terminal (VSS) of the protection IC through a wire or a wire, and a part of the first connection terminal protrudes out of the integrated chip to integrate the first terminal. Configure the first external connection terminal of the chip, The second connection terminal disposed on the base substrate is electrically connected to a source terminal of the second FET through a wire or a wire, and part of the second connection terminal protrudes out of the integrated chip to form a second external connection terminal of the integrated chip. The fifth connection terminal disposed on the base substrate is connected to the first conductive region through a first capacitor and a part of the fifth connection terminal protrudes out of the integrated chip to form a fifth external connection terminal of the integrated chip. The fourth connection terminal disposed on the base substrate is connected to the first conductive region through a first resistor, and a part of the fourth connection terminal protrudes out of the integrated chip to form a fourth external connection terminal of the integrated chip. The third connecting terminal disposed on the base substrate is connected to the second conductive region through a second resistor, and a part of the third connecting terminal protrudes out of the integrated chip to form a third external connecting terminal of the integrated chip. In the protection IC, the discharge cutoff signal output terminal DO outputting a discharge cutoff signal for turning off the first FET in an over-discharge state is electrically connected to a gate terminal of the first FET through a wire or a wire. In the protection IC, the charge blocking signal output terminal CO outputting the charge blocking signal for turning off the second FET in an overcharge state is electrically connected to a gate terminal of the second FET through a wire or a wire. The first resistor is a chip type or SMD type and connects between the fourth connector and the first conductive region, and the second resistor is a chip type or SMD type and is connected to the third connection terminal. Integrated chip arrangement structure, characterized in that having a structure for connecting between the second conductive region. delete delete The method according to claim 1, The second chip and the third capacitor is further disposed on the integrated chip, The second capacitor connects between the third connection terminal and the fourth connection terminal, and the third capacitor has an arrangement structure for connecting between the first connection terminal and the second connection terminal. Chip layout structure.

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