KR101051565B1 - Printed circuit board and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a printed circuit board and a method of manufacturing the same which can simplify the wiring process for the electrical conduction between layers of the printed circuit board.

A printed circuit board according to the present invention includes a core substrate having a first circuit pattern including a land, a bump and a metal layer formed on an insulating layer, a photosensitive insulating layer formed on the core substrate, and one surface thereof passing through the photosensitive insulating layer. The via pattern may include a via connected to the via and a circuit pattern formed on the photosensitive insulating layer.

A method of manufacturing a printed circuit board according to the present invention may include forming a substrate having a first circuit pattern including a land and a metal layer on an insulating layer, forming a photosensitive insulating layer on the substrate, and forming a via on the photosensitive insulating layer. Defining a region and a circuit pattern region, and filling a paste in the via region and the circuit pattern region to form vias connected to the circuit pattern and the land.

Photosensitive Insulation Layer, Printed Circuit Board, Wiring, Vias, Paste

Description

Printed circuit board and method for manufacturing thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board and a method of manufacturing the same, and to a printed circuit board and a method of manufacturing the same, which can simplify a wiring process for interlayer electrical conduction of a printed circuit board.

Various electronic components such as IC (Intergrated Circuit) must be properly arranged to electrically connect each other and to supply power to become electronic products that operate according to design purpose.

The basis for installing electronic components, and electrically connecting the components is called a printed circuit board (PCB) or a printed wiring board (PWB).

The printed circuit board is wired to one or both sides of a board made of various thermosetting synthetic resins, and then the semiconductor chips, integrated circuits (ICs) or electronic components are placed and fixed on the board, and the electrical wiring between them is implemented and coated with an insulator. will be.

1A to 1K are cross-sectional views of a printed circuit board manufacturing process according to the prior art.

First, the paste bump printing process and the process of forming the insulating layer so that the paste bump penetrates the insulating layer and the pressing process are performed according to a conventional technique, and the bump 110 enters the inside as shown in FIG. 1A. 120) The core substrate 100 having the first metal layer 130 coated on both surfaces thereof is manufactured.

Referring to FIG. 1B, the land 130a and the first circuit pattern 130b are formed on the core substrate 100 by performing a pattern forming process on the first metal layer 130 by a conventional photolithography process.

Referring to FIG. 1C, the PPG insulating layer 140 and the second metal layer 150 are stacked.

Referring to FIG. 1D, the first dry film 160 is laminated to define vias.

Referring to FIG. 1E, after the mask 170 is disposed to define the via region in the first dry film 160, a negative exposure process is performed to irradiate ultraviolet rays to cure the dry film of the portion to which the ultraviolet rays are irradiated. .

Referring to FIG. 1F, a developing process using a developing solution is performed to remove an uncured portion of the first dry film 160, and an etching process using the same as an etching mask and a peeling process of the first dry film 160 are performed. .

Referring to FIG. 1G, vias 180 are formed using a CO ₂ laser.

Referring to FIG. 1H, the via 180 may be filled by a fill plating process to achieve interlayer conduction.

Referring to FIG. 1I, the second dry film 190 is laminated to form a circuit.

Referring to FIG. 1J, a negative exposure process using a mask 210 is performed to define a circuit pattern region in the second dry film 190.

Referring to FIG. 1K, a developing process of the second dry film 190, an etching process of the second metal layer 150, and a peeling process of the second dry film 190 may be performed.

Conventional printed circuit board manufacturing processes include dry film lamination, dry film exposure, dry film development, metal layer and insulation layer etching, dry film peeling, laser processing to form vias, fill plating, dry film lamination, dry Through film exposure, dry film development, pattern region definition through etching the metal layer and insulating layer, and dry film peeling process.

In other words, the dry film lamination, exposure, development, etching, and peeling process must be performed twice, so that the process is complicated and the request for short lead-time for improving mass production is not satisfied. There are problems such as cost increase and environmental infringement due to the processing process and many exposure developing processes.

The present invention integrates the etching mask used for forming the insulating layer and the pattern into a photosensitive insulating layer, simplifies the patterning process for forming vias and circuit patterns, and omits the conventional dry film peeling process and laser processing process for forming vias. The present invention relates to a printed circuit board and a method of manufacturing the same, which can shorten process steps and process time.

The printed circuit board of the present invention for solving the above problems comprises a core substrate having a first circuit pattern including a land and a bump and a metal layer in an insulating layer, a photosensitive insulating layer formed on the core substrate, and the photosensitive insulating layer. It may include a via and one surface connected to the land and a circuit pattern formed on the via and the photosensitive insulating layer.

In addition, the via and the circuit pattern may further include at least one photosensitive insulating layer stacked on the photosensitive insulating layer.

In addition, the photosensitive insulating layer has a positive type in which the photopolymer polymer bond is broken by light, or a negative type in which the lighted portion is cured by causing a photopolymerization reaction.

According to another aspect of the present invention, there is provided a method of manufacturing a printed circuit board, the method comprising: forming a substrate having a first circuit pattern including a land and a metal layer on an insulating layer, forming a photosensitive insulating layer on the substrate; Defining a via region and a circuit pattern region in the photosensitive insulating layer, and filling a paste in the via region and the circuit pattern region to form vias connected to the circuit pattern and the land.

In addition, at least one photosensitive insulating layer may be further formed on the photosensitive insulating layer to form vias and circuit patterns.

In addition, the paste filling process may use a squeegee printing method.

The photosensitive insulating layer is a positive type in which photopolymer polymer bonds are broken by light, and defining a via region and a circuit pattern region in the photosensitive insulating layer comprises: forming the via region and the circuit pattern region in the positive photosensitive insulating layer. And forming the via region and the circuit pattern region by performing an exposure process to define a and a development process on the exposed positive photosensitive insulating layer.

Alternatively, the photosensitive insulating layer may be a negative type in which a lighted portion is cured by a photopolymerization reaction, and defining a via region and a circuit pattern region in the photosensitive insulating layer may include defining a via region in the first negative photosensitive insulating layer. Performing an exposure process and a developing process, and further forming a second negative photosensitive insulating layer on the first negative photosensitive insulating layer and defining a via region and a circuit region of the second negative photosensitive insulating layer. It may include the step of proceeding.

The present invention has an effect of reducing the manufacturing cost by reducing the process material by uniting the etching mask used for forming the insulating layer and the pattern with a photosensitive insulating layer.

In addition, the present invention can improve the yield by simplifying the patterning process for forming vias and circuit patterns, and by eliminating the conventional dry film peeling process and laser processing for forming vias, thereby reducing process steps and processing time.

Details of the structure of the printed circuit board according to the present invention, the manufacturing method of the printed circuit board and the effects thereof will be clearly understood by the following detailed description with reference to the drawings in which preferred embodiments of the present invention are shown.

First Example

2A to 2G are cross-sectional views illustrating a process of manufacturing a printed circuit board according to a first embodiment of the present invention, illustrating a process of manufacturing a four-layer printed circuit board.

First, a bump 14 is formed by printing a paste on the metal layer 12 using conventional B2it '(Buried bump interconnection technology) technology, and the insulating layer 16 is applied to the bump 14 to form a bump 14. The core substrate is formed so as to penetrate through the insulating layer 16, and is subjected to a crimping process so that bumps 14 enter the insulating layer 16 and metal layers 12 are formed on both sides of the insulating layer 16, as shown in FIG. 2A. Produce 10.

In this case, the bump 14 serves as electrical conduction between circuit layers in the core substrate 10, and has a smaller strength than the metal layer 12 forming the lands 12a and the first circuit pattern 12b, which will be described later, and the insulating layer. It is preferable that strength is larger than (16). This is to allow the bump 14 to penetrate the insulating layer 16 without being deformed by the insulating layer 16.

Referring to FIG. 2B, a photolithography process is performed on the metal layer 12 to form a first circuit pattern 12b including lands 12a on both surfaces of the core substrate 10.

That is, although not shown in the drawing, a photosensitive film layer is laminated on the metal layer 12, a photomask is manufactured according to the lands 12a and the first circuit pattern 12b, and the core substrate on which the photosensitive film layer is stacked ( 10) and then exposed to ultraviolet light.

When the photosensitive film layer laminated on the core substrate 10 is exposed and developed with a developer, the land 12a and the first circuit pattern 12b that are not exposed by the photomask on the core substrate 10 may be formed. The uncured photosensitive film layer is removed, and the photosensitive film layer cured by exposure remains to be an etch mask (not shown). Thereafter, an etching process using an etching mask is performed to etch portions other than the etching mask, and to remove the photosensitive film layer remaining on the core substrate 10. The first circuit pattern 12b including the lands 12a to be formed. Is formed.

Referring to FIG. 2C, the land process 12a and the first circuit pattern 12b are buried by performing a crimping process on the core substrate 10 on which the first circuit pattern 12b is formed. At this time, the crimping step is performed to improve the adhesion to the first positive photosensitive insulating layer 18 described later by having the surfaces of the lands 12a and the first circuit patterns 12b with the surfaces of the bumps 14. In this case, in the first embodiment of the present invention, the land 12a and the first circuit pattern 12b are buried, but may be omitted in some cases.

Referring to FIG. 2D, the first positive photosensitive insulating layer 18 is laminated. In this case, the first positive photosensitive insulating layer 18 is in the form of a bonding film, and serves as a general photoresist film as well as acting as a circuit pattern and an interlayer insulation.

Referring to FIG. 2E, after the mask 20 defining the second circuit pattern region is disposed on both surfaces of the first positive photosensitive insulating layer 18, an exposure process of irradiating ultraviolet rays is performed.

Referring to FIG. 2F, the mask 22 defined by the via region is disposed on both surfaces of the first positive photosensitive insulating layer 18, and then an exposure process of irradiating ultraviolet rays is performed.

At this time, the first positive photosensitive insulating layer 18 is the photopolymer polymer bond of the lighted portion is broken according to the intrinsic properties.

Referring to FIG. 2G, a developing process using a developer is performed to expose a portion of the first positive photosensitive insulating layer 18 exposed to the photopolymer polymer, that is, the second circuit pattern region 24 and the first via region 26. The first positive photosensitive insulating layer 18 of) is simultaneously removed.

Referring to FIG. 2H, the conductive paste is filled with the second circuit pattern region 24 (see FIG. 2G) and the first via region 26 (see FIG. 2G) to form the second circuit pattern 28 and the first via 30. After forming the conductive paste and the first positive photosensitive insulating layer 18 through a drying process. In this case, the filling process is any one selected from materials including metal particles such as gold (Au), silver (Ag), copper (Cu), palladium (Pd), platinum (Pt), or a combination of at least two or more selected from them. You can proceed.

The filling process may be performed through a squeegee printing process in which a pattern is opened by exposure and development using a separate mask and then filled by a printing method, or plating by electroless and / or electrolytic plating. have.

2nd Example

3A to 3E are cross-sectional views illustrating a process of manufacturing a printed circuit board according to a second embodiment of the present invention. A process of manufacturing a six-layer printed circuit board using the four-layer substrate manufactured by the above-described first embodiment will be described. The description of the four-layer substrate manufacturing process will be omitted, and the same reference numerals for the same components as in the first embodiment are applied.

Referring to FIG. 3A, the second positive photosensitive insulating layer 30 in the form of a bonding film is laminated on the four-layer substrate defined by FIG. 2H.

Referring to FIG. 3B, the mask 34 defining the third circuit pattern region is disposed, and the second positive photosensitive insulating layer 32 is exposed to the exposure process.

Referring to FIG. 3C, the mask 36 defining the second via region is disposed, and the second positive photosensitive insulating layer 32 is exposed, and the second positive photosensitive insulating layer 32 of the lighted portion is disposed. To break the photopolymerization polymer bond.

Referring to FIG. 3D, the second positive photosensitive insulating layer 32 of the exposed portion through the development process, that is, the second positive photosensitive insulating layer 32 of the third circuit pattern region 38 and the second via region 40 ( Remove 32) at the same time.

Referring to FIG. 3E, the conductive paste is filled with the third circuit pattern region 38 (see FIG. 3D) and the via region 40 (see FIG. 3D) to form the third circuit pattern 42 and the second via 44. Let's do it. In this case, the filling process may be performed by any one selected from gold (Au), silver (Ag), copper (Cu) or a combination of at least two or more selected from these.

The filling process may be performed through a squeegee printing process in which only a portion patterned by exposure and development is opened using a separate mask.

The printed circuit board manufactured as described above includes the core substrate 10 including the bumps 14, the lands 12a, and the first circuit patterns 12b, the first positive photosensitive insulating layer 18 formed on both surfaces of the core substrate, The second circuit pattern 28 and the first via 30 formed on the first positive photosensitive insulating layer 18, the second positive photosensitive insulating layer 32 and the second formed on both surfaces of the first positive photosensitive insulating layer 18. The third circuit pattern 42 and the second via 44 are formed on the positive photosensitive insulating layer 32.

The printed circuit board manufacturing process according to the first and second embodiments of the present invention as described above is used as a patterning mask for forming the first circuit pattern and the via as an insulating layer serving as an insulating material between layers and circuit patterns. The positive photosensitive insulating layer is used, and the first circuit pattern predetermined region and the via region are exposed to the positive photosensitive insulating layer, and the first circuit pattern and the via are simultaneously formed in one development process.

As a result, the material cost can be reduced by unifying the insulating film used for inter-layer circuit pattern insulation and the dry film used for patterning into a single positive photosensitive insulating layer. by omitted for the CO ₂ laser processing step for the separation process and via formation simplify the process it is possible to improve the yield.

The third Example

4A to 4J are cross-sectional views illustrating a process of manufacturing a printed circuit board according to a third embodiment of the present invention, illustrating a process of manufacturing a four-layer printed circuit board, the same as the above-described first and second embodiments. The same reference numerals apply to the components.

First, a bump 14 is formed by printing a paste on the metal layer 12 using conventional B2it '(Buried bump interconnection technology) technology, and the insulating layer 16 is applied to the bump 14 to form a bump 14. The core substrate 10 having the insulating layer penetrated therein and a compression process to enter the bump 14 into the insulating layer 16 and the metal layer 12 formed on both surfaces of the insulating layer 14 as shown in FIG. 4A. To produce.

In this case, the bump 14 serves as electrical conduction between circuit layers in the core substrate 10, and has a smaller strength than the metal layer 12 forming the lands 12a and the first circuit pattern 12b, which will be described later, and the insulating layer. It is preferable that strength is larger than (16). This is to allow the bump 14 to penetrate the insulating layer 16 without being deformed by the insulating layer 16.

Referring to FIG. 4B, a photolithography process is performed on the metal layer 12 to form a first circuit pattern 12b including lands 12a on both surfaces of the core substrate 10.

That is, although not shown in the drawing, a photosensitive film layer is laminated on the metal layer 12, a photomask is manufactured according to the lands 12a and the first circuit pattern 12b, and the core substrate on which the photosensitive film layer is stacked ( 10) and then exposed to ultraviolet light.

After the photosensitive film layer laminated on the core substrate 10 is exposed and developed with a developer, the first circuit pattern 12b including the lands 12a not exposed by the photomask on the core substrate 10 is developed. The corresponding uncured photosensitive film layer is removed, and the photosensitive film layer cured by exposure remains to be an etch mask (not shown). Subsequently, by performing an etching process using an etching mask to etch portions other than the etching mask and removing the photosensitive film layer remaining on the core substrate 10, the lands 12a and the first circuit patterns 12b to be formed are formed. Is formed.

Referring to FIG. 4C, the land 12a and the first circuit pattern 12b may be pressed into the core substrate 10 to bury the land 12a and the first circuit pattern 12b. In this case, the crimping step is performed to improve the adhesion to the first negative photosensitive insulating layer 46 to be described later by providing the land 12a, the first circuit pattern 12b, and the bump 14 surface. May be omitted.

Referring to FIG. 4D, the first negative photosensitive insulating layer 46 is laminated. In this case, the first negative photosensitive insulating layer 46 is in the form of a bonding flim (Bonding flim), and serves as a general photoresist film as well as acting as a circuit pattern and interlayer insulation.

Referring to FIG. 4E, the mask 48 defining the via region 26 is disposed on both surfaces of the first negative photosensitive insulating layer 46, and then an exposure process of irradiating ultraviolet rays is performed.

At this time, the first negative photosensitive insulating layer 46 is cured by forming a chain-shaped three-dimensional network structure in a single structure by the photopolymerization reaction of the light-received portion according to the inherent characteristics.

Referring to FIG. 4F, a developing process using a developer is performed to remove the unexposed portions of the first negative photosensitive insulating layer 46, that is, the first via region 26.

Referring to FIG. 4G, the second negative photosensitive insulating layer 50 is laminated. In this case, the second negative photosensitive insulating layer 50 is in the form of a bonding film, and serves as a general photoresist film as well as acting as a circuit pattern and interlayer insulation.

Referring to FIG. 4H, a mask 52 defining a second circuit pattern region is disposed on both surfaces of the second negative photosensitive insulating layer 50, and then an exposure process of irradiating ultraviolet rays is performed. In this case, the mask 52 is preferably blocked to prevent photocuring of the first via region 26 as well as the second circuit pattern region 24.

Referring to FIG. 4I, a developing process using a developer is performed to expose an unexposed portion of the second negative photosensitive insulating layer 50, that is, a second negative portion of the first via region 26 and the second circuit pattern region 24. The photosensitive insulating layer 50 is removed.

Referring to FIG. 4J, the conductive paste is filled in the second circuit pattern region 24 (see FIG. 4I) and the first via region 26 (see FIG. 4I) to form the second circuit pattern 28 and the first via 30. After forming the conductive paste and the first negative photosensitive insulating layer 46 through a drying process. In this case, the filling process is any one selected from materials including metal particles such as gold (Au), silver (Ag), copper (Cu), palladium (Pd), platinum (Pt), or a combination of at least two or more selected from them. You can proceed.

The filling process may be performed through a squeegee printing process in which a pattern is opened by exposure and development using a separate mask and then filled by a printing method, or plating by electroless and / or electrolytic plating. have.

Fourth Example

5A to 5G are cross-sectional views illustrating a process of manufacturing a printed circuit board according to a fourth embodiment of the present invention. A process of manufacturing a six-layer printed circuit board using the four-layer substrate manufactured by the above-described third embodiment will be described. The description of the four-layer substrate manufacturing process will be omitted, and the same reference numerals for the same components as those of the first to third embodiments are applied.

Referring to FIG. 5A, a third negative photosensitive insulating layer 54 in the form of a bonding film is laminated on the four-layer substrate defined by FIG. 4J.

Referring to FIG. 5B, the third negative photosensitive insulating layer 54 is exposed by using the mask 56 defining the second via region. In this case, the third negative photosensitive insulating layer 54 is hardened by forming a chain-shaped three-dimensional network structure in a single structure by causing a photopolymerization reaction of a portion exposed by light.

Referring to FIG. 5C, the developing process may be performed to simultaneously remove the exposed third negative photosensitive insulating layer 54, that is, the second via region 40.

Referring to FIG. 5D, the fourth negative photosensitive insulating layer 58 is laminated.

Referring to FIG. 5E, the fourth negative photosensitive insulating layer 58 of the third circuit pattern region is exposed using the mask 60 defining the third circuit pattern region. In this case, the fourth negative photosensitive insulating layer 58 is cured by forming a chain-shaped three-dimensional network structure in a single structure by causing a photopolymerization reaction of a portion exposed by light. Here, the mask 60 may be blocked to prevent photocuring of the second via region 40 as well as the third circuit pattern region 38.

Referring to FIG. 5F, the development process is performed to simultaneously remove the exposed fourth negative photosensitive insulating layer 58, that is, the third circuit pattern region 38 and the second via region 40.

Referring to FIG. 5G, the conductive paste fills the third circuit pattern region 38 and the second via region 40. In this case, the filling process may be performed by any one selected from gold (Au), silver (Ag), copper (Cu) or a combination of at least two or more selected from these.

The filling process may be performed through a squeegee printing process in which only a portion patterned by exposure and development is opened using a separate mask.

The printed circuit board manufactured as described above includes a core substrate 10 including a bump 14, a land 12a, and a first circuit pattern 12b, and a first negative photosensitive insulating layer formed on both surfaces of the core substrate 10. (46), the second negative insulating layer 50 formed on the first negative photosensitive insulating layer 46, the second circuit pattern 28 formed on the second negative photosensitive insulating layer 50, and the second negative photosensitive insulation A third negative photosensitive insulating layer 54 formed in the first via 30, the second negative photosensitive insulating layer 50 penetrating the layer 50, the first negative photosensitive insulating layer 46, and the third negative photosensitive The fourth negative photosensitive insulating layer 58 formed on the insulating layer 54, the third circuit pattern 42 formed on the fourth negative photosensitive insulating layer 58, the fourth negative photosensitive insulating layer 58 and the third negative And a second via 44 penetrating the photosensitive insulating layer 54.

The printed circuit board manufacturing process according to the third and fourth embodiments of the present invention as described above, the photosensitive for the insulating layer and the first circuit pattern that serves as an insulating material between the existing photosensitive layer and the circuit pattern of the negative photosensitive insulating layer. Instead of the film, the circuit pattern region and the via region are respectively exposed to each negative photosensitive insulating layer, and then the first circuit pattern and the via are simultaneously formed.

Accordingly, it is possible to reduce the material cost by unifying the conventionally used dry film for insulating film and patterning into a single negative photosensitive insulating layer, to shorten the development process after exposure, CO for peeling process and via formation for dry film _The yield improvement can be aimed at by simplifying a process by omitting the laser processing process.

5th Example

6 is a six-layer printed circuit board manufactured according to the fifth embodiment of the present invention, and detailed descriptions of the same processes and configurations as those of the first to fourth embodiments will be omitted.

Referring to FIG. 6, in a fifth embodiment of the present invention, bumps 14 penetrate between insulating layers 16 using a B2it '(Buried bump interconnection technology) technology, and metal layers (B) are formed on both sides of the insulating layer 16. The core substrate 10 in which 12 of FIG. 2A was formed is produced.

Then, the land 12a and the first circuit pattern 12b are buried through the patterning and pressing process for the metal layer 12.

In addition, a fifth negative photosensitive insulating layer 62 is formed on the core substrate 10, and an exposure and development process are performed to define a first via region (not shown), and then, on the fifth negative insulating layer 62. After the sixth negative insulating layer 64 is formed on the unexposed portions through exposure and development, the second circuit pattern region (not shown) and the first via region (not shown) are defined.

Subsequently, a conductive paste filling process is performed on the second circuit pattern region and the first via region to form the first circuit 28 and the first via 30.

In addition, a third positive photosensitive insulating layer 66 is formed on the upper portion of the third positive photosensitive insulating layer 66, and the exposed portions are removed through an exposure and shape process to form a third circuit pattern region (not shown) and a second via region (not shown). Define.

Subsequently, a conductive paste filling process is performed on the third circuit pattern region and the second via region to form the second circuit 42 and the second via 44.

6th Example

7 is a six-layer printed circuit board manufactured according to the sixth embodiment of the present invention, and detailed descriptions of the same processes and configurations as those of the first to fifth embodiments will be omitted.

Referring to FIG. 7, the sixth embodiment of the present invention uses the positive photosensitive insulating layer 68 to define the second circuit pattern region and the first via region, and uses the third circuit pattern region and the second via region. To define, negative photosensitive insulating layers 70 and 72 are used.

Furthermore, although the present invention is not specifically illustrated in the drawings, the negative photosensitive insulating layer and the positive photosensitive insulating layer are selectively applied in the above-described manner on the six-layer substrate, and the exposure, development, and paste filling processes are repeated, and the eight layers and More multilayer substrates can be produced.

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications, and changes within the scope without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It will be possible, but such substitutions, changes and the like should be regarded as belonging to the following claims.

1A to 1K are cross-sectional views of a printed circuit board manufacturing process according to the prior art.

2A to 2G are cross-sectional views of a printed circuit board manufacturing process according to the first embodiment of the present invention.

3A to 3E are cross-sectional views of a printed circuit board manufacturing process according to the second embodiment of the present invention.

4A to 4J are cross-sectional views of a printed circuit board manufacturing process according to the third embodiment of the present invention.

5A to 5G are cross-sectional views of a printed circuit board manufacturing process according to the fourth embodiment of the present invention.

6 is a six-layer printed circuit board manufactured according to the fifth embodiment of the present invention.

7 is a six-layer printed circuit board manufactured according to the sixth embodiment of the present invention.

Description of the Related Art [0002]

10: core substrate 12: conductive layer

12a: land 12b: first circuit pattern

14 bump 16 insulation layer

18,32,66,68: positive photosensitive insulating layer

46,50,54,58,62,64,70,72: negative photosensitive insulating layer

28, 42: circuit pattern 30, 44: via

Claims (8)

delete delete delete Preparing a core substrate; Forming a land and a first circuit pattern on the core substrate; Forming a photosensitive insulating layer on the core substrate to cover the land and the first circuit pattern; Forming the via region and the circuit pattern region in the photosensitive insulating layer using an exposure process and a developing process using a mask defining a via region and a mask defining a circuit pattern region; Simultaneously filling a conductive paste into the via region and the circuit pattern region; And And drying the conductive paste and the photosensitive insulating layer to simultaneously form vias and circuit patterns in the photosensitive insulating layer. The method of claim 4, wherein And stacking one or more photosensitive insulating layers having vias and circuit patterns formed on the photosensitive insulating layers. The method according to claim 4 or 5, Filling the conductive paste is a printed circuit board manufacturing method using a squeegee printing method. The method of claim 4, The photosensitive insulating layer is a positive type in which the photopolymer polymer bond is broken by light, Forming the via region and the circuit pattern region in the photosensitive insulating layer; Performing an exposure process to define the via region and the circuit pattern region on the positive photosensitive insulating layer; And forming the via region and the circuit pattern region by performing a developing process on the exposed positive photosensitive insulating layer. The method of claim 4, wherein The photosensitive insulating layer is a negative type that the lighted portion is cured by the photopolymerization reaction, Forming the via region and the circuit pattern region in the photosensitive insulating layer; Performing an exposure process and a developing process defining a via region in the first negative photosensitive insulating layer; Further forming a second negative photosensitive insulating layer on the first negative photosensitive insulating layer; And performing an exposure process and a development process defining a via region and a circuit region of the second negative photosensitive insulating layer.

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