KR101046252B1 - Multilayer Chip Package Using TSV - Google Patents

Abstract

The present invention relates to a stacked chip package using a TSV, and more particularly, to maximize the heat dissipation effect of a semiconductor package in which a plurality of chips are stacked using a through silicon via (TSV), and a chip by a through silicon via. The present invention relates to a multilayer chip package using a TSV to reduce the risk of yield reduction.

That is, the present invention includes heat dissipation means in a package in which chips having through silicon vias (TSV) are stacked, and heat dissipation means in direct or indirect contact with each stacked chip, so that external emission of heat generated from the chip is provided. To provide a laminated chip semiconductor package using a TSV having a heat dissipation means that can maximize the, and can accurately determine the yield of the chip.

Semiconductor Package, TSV, Heat Dissipation, Rewiring, Heat Spreader, Heat Slug, Electromagnetic Shielding

Description

Stacked Chip Package Using TSV {Stack Chip Package using TSV}

The present invention relates to a stacked chip package using a TSV, and more particularly, to maximize the heat dissipation effect of a semiconductor package in which a plurality of chips are stacked using a through silicon via (TSV), and a chip by a through silicon via. The present invention relates to a multilayer chip package using a TSV to reduce the risk of yield reduction.

Conventional stacked chip package is manufactured in a structure in which a plurality of chips are attached to a chip attaching region of a substrate, and a bonding pad of each chip and a conductive circuit pattern of the substrate are electrically connected to each other so that wire bonding is possible. This is necessary, and also requires a circuit pattern area of a substrate to which wires are connected, resulting in an increase in the size of the semiconductor package.

In view of this, a structure using through silicon vias (TSV) has been proposed as an example of a stack package. After forming through silicon vias in each chip at the wafer stage, the through silicon vias are perpendicular to each other. As a structure to allow physical and electrical connection between the chips, the conventional manufacturing process is briefly described as follows.

7 is a cross-sectional view illustrating a process of forming a conventional through silicon via.

First, a vertical hole 702 is formed in a portion adjacent to the bonding pad of each chip 700 at the wafer level, and an insulating film (not shown) is formed on the surface of the vertical hole 702.

In the state in which the seed metal film is formed on the insulating layer, a through silicon via 706 is formed by burying an electrolytic material, that is, a conductive metal 704 in the vertical hole 702 through an electroplating process.

Next, the backside of the wafer is back ground to expose the conductive metal 704 embedded in the through silicon via 706.

Subsequently, after sawing and separating the wafer into individual chips, at least two or more chips are vertically stacked on the substrate so as to be electrically signal exchanged through conductive metal of through silicon vias, and then molding the top surface of the substrate including the stacked chips, The solder package is mounted on the bottom of the board to complete the stack package.

However, a package in which a plurality of chips stacked with through silicon vias are stacked as described above does not have a separate heat dissipation means, and thus does not properly dissipate heat generated from the chips, and heat dissipation is not properly performed. As a result, there was a problem that the chip performance is reduced.

In addition, when a defect occurs in any one of the plurality of through-silicon vias formed in the chip, it is difficult to determine the defect, resulting in a decrease in chip yield.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and includes heat dissipation means in a package in which chips having through silicon vias (TSVs) are stacked, and heat dissipation means in direct or indirect contact with each stacked chip. Accordingly, an object of the present invention is to provide a stacked chip semiconductor package using TSV having heat dissipation means capable of maximizing external emission of heat generated from a chip and accurately determining chip yield.

One embodiment of the present invention for achieving the above object is a substrate; A plurality of active chips stacked so as to be electrically exchanged over a portion of the substrate; A dummy chip having through silicon vias stacked over the remaining area of the substrate; A first rewiring formed in a predetermined arrangement over an inactive surface, which is an upper surface of an active chip except for the top and bottom chips among the active chips; A conductive pad connected between a bonding pad formed on an active surface, which is a bottom surface of the active chip, and a first rearrangement of an active chip stacked below the active pad; A second rewiring formed integrally with the first rewiring and formed in a predetermined arrangement on an upper surface of the dummy chip positioned on the same line as the active chip on which the first rewiring is formed, and electrically connected to the through silicon vias of the dummy chip; ; A thermally conductive molding resin molded on the substrate to encapsulate the active chips and the dummy chips; It provides a stacked chip package using a TSV, characterized in that configured to include.

In a preferred embodiment, the through silicon vias are further formed in each of the active chips, and the through silicon vias are connected to the conductive bumps, so that electrical signals can be exchanged between the active chips.

Another embodiment of the present invention for achieving the above object is a substrate; A plurality of semiconductor chips having through silicon vias stacked on the substrate so as to be electrically exchanged thereon; A heat spreader inserted between the stacked chips and having through holes formed at positions where through silicon vias of each chip are formed; A heat dissipation plate which is vertically erected on the substrate and integrally connected to all four edges of each heat spreader; It provides a stacked chip package using a TSV, characterized in that configured to include.

In another preferred embodiment, the outer surface of the heat dissipation plate is characterized in that the Peltier element is further attached.

Another embodiment of the present invention for achieving the above object is a substrate; A plurality of semiconductor chips having through silicon vias stacked on the substrate so as to be electrically exchanged thereon; A silicon interposer inserted between the stacked chips and having through holes formed at positions where through silicon vias of each chip are formed; A heat slug having a plurality of legs which are stacked and attached to an upper surface of the uppermost chip among the stacked chips, and the lower surface of which is seated and supported on an upper surface of an edge of an interposer; It provides a stacked chip package using a TSV, characterized in that configured to include.

In another preferred embodiment, some of the legs of the heat slug pass through the silicon interposer and are grounded to a conductive pattern on the substrate.

Another embodiment of the present invention for achieving the above object is a substrate; A plurality of semiconductor chips having through silicon vias stacked on the substrate so as to be electrically exchanged thereon; Heat dissipation means arranged between or around the stacked chips; It provides a stacked chip package using a TSV, characterized in that configured to include.

One embodiment of the heat dissipation means is inserted between the stacked chips, the horizontal plate having a through-hole formed in the position where the through-silicon via of each chip is formed, and the bottom of the substrate is integrally connected to the edge of each horizontal plate A heat spreader comprising a vertical plate connected to the conductive pattern on the ground; A heat sink attached to the outer surface of the uppermost horizontal plate of the heat spreader and the outer surface of the vertical plate; .

Another embodiment of the heat dissipation means includes a thermally conductive refrigerant pipe attached to the side of the stacked chips and the uppermost chip top surface, the refrigerant is filled; A heat sink attached over the top and side surfaces of the thermally conductive refrigerant pipe; .

In particular, the thermally conductive refrigerant pipe is formed with an injection pipe and a discharge pipe for filling and circulating the refrigerant, a circulating pump for pumping the refrigerant in the refrigerant tank is connected to the injection pipe, the discharge pipe is connected to the refrigerant tank so that the refrigerant is returned and stored It features.

Through the above problem solving means, the present invention provides the following effects.

According to the present invention, the through silicon vias (TSV) are electrically connected to each other by using conductive bumps, etc., and a plurality of chips are stacked, and heat dissipating means including a heat spreader, a heat conductive material, a heat sink, and the like are combined in various forms. By directly or indirectly contacting each chip, it is possible to maximize the release of heat generated in each stacked chip.

In addition, through-through vias are not formed in the active chip, but through-vias are formed in a separate dummy chip and connected to the active chip by rewiring, thereby improving reliability and yield of the active-chip.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the multilayer chip package structure using TSV according to the first embodiment of the present invention will be described.

1A and 1B are cross-sectional views illustrating a stacked chip package using a TSV according to a first embodiment of the present invention.

According to the first embodiment of the present invention, an active chip without through silicon vias and a dummy chip with through silicon vias for electrical signal exchange of the active chip are stacked together on a substrate.

That is, a plurality of active chips 102a to 102n are stacked to exchange electrical signals over a portion of the substrate 100, and the bottom chip 102a is flipped between the conductive patterns 101 of the substrate 100. The chip 120 is electrically connected to each other, and the active chips 102b to 102n stacked thereon electrically connect the conductive bumps 110 to each other.

At this time, the first cultivation is achieved by forming a predetermined circuit pattern on the upper surface of the remaining active chips 102a to 102c except for the uppermost 102n of the active chips 102a to 102n, that is, the inactive surface without the bonding pad for input / output. Line 106 is formed.

The first redistribution line 106 (RDL: ReDistribution Line) may be formed by a conventional photo-lithography method or an electroplating method.

Therefore, the bonding pads formed on the active surfaces, which are the bottom surfaces of the active chips 102b to 102n, and the corresponding first rewiring 106 of the active chips 102a to 102c stacked below the conductive bumps 110. Are electrically connected to each other.

According to the first embodiment of the present invention, in addition to the active chips 102a to 102n, the through silicon vias 103 are formed on the substrate 100 to serve as an electrical signal path between the active chips 102a to 102n. Chips 104a to 104n are stacked.

In more detail, each of the dummy chips 104a to 104n is stacked one less than the active chips 102a to 102n, and each of the dummy chips 104a to 104n corresponds to the active chips 102a to 102c and is the same. It is located on the horizon.

At this time, the second rewiring 108 which is integrally connected to the first rewiring 106 of each of the active chips 102a-102c is formed on the upper surface of each of the dummy chips 104a-104n by the same forming method. The second rewiring is electrically connected to the through silicon vias 103 of the dummy chips 104a to 104n.

In addition, a thermally conductive molding resin 112 is molded on the substrate 100, and the active chips 102a to 102n and the dummy chips 104a to 104n are completely encapsulated by the molding resin 112. Alternatively, side surfaces of the active chips 102a to 102n and the dummy chips 104a to 104n are exposed and encapsulated to facilitate heat dissipation.

Accordingly, as the through silicon vias are not formed in the active chips 102a to 102n, yield loss such as a defect such as an electrical short caused by forming a plurality of through silicon vias may be reduced, and thus the active chip may be reduced. Heat generated from the 102a to 102n may be released to the outside through the thermally conductive molding resin 112, and may be externally provided through the conductive molding resin 112 through the redistribution 106 and 108 and the dummy chips 104a to 104n. Can be released.

Meanwhile, the through silicon vias 114 are further formed in the active chips 102a to 102c, and the through silicon vias 114 are connected to each other by the conductive bumps 110 to electrically connect the through silicon vias 114 to the active chips 102a to 102n. The signal exchange is performed, and the bottom active chip 102a may be directly connected to the substrate 100 using the flip chip 120.

Accordingly, the input / output path of each of the active chips 102a to 102n passes through the first rewiring 106, the second rewiring 108 of the dummy chips 104a through 104n, and the through silicon vias 103. In addition, through the through silicon via 114 and the conductive bump 110 of each active chip (102a ~ 102n) to be made of the substrate 100, by increasing the number of input and output terminals, the desired electrical signal transmission and multi-pinning Can be realized.

Herein, the multilayer chip package structure using TSV according to the second embodiment of the present invention will be described.

2A to 2C are cross-sectional views illustrating a stacked chip package using a TSV according to a second embodiment of the present invention.

The package according to the second embodiment of the present invention is a laminated package using TSV, and has a feature of maximizing a heat dissipation effect.

A plurality of semiconductor chips 202a to 202n having through silicon vias 204 stacked thereon are stacked on the substrate 200, and a plurality of through holes 206 are formed between the chips 202a to 202n. A heat spreader 208, such as a copper foil with a copper foil, is inserted.

First, the bottom chip 202a is electrically connected to and stacked on the conductive pattern 201 on the substrate 200 via the conductive flip chip 230, and then the heat spreader 208 is disposed on the bottom chip 202a. Are attached to each other, a plurality of chips 202a to 202n are heat spreaders through the same repetitive process in which the bottom chip 202a and the conductive bump 220 are connected to each other, and the chips 202b are stacked and attached. Laminated with 208 therebetween.

In other words, a plurality of chips 202a to 202n sandwich the heat spreader 208 through the same stacked repetition process in which the through silicon vias 204 of the chips 202a to 202n are connected to the conductive bumps 220. And are electrically connected to each other and stacked.

In particular, the conductive bumps 220, which are electrical connection means between the respective chips 202a-202n, are positioned in the through holes 206 of the heat spreader 208, thereby contacting the heat spreader 208 with each conductive bump 220. Do not cause interference.

At this time, the heat spreader 208 arranged between the chips 202a to 202n is adopted to have a larger area than the chips 202a to 202n, so that the four sides of the heat spreaders 208 protrude from the edges. do.

Thus, the four edges of each of the heat spreader 208 is integrally connected to the heat radiation plate 210 in the form of a vertical plate standing vertically on the substrate 200.

Therefore, heat generated in each chip 202a to 202n can be discharged to the outside through the heat spreader 208, and heat generated in the chip through the heat dissipation plate 210 having a larger heat dissipation area is easier. Can be released to the outside.

Meanwhile, according to the second embodiment of the present invention, the Peltier element 212 is attached to the outer surface of the heat dissipation plate 210 in order to maximize the effect of dissipating heat generated from the chip.

That is, the Peltier element 212 is a thermoelectric cooler (TEC: Thermoelectric Cooler) using the Peltier effect, the endothermic side of the Peltier element 212 is in contact with the heat dissipation plate 210, the heat generated by the Peltier element 212 As the side is directed outward, the heat transferred to the heat dissipation plate 210 is taken away by the heat absorbing side of the Peltier element 212, thereby maximizing the effect of dissipating heat generated from the chip.

Herein, the stacked chip package structure using TSV according to the third embodiment of the present invention will be described.

3A and 3B are cross-sectional views illustrating a stacked chip package using a TSV according to a third embodiment of the present invention.

The package according to the third embodiment of the present invention is characterized by a structure in which the heat dissipation effect is maximized by using the silicon interposer 308 and the heat slug 310.

First, a plurality of semiconductor chips 302a to 302n having through silicon vias 304 formed thereon are stacked on the substrate 300 so as to exchange electrical signals, and one or more of the chips 302a to 302n are stacked. A silicon interposer 308 having a plurality of through holes 306 is inserted therebetween.

That is, after the through silicon via 304 of the bottom chip 302a is electrically connected and stacked through the conductive flip chip 330 to the conductive pattern 301 on the substrate 300, the bottom chip 302a is stacked. ) Another chip 302b is stacked on each other, and the through silicon vias 304 are electrically connected to each other via the conductive bumps 320. Thus, the through silicon vias 304 of the respective chips 302a to 302n are electrically conductive. Through the same stacking repetition process of connecting the bumps 320, the plurality of chips 302a to 302n are electrically connected to each other and stacked.

In this case, a silicon interposer 308 having a plurality of through holes 306 is inserted between one or more of the chips 302a to 302n, and the silicon interposer 308 is configured to each chip 302a. It is adopted to have a larger area than ˜302n), and its edge protrudes from each chip 302a to 302n.

In particular, the heat slug 310 is stacked and attached to the top surface of the top chip 302n among the stacked chips 302a to 302n, and the bottom surface of the heat slug 310 is disposed on the top surface of the edge of the interposer 308. A plurality of legs 312 that are seated and supported are integrally formed.

In this case, the conductive bump 320, which is an electrical connection means between each chip 302a ˜ 302n, is positioned in the through hole 306 of the silicon interposer 308 so that the silicon interposer 308 and each conductive bump 320 are formed. Avoid contact interference between the liver.

Accordingly, heat generated in the chips 302a to 302n is easily discharged to the outside through the heat slug 310 via the silicon interposer 308.

Meanwhile, according to the third embodiment of the present invention, some of the legs 312 of the heat slug 310 extend downward through the silicon interposer 308 and at the same time, the conductive pattern 301 on the substrate 300. By being grounded to the ground, heat generated from the chips 302a to 302n is discharged to the outside through the heat slug 310 via the silicon interposer 308 and at the same time, the conductive pattern for grounding the substrate 300 It is also emitted to 301, it is possible to obtain a greater heat dissipation effect generated in the chip.

Herein, the stacked chip package structure using TSV according to the fourth embodiment of the present invention will be described.

4A to 4C are cross-sectional views illustrating a stacked chip package using a TSV according to a fourth embodiment of the present invention.

The stacked chip package using the TSV according to the fourth embodiment of the present invention is characterized in that a heat radiating means using a refrigerant and a heat sink or a heat radiating means using a heat spreader and a heat sink is added.

A plurality of semiconductor chips 402a to 402n having through silicon vias 404 formed on the substrate 400 are stacked to exchange electrical signals.

That is, the through silicon vias 404 of the bottommost chip 402a are electrically connected and stacked through the conductive flip chip 440 to the conductive pattern 401 on the substrate 400, and then the bottommost chip 402a is stacked. ) Another chip 402b is stacked on the conductive silicon vias 404, and the through silicon vias 404 are electrically connected to each other via the conductive bumps 430. Through the same stacking repetition process of connecting the bumps 430, the plurality of chips 402a to 402n are electrically connected to each other and stacked.

At this time, the heat dissipation means 410 is mounted between or around the stacked chips 402a to 402n.

As an embodiment of the heat dissipation means 410 according to the fourth embodiment of the present invention, a heat spreader 416 consisting of a horizontal plate 412 and a vertical plate 414 is adopted.

The horizontal plate 412 of the heat spreader 416 is inserted between the stacked chips 402a to 402n, and a plurality of conductive bumps 430 connecting the through silicon vias 404 of each chip are embedded. As a structure in which a through hole is formed, an area larger than the chips 402a to 402n is adopted.

In addition, the vertical plate 414 of the heat spreader 416 is integrally connected to the edge of the horizontal plate 412 protruding from each chip (402a ~ 402n), the lower end of the conductive pattern 401 on the substrate 400 Is connected to ground.

Further, a heat sink 418 having a plurality of heat sink fins is further attached to the outer surface of the uppermost horizontal plate 412 of the heat spreader 416 and the outer surface of the vertical plate 414.

Therefore, heat generated in each chip 402a to 402n can be discharged to the outside through the horizontal plate 412 and the vertical plate 414 of the heat spreader 416, and also the heat transferred to the heat spreader 416. The heat sink 418 can be more easily released.

Another embodiment of the heat dissipation means 410 according to the fourth embodiment of the present invention is a thermally conductive refrigerant pipe 420 in which refrigerant is charged over the side surfaces of the stacked chips 402a to 402n and the uppermost chip top surface. And a heat dissipation plate 422 having a plurality of heat dissipation fins over the top and side surfaces of the heat conductive refrigerant pipe 420.

Optionally, the heat conductive refrigerant pipe 420 may be adopted as a hermetic type, and a gel type refrigerant may be filled therein to absorb and release heat generated from the chip.

Alternatively, the thermally conductive refrigerant pipe 420 is adopted as the injection pipe 424 and the discharge pipe 425 formed for filling and circulating the refrigerant, and the injection pipe 424 is a circulation for pumping the refrigerant in the refrigerant tank 426. The pump 428 is connected, and the discharge pipe 425 is connected to the refrigerant tank 426, the refrigerant is returned and stored.

Accordingly, the refrigerant in the refrigerant tank 426 flows into the injection pipe 424 of the thermally conductive refrigerant pipe 420 by driving the circulation pump 428, and then passes through the discharge pipe 425 to the refrigerant tank 426. By circulating, the circulating refrigerant absorbs heat generated from the chip to be discharged to the outside, and the heat absorbed by the thermally conductive refrigerant pipe 420 causes the heat sink 422 in close contact with the thermally conductive refrigerant pipe 420. Through it can be more easily released to the outside.

Herein, the electromagnetic shielding structure and the chip stacking structure applicable to the first to fourth embodiments of the present invention described above are as follows.

5 and 6 are cross-sectional views showing an electromagnetic shielding structure and a chip stacking structure applicable to each embodiment of the present invention.

As shown in FIG. 5, the packages of the first to fourth embodiments described above are stacked and electrically connected through TSVs, ie, through silicon vias.

Once again, the chips 502a to 502n having a plurality of through silicon vias 504 are stacked on the substrate 500, but the bottom of the chip 502a is disposed on the conductive pattern 501 on the substrate 500. After the through silicon vias 504 are electrically connected and stacked through the conductive flip chip 508, another chip 502b is stacked on the bottom chip 502a, and the through silicon vias 504 are conductive. The plurality of chips 502a ˜ may be electrically connected through the bumps 506 through the same stacked repetition process in which the through silicon vias 504 of the chips 502a ˜ 502n are connected to the conductive bumps 506. 502n are electrically connected to each other and stacked.

Via-hole shielding means in the form of a via hole may be added to the semiconductor packages of the first to fourth embodiments having the chip stack structure as described above, and the through silicon via is formed as shown in FIG. 5. After processing the via hole 510 for shielding the electromagnetic wave in a non-area region, an electromagnetic shielding material is filled in the inside thereof, and the grounding is connected to the conductive pattern 501 of the substrate 500. Electromagnetic waves from the electronic device and the like mounted on the motherboard can be grounded and removed.

As shown in the semiconductor package of the first to fourth embodiments described above, the package shown in FIG. 6 is a TSV, that is, a chip having different sizes and functions as a package that is electrically connected and stacked through a through silicon via. Lamination can be through through silicon vias.

First, a plurality of through silicon vias 610 are formed, and a first chip 602 having a recess 608 formed thereon is electrically connected to the substrate 600 using a flip chip 616 to be stacked. Let's do it.

Next, the second chip 604 having the through silicon via 610 is attached to the mounting groove 608 of the first chip 602, and the through silicon vias 610 are connected to each other via the conductive bumps 614. Connect

In this case, an insulating material 618 is filled between the inner wall of the mounting groove 608 of the first chip 602 and the outer surface of the second chip 602, and the first chip 602 and the first chip 602 are formed on the same horizontal line. A redistribution 612 of a predetermined circuit array is integrally connected to each other over the upper surface of the two chips 604.

Subsequently, a larger third chip 606 having a through silicon via 610 is stacked over the first chip 602 and the second chip 604. Between the through silicon vias 610 of the third chip 606 and the through silicon vias 610 of the third chip 606, and the redistribution 612 of the second chip 604 and the through silicon vias 610 of the third chip 606. The simple electrically conductive bumps 614 are electrically connected and stacked.

In this way, in addition to the heat dissipation means, electromagnetic wave shielding means in the form of via holes is added to the semiconductor packages of the first to fourth embodiments, and the electromagnetic waves from the external devices can be grounded and removed, and they have different sizes and functions. Multiple chips can be stacked in various forms using through silicon vias.

1A and 1B are cross-sectional views illustrating a stacked chip package using a TSV according to a first embodiment of the present invention;

2A to 2C are cross-sectional views illustrating a stacked chip package using a TSV according to a second embodiment of the present invention;

3A and 3B are cross-sectional views illustrating a stacked chip package using a TSV according to a third embodiment of the present invention;

4A and 4C are cross-sectional views illustrating a stacked chip package using a TSV according to a fourth embodiment of the present invention;

5 and 6 are cross-sectional views showing an electromagnetic shielding structure and a chip stacking structure applicable to each embodiment of the present invention;

7 is a cross-sectional view illustrating a chip on which a through silicon via is formed in the related art and a stacked structure thereof;

<Explanation of symbols for the main parts of the drawings>

100: substrate 101: conductive pattern

102a to 102n: Active chip 103: Through silicon via

104a ~ 104n: Dummy chip 106: First rewiring

108: second wiring 110: conductive bump

112: thermally conductive molding resin 114: through silicon via

120: flip chip

200: substrate 201: conductive pattern

202a to 202n: Semiconductor chip 204: Through silicon via

206: through hole 208: heat spreader

210: heat dissipation plate 212: Peltier element

220: conductive bump 230: flip chip

300: substrate 301: conductive pattern

302a to 302n: semiconductor chip 304: through silicon via

306: through hole 308: silicon interposer

310: hit slug 312: legs

320: conductive bump 330: flip chip

400: substrate 401: conductive pattern

402a to 402n: semiconductor chip 404: through silicon via

410: heat dissipation means 412: horizontal plate

414 vertical plate 416 heat spreader

418: heat sink 420: thermal conductive refrigerant tube

422: heat sink 424: injection tube

425: discharge pipe 426: refrigerant tank

428: circulation pump 430: conductive bump

440 flip chip

500: substrate 501: conductive pattern

502a to 502n: semiconductor chip 504: through silicon via

506: conductive bump 508: flip chip

510: via hole for electromagnetic shielding

600: substrate 601: conductive pattern

602: first chip 604: second chip

606: third chip 608: seating groove

610: through silicon via 612: redistribution

614: conductive bump 616: flip chip

618: Insulation Material

Claims (10)

A substrate 100; A plurality of active chips (102a to 102n) stacked so as to be electrically exchanged over a portion of the substrate (100); Dummy chips 104a to 104n having through silicon vias 103 stacked over the remaining area of the substrate 100; A first rewiring 106 formed in a predetermined arrangement over an inactive surface that is an upper surface of the remaining active chips 102a to 102c except for the uppermost 102n of the active chips 102a to 102n; A conductive pad 110 connected between a bonding pad formed on an active surface, which is a bottom surface of the active chips 102b to 102n, and a first rewiring 106 of the active chips 102a to 102c stacked below; It is formed in a predetermined arrangement on the upper surface of the dummy chip (104a ~ 104n) co-connected with the first wiring (106) integrally located on the same line as the active chip (102b ~ 102n) formed on the first wiring (106) A second rewiring 108 electrically connected to the through silicon vias 103 of the dummy chips 104a to 104n; A thermally conductive molding resin 112 molded on the substrate 100 to encapsulate the active chips 102a to 102n and the dummy chips 104a to 104n; Stacked chip package using a TSV, characterized in that configured to include. The method according to claim 1, Further through silicon vias 114 are formed in each of the active chips 102a to 102c, and the through silicon vias 114 are connected to the conductive bumps 110 to exchange electrical signals between the active chips 102a to 102n. Multilayer chip package using a TSV, characterized in that made. delete delete delete delete delete delete delete delete

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