KR101041519B1 - Phase control device, phase control print plate and control method - Google Patents

Abstract

This invention makes it a subject to control the phase of an output signal minutely.

In the first delay line, when the input of the input signal is received, a delay amount is added to the phase of the input signal by each of the delayers that add a delay amount to the phase of the signal, and outputs a delay signal for each delay period. In the DLL circuit, when the second delay line receives an input of an external signal whose frequency can be switched externally, a delay amount is added to the phase of the external signal by each of the delayers, and the plurality of delays of the second delay line are added. A phase difference between the delayed signal delayed by all the phases and an external signal whose delay amount is not added to the second delay line, and a voltage for synchronizing the delayed signal compared by the phase comparator to the external signal. The control voltage generated from the phase difference output by this is input to each of the plurality of delays of the first delay line and the second delay line.

Description

PHASE CONTROL DEVICE, PHASE CONTROL PRINT PLATE AND CONTROL METHOD}

The present invention relates to a phase control device, a phase control printed plate, and a control method.

Conventionally, various methods are known regarding the method of obtaining the output signal which adjusted the phase of a signal. For example, a DLL (Delay Locked Loop) is known as a method of obtaining an output signal in which the phase of a signal is adjusted. In a DLL, for example, a delayer that adds a delay amount to a phase is used. In the DLL, the delayer adds a delay amount to the phase of the input signal, and sets the delayed signal whose phase is delayed as compared with the phase of the input signal as the output signal.

In addition, Patent Documents 1 to 3 disclose a method of correcting a phase shift between an input signal and a clock signal.

[Patent Document 1] Japanese Patent Application Laid-Open No. 2007-293911

[Patent Document 2] Japanese Patent Application Laid-Open No. 11-7768

[Patent Document 3] Japanese Unexamined Patent Application Publication No. 2004-15689

However, the above-described prior art has a problem that the phase of the output signal cannot be finely adjusted.

For example, in conventional techniques, each of the delayers adds a delay amount above a predetermined minimum value and below a predetermined maximum value with respect to the phase of the input signal. Here, the predetermined minimum value is the propagation delay time of the delay itself, and represents the phase resolution between the delays. For this reason, in the conventional method, it is not possible to perform the delay amount added with respect to the phase of an input signal below a predetermined minimum value, and the phase of an output signal cannot be finely adjusted to below a predetermined minimum value. Further, Patent Documents 1 to 3 do not disclose a method for finely adjusting the phase of an output signal.

The disclosed technique is made in view of the above, and an object thereof is to provide a phase control device, a phase control printed plate, and a control method capable of finely adjusting the phase of an output signal.

When the phase control apparatus disclosed in this application receives an input of an input signal, it adds a delay amount with respect to the phase of the input signal by each of the delayers which add a delay amount with respect to the phase of the signal, and outputs a delay signal for each delay unit. And a first delay line and a DLL circuit. The DLL circuit further includes a second delay line which adds a delay amount to the phase of the external signal by each of the delayers upon receiving an input of an external signal whose frequency can be switched externally. The DLL circuit further includes a phase comparator for comparing the phase difference between the delayed signal delayed by all of the plurality of delayers of the second delay line and the external signal to which the delay amount is not added in the second delay line. The DLL circuit is a voltage for synchronizing a delay signal compared by the phase comparator to the external signal, and the control voltage generated from the phase difference output by the phase comparator is used for the first delay line and the second. And a delay control circuit for inputting to each of the plurality of delays in the delay line.

According to the phase control apparatus disclosed by this application, the effect of minutely controlling the phase of an output signal is exhibited.

EMBODIMENT OF THE INVENTION Hereinafter, with reference to an accompanying drawing, the Example of a phase control apparatus, a phase control printed board, and a control method which concerns on this invention is described in detail. In addition, below, the outline | summary of the structure of the phase control apparatus which concerns on Example 1, the structure of LSI, the flow of a process, and the effect of the phase control apparatus which concerns on Example 1 are explained in order, and after that to another Example Explain.

Example 1

[Summary of Configuration of Phase Control Device According to Example 1]

First, the outline | summary of the structure of the phase control apparatus which concerns on Example 1 is demonstrated briefly using FIG. In addition, below, the outline | summary of the phase control apparatus which concerns on Example 1 is demonstrated briefly first using FIG. 1, and the structure of the phase control apparatus which concerns on Example 1 is demonstrated after that. 1 is a figure for showing an example of a structure of the phase control apparatus which concerns on Example 1. FIG.

As shown in FIG. 1, the phase control device according to the first embodiment includes a voltage controlled delay line (for an input signal) 100 and a DLL (Delay Locked Loop) circuit 200. . In addition, the phase control device according to the first embodiment includes a clock generator (“CKG” clock generator) 300.

Here, the voltage controlled delay line (for input signals) 100 adds a delay amount (delay time) to the phase of the input signal. Specifically, each of the delayers (for input signals) 110 provided in the voltage controlled delay line (for input signals) 100 adds a delay amount to the input signal. And as shown to "OUT1"-"OUTn" of FIG. 1, the voltage-controlled delay line (for input signals) 100 is a delay signal which is an input signal with a delay amount added by each of the delayers (for input signals) 110. As shown in FIG. Outputs

The clock generator 300 also outputs an external signal to the DLL circuit 200. The DLL circuit 200 corresponds to one cycle by each of the delayers (for DLL) 220 provided in the DLL circuit 200 with respect to the phase of the external signal output from the clock generator 300. Add the delay amount (delay time).

Here, as described below, each of the delayers (for input signals) 110 and each of the delayers (for DLLs) 220 provided in the DLL circuit 200 add the same amount of delay to the signal. . Specifically, each of the delayers (for input signals) 110 adds a delay amount equal to the delay amount that each of the delayers (for DLLs) 220 adds to the external signal with respect to the input signal.

For example, when a user using the phase control device according to the first embodiment switches the frequency of an external signal output from the clock generator 300, and the length corresponding to one period is changed, a delay (for DLL) The amount of delay each 220 adds to the external signal also changes. In addition, when the delay amount added to each of the delay signals (for the DLL) 220 to the external signal is changed, the delay amount added to each of the delay signals (for the input signal) 110 to the input signal is also reduced. 220) the same as each.

For this reason, in the phase control apparatus according to the first embodiment, as described below, by switching the frequency of an external signal separate from the input signal, each of the delay units (for input signals) 110 adds to the input signals. Fine tune the delay. Thereby, the phase control apparatus which concerns on Example 1 can perform fine phase control of the output signal which was not possible conventionally.

[Configuration of Phase Control Device According to Example 1]

Next, the structure of the phase control apparatus which concerns on Example 1 is demonstrated. Below, an example of the structure of the voltage controlled delay line (for input signals) 100 among the structure of the phase control apparatus which concerns on Example 1 is demonstrated first, and the phase control apparatus which concerns on Example 1 is equipped after that An example of the configuration of the DLL circuit 200 will be described. An example of the configuration of the clock generator 300 included in the phase control device according to the first embodiment will be described. The voltage controlled delay line (for input signals) 100 is also referred to as a first delay line.

[Voltage Controlled Delay Line (For Input Signal)]

First, an example of the configuration of the voltage controlled delay line (for input signals) 100 will be described with reference to FIG. 1. As shown in FIG. 1, the voltage controlled delay line (for input signals) 100 has a plurality of delayers (for input signals) 110 connected in series, and is connected to the DLL circuit 200. Specifically, in the voltage controlled delay line (for input signals) 100, the delayer (for input signals) 110 is connected to the DLL circuit 200 through the capacitor 250 included in the DLL circuit 200. do.

In addition, the voltage controlled delay line (for input signals) 100 receives an input signal, adds a delay amount (delay time) to the phase of the received input signal, and outputs a delay signal. Specifically, each of the delayers (for input signals) 110 provided in the voltage controlled delay line (for input signals) 100 adds a delay amount to the phase of the input signal. The voltage-controlled delay line (for input signals) 100 adds a delay amount to the phase of the input signal, and adds a delay signal for each of the delayers (for input signals) 110 to the voltage-controlled delay line (for input signals). Output to outside of 100.

The input signal input to the voltage controlled delay line (for an input signal) 100 is a signal to be finely adjusted in phase, for example, a data or a clock signal.

Here, the point of outputting the delay signal to the outside of the voltage controlled delay line (for the input signal) 100 will be described in more detail. The voltage-controlled delay line (for input signals) 100 transmits a delay signal to which a delay amount is added by some or all of the plurality of delayers (for input signals) 110 connected in series. ) And a delay (for an input signal) 110, respectively.

In the example shown in FIG. 1, in the example shown in FIG. 1, the voltage controlled delay line (for an input signal) 100 outputs, as "OUT1", a delay signal to which a delay amount is added by the delay unit "1 Tap". . In the voltage-controlled delay line (for input signals) 100, a delay signal added with a delay amount by the delay unit "1 Tap" and the delay unit "2 Tap" is output as "OUT2". In the voltage-controlled delay line (for input signals) 100, a delay signal added with a delay amount by all the delayers ("1 Tap" to "n Tap") is output as "OUTn".

It is to be noted that the delay unit (for the input signal) 110 is simply described here. The delay unit 110 (for input signal) 110 corresponds to, for example, two inverters.

In addition, the delay amount (added to the phase of the input signal) is determined by the control voltage input by the capacitor 250 included in the DLL circuit 200 in the delay unit 110 (for the input signal). In addition, the delay amount is a delay amount equal to or greater than the predetermined minimum amount and equal to or smaller than the predetermined maximum amount and becomes an amount within a certain range. In other words, the delay amount does not become a delay amount less than or equal to the predetermined minimum amount.

The predetermined minimum amount of the delay added by the delay unit (for the input signal) 110 becomes the propagation delay amount of the delay unit (for the input signal) 110 itself, and when the signal propagates, the delay (for the input signal) ( The delay amount necessarily delays 110). For example, when the phase control device is realized by LSI, the minimum time is high speed (minimum amount is small) when the LSI becomes smaller, but the phase resolution is limited to about tens of psec.

[DLL circuit]

Next, an example of a configuration of the DLL circuit 200 will be described with reference to FIG. 1. The phase control apparatus according to the first embodiment includes a voltage controlled delay line (for DLL) 210 and a phase comparator ("PD", Phase Detector) 230 in the DLL circuit 200. Moreover, the phase control apparatus which concerns on Example 1 has a charge pump ("CP", Charge Pump) 240, and a capacitor ("C", Capacitor) 250.

The voltage controlled delay line (for DLL) 210 is also referred to as a second delay line. In addition, the phase comparator 230 is also called a phase comparator. The capacitor 250 or the like is also referred to as a delay control circuit.

The voltage controlled delay line (for DLL) 210 has a plurality of delayers (for DLL) 220 (Tap) for adding a delay amount to the phase of the signal. For example, in the example shown in FIG. 1, the voltage controlled delay line (for DLL) 210 has a plurality of delayers (for DLL) 220 connected in series. The voltage controlled delay line (for DLL) 210 is connected to the phase comparator 230 and the clock generator 300. In addition, each of the delayers (for DLL) 220 included in the voltage-controlled delay line (for DLL) 210 is connected to a capacitor 250.

In addition, when the voltage controlled delay line (for DLL) 210 receives an input of an external signal from the outside of the DLL circuit 200, each of the delays (for DLL) 220 is placed on the external signal. Add the delay amount.

In addition, an external signal is a signal which frequency can be switched externally. As described later, the external signal may be any signal as long as it can change the delay amount added by each of the delay units (for the DLL) 220 in the DLL circuit 200, for example, a clock. Signal is used.

Specifically, the voltage controlled delay line (for DLL) 210 receives an input of an external signal from the clock generator 300. In the voltage-controlled delay line (for DLL) 210, an external signal is input to one end of a plurality of delayers (for DLL) 220 connected in series, and each of the plurality of delays (for DLL) 220 is provided. This delay amount is added to the external signal.

In addition, the voltage controlled delay line (for DLL) 210 outputs a delay signal delayed by all of the plurality of delays (for DLL) 220 to the phase comparator 230. Specifically, the voltage-controlled delay line (for DLL) 210 is one end of the plurality of delayers (for DLL) 220 connected in series (one end different from the one to which an external signal is input) and the delay end of the final stage. (For the DLL) 220, a delay signal is output to the phase comparator 230. As a specific example, the voltage-controlled delay line (for DLL) 210 phases a delay signal to which a delay amount is added by all of the delay (for DLL) 220 ("1 Tap" to "nTap"). Output to comparator 230.

In addition, the delay amount (for DLL) 220 is added to the phase of the input signal by the control voltage input by the capacitor 250 included in the DLL circuit 200. The delay unit (for DLL) 220 is a delay unit having the same function as the delay unit (for input signal) 110.

In the first embodiment, the voltage controlled delay line (for input signals) 100 and the voltage controlled delay line (for DLLs) 210 have the same structure. Specifically, the voltage controlled delay line (for input signals) 100 and the voltage controlled delay line (for DLLs) 210 have the same number of delays. In addition, each of the delays of the voltage controlled delay line (for input signals) 100 and the voltage controlled delay line (for DLLs) 210 uses the same control voltage supplied from the capacitor 250 to provide the same delay amount. Add.

The phase comparator 230 is connected to a voltage controlled delay line (for DLL) 210, a charge pump (for DLL) 240, and a clock generator 300. In addition, the phase comparator 230 is the delay stage of the final stage among the voltage controlled delay line (for DLL) 210 and the voltage controlled delay line (for DLL) 210. (For a DLL) 220.

The phase comparator 230 compares the phases of the two signals. Specifically, the phase comparator 230 transmits a delay signal delayed by all of the plurality of delayers (for DLL) 220 of the voltage-controlled delay line (for DLL) 210 to the voltage-controlled delay line (for DLL). Receive from 210. In addition, the phase comparator 230 receives an external signal from the clock generator 300. The phase comparator 230 compares the phase of the delay signal received from the voltage controlled delay line (for DLL) 210 with the phase of the external signal output by the clock generator 300. The phase comparator 230 transmits the comparison result (phase difference) to the charge pump (for DLL) 240.

To give a specific example, the phase comparator 230 uses the phase pump as a down signal pulse when the phase of the delay signal is compared with the external signal based on the difference between the phases of the two signals. To 240 (for a DLL). In addition, the phase comparator 230 transmits the phase difference to the charge pump (for DLL) 240 as an up signal pulse when the phase of the delay signal is late compared to the external signal.

The charge pump (for DLL) 240 is connected to the phase comparator 230 and the capacitor 250. In addition, when the comparison result is transmitted from the phase comparator 230, the charge pump (for DLL) 240 supplies the current corresponding to the comparison result to the capacitor 250.

Specifically, the charge pump (for DLL) 240 converts the phase difference transmitted from the phase comparator 230 into a current when the phase difference is transmitted from the phase comparator 230, and charges the current in the capacitor 250. Or discharge current in the capacitor 250. Here, the charge pump (for DLL) 240 charges a current to the capacitor 250 when the phase difference is transmitted as an up signal pulse from the phase comparator 230. In addition, the charge pump (for DLL) 240 discharges a current to the capacitor 250 when the phase difference is transmitted from the phase comparator 230 as a down signal pulse.

The capacitor 250 is connected to each of the retarder (for DLL) 220 included in the charge pump (for DLL) 240 and the voltage controlled delay line (for DLL) 210. The capacitor 250 is connected to each of the delayers (for input signals) 110 included in the voltage controlled delay line (for input signals) 100.

In addition, the capacitor 250 controls a plurality of retarders (for the DLL) 220 of the voltage-controlled delay line (for the DLL) 210 to control voltages generated and controlled from the phase difference output by the phase comparator 230. Enter in each. The capacitor 250 also inputs a control voltage to each of the plurality of delayers (for input signals) 110 of the voltage controlled delay line (for input signals) 100. Here, the capacitor 250 inputs the same control voltage to each of the delayers (for input signals) 110 and the delayers (for DLLs) 220.

Specifically, the capacitor 250 is charged or discharged with a current by the charge pump (for DLL) 240. Here, in the capacitor 250, the current charged or discharged by the charge pump (for DLL) 240 is integrated into the capacity of the capacitor 250 to become a control voltage. The capacitor 250 has a control voltage for each of the delayers (for the DLL) 220 of the voltage-controlled delay line (for the DLL) 210 and the delayers for the voltage-controlled delay line (for the input signal) 100. (For input signals) 110 to each.

Here, in the DLL circuit 200, the phase difference between the delay signal and the external signal is always monitored by the phase comparator 230, and the processing is performed so that the two phase differences are eliminated. The state in which the two phase differences have been eliminated means that the delay signal is synchronized with the external signal by one cycle. Specifically, in the DLL circuit 200, the comparison result is fed back from the phase comparator 230 to the capacitor 250 via the charge pump (for DLL) 240. As a result, the control voltage of the capacitor 250 becomes a value for synchronizing the delayed signal compared by the phase comparator 230 with an external signal by one period and synchronizing with all the plurality of delayers (for DLL) 220. The delayed signal is delayed one cycle from the external signal to become a phase locked signal.

That is, the DLL circuit 200 includes an external signal itself output by the clock generator 300 and a delay signal obtained by adding a delay amount to the external signal by the voltage-controlled delay line (for DLL) 210. Control to delay phase synchronization. As a result, in the DLL circuit 200, a control voltage Vcnt corresponding to one cycle of the external signal is generated and supplied to the capacitor 250. In the DLL circuit 200, the capacitor 250 supplies the control voltage Vcnt to the voltage controlled delay line (for an input signal) 100. As a result, the voltage-controlled delay line (for input signals) 100 adds a delay amount corresponding to one cycle of an external signal separate from the input signal output from the clock generator 300 to the input signal.

[Overview of Configuration of Clock Generator]

Next, the outline | summary of the structure of the clock generator 300 is demonstrated using FIG. The clock generator 300 outputs an external signal to the DLL circuit 200. Hereinafter, as shown in FIG. 2, the method which implements the clock generator 300 using the phase lock circuit ("PLL", Phase Locked Loop) 400 is demonstrated as an example.

2 is a figure for showing an example of the structure of the phase control apparatus which concerns on Example 1 in the case of using a phase synchronization circuit. In addition, the clock generator 300 should just be able to switch the frequency of the output external signal arbitrarily, and this invention is not limited to the method of implementing the clock generator 300 using the phase lock circuit 400. FIG. . For example, a voltage controlled oscillator ("VCO", Voltage Controlled Oscillator) may be used.

As shown in FIG. 2, the phase synchronization circuit 400 is connected to the DLL circuit 200. Specifically, the phase synchronization circuit 400 is connected to one end of a plurality of delayers (for DLL) 220 connected in series of the voltage controlled delay line (for DLL) 210.

In addition, as shown in FIG. 2, when the reference signal is input from the outside of the phase synchronization circuit 400, the phase synchronization circuit 400 adjusts the frequency of the reference signal. Adjust to external signal. Specifically, as described below, the phase synchronization circuit 400 adjusts the frequency of the reference signal using a control signal, as shown in "Dcnt (Divider Control)" in FIG. Shall be. The phase synchronization circuit 400 then transmits an external signal to the voltage controlled delay line (for DLL) 210.

In addition, below, it is assumed that the reference signal input from the outside of the phase synchronizing circuit 400 is a constant signal, and a method of switching the frequency of the reference signal by the phase synchronizing circuit 400 will be described.

[Configuration of Phase Synchronization Circuit]

Next, an example of the configuration of the phase synchronization circuit 400 will be described with reference to FIGS. 3 to 4. 3 is a diagram for illustrating an example of the structure of the phase synchronization circuit in the first embodiment. 4 is a diagram for explaining a frequency divider circuit in the first embodiment.

As shown in FIG. 3, the phase synchronization circuit 400 includes a phase frequency comparator (“PFD”, Phase Frequency Detector) 410, a charge pump (for PLL) 420, and a low pass filter (“LPF”). Low pass filter). The phase synchronization circuit 400 also includes a voltage controlled oscillator ("VCO", Voltage Controlled Oscillator) 440, and a divider circuit ("Divider") 450.

The phase synchronizing circuit 400 having such a configuration receives a reference signal as an input and sets the frequency of the reference signal at a frequency specified according to the division ratio of the frequency dividing circuit 450 inside the phase synchronizing circuit 400. Generates an external signal that is an adjusted signal. The phase synchronization circuit 400 then transfers an external signal to the voltage controlled delay line (for DLL) 210.

In addition, among the components of the phase synchronization circuit 400 described below, components other than the frequency divider 450 are the same as those of the general PLL.

The phase frequency comparator 410 is connected to a charge pump (for PLL) 420 and a divider circuit 450. In addition, the phase frequency comparator 410 compares the phases of the two signals.

Specifically, the phase frequency comparator 410 receives an input of a reference signal from the outside of the phase synchronization circuit 400 in which the phase frequency comparator 410 is provided. In addition, the phase frequency comparator 410 feedbacks and receives an external signal from the frequency dividing circuit 450. The phase frequency comparator 410 compares the phase of the reference signal with the phase of the external signal. The phase frequency comparator 410 then transfers the comparison result (phase difference) to the charge pump (for PLL) 420.

To give a specific example, the phase frequency comparator 410 is based on the difference between the phases of two signals, and when the phase of the reference signal is advanced compared to the external signal, the charge pump (PLL) is used as an up signal pulse. For the phase difference). In addition, when the phase of the reference signal is late compared to the external signal, the phase frequency comparator 410 transmits the phase difference to the charge pump (for PLL) 420 as a down signal pulse.

The charge pump (for PLL) 420 is connected to a phase frequency comparator 410 and a low pass filter 430.

When the comparison result is transmitted from the phase frequency comparator 410, the charge pump (for PLL) 420 transmits the current according to the comparison result to the low pass filter 430. Specifically, the charge pump (for PLL) 420 converts the phase difference transmitted from the phase frequency comparator 410 into a current. The charge pump (for PLL) 420 transfers the current to the low pass filter 430.

The low pass filter 430 is connected to a charge pump (for PLL) 420 and a voltage controlled oscillator 440. The low pass filter 430 attenuates and cuts off a frequency signal higher than a specific threshold from the current when current is transmitted from the charge pump (for PLL) 420. The low pass filter 430 passes only the low region frequency of the current to the voltage controlled oscillator 440.

The voltage controlled oscillator 440 is connected to the low pass filter 430 and the divider circuit 450. In addition, the voltage controlled oscillator 440 is connected to the DLL circuit 200.

The voltage controlled oscillator 440 is an oscillator for controlling the oscillation frequency with a voltage and oscillates an external signal. Specifically, the voltage controlled oscillator 440 oscillates a signal using the voltage output from the low pass filter 430. Here, the signal generated by the voltage controlled oscillator 440 becomes an external signal. The voltage controlled oscillator 440 then transmits an external signal to the frequency divider circuit 450 and to the DLL circuit 200 (voltage controlled delay line (for DLL) 210).

The frequency divider 450 switches the frequency of the external signal. Specifically, the frequency of the external signal transmitted from the voltage control oscillator 440 is switched, and the converted external signal is transmitted to the phase frequency comparator 410.

In addition, the frequency dividing circuit 450 receives a control signal specified by the user who uses the phase control apparatus according to the first embodiment, and uses the frequency division ratio (PLL constant multiple) specified by the control signal. To switch the frequency of the external signal.

It demonstrates concretely using the example shown in FIG. Here, it is assumed that the reference signal is "20 MHz" and the delayers (for DLL) 220 included in the voltage-controlled delay line (for DLL) 210 are "40". In addition, it demonstrates here on the basis of the state whose division ratio is "32".

For example, the case where the division ratio is changed from "32" to "31" by the control signal input from the user is demonstrated. In this case, the external signal ("PLL output" shown in FIG. 4) output from the phase synchronization circuit 400 is switched from "640 MHz" to "620 MHz" as shown in FIG. In addition, by switching the frequency, the delay amount corresponding to one cycle of the external signal added by the voltage-controlled delay line (for DLL) 210 is changed from "1562.5 psec" to "1612.9 psec". That is, the period of the external signal is changed to "50.4 psec" (corresponding to Δt). Since the delay amount added by each of the delay units corresponds to one cycle of the external signal, the sum of the delay amounts added by the delay units also changes by "50.4 psec."

Here, since each of the delayers adds a delay amount using the same control voltage, each of the delayers adds the same delay amount. For this reason, when the number of delayers (for DLL) 220 is "40", "50.4 psec" is equally distributed to each of the 40 delayers (for DLL) 220. As a result, the amount of delay added by each of the delay units (for the DLL) 220 changes by "1.3 psec" per one.

The initial period of the external signal output from the phase synchronization circuit 400 is "T0", and the number of delayers (for DLL) 220 of the voltage-controlled delay line (for DLL) 210 is "n". The case where the frequency dividing circuit 450 changes the period of an external signal "(DELTA) t" is demonstrated as an example. In this case, the period after switching becomes "T0 + Δt", and as a result, the delay amount (phase step amount) added by each of the delayers generated when switching the cycle of the external signal is "phase step amount = Δt / n". Is changed.

[Process by Phase Control Device]

Next, the flow of processing by the phase control device according to the first embodiment will be briefly described with reference to FIGS. 5 and 6. In the following, first, the flow of processing in the voltage controlled delay line (for input signals) 100 will be briefly described with reference to FIG. 5, and thereafter, the DLL circuit 200 will be described using FIG. 6. Briefly, the flow of processing in. 5 is a flowchart for explaining the flow of processing by the voltage controlled delay line (for input signals) in the first embodiment. 6 is a flowchart for explaining the flow of processing by the DLL circuit in the first embodiment.

First, the flow of processing in the voltage controlled delay line (for input signals) 100 will be briefly described with reference to FIG. 5. As shown in Fig. 5, in the voltage controlled delay line (for input signals) 100, when an input of an input signal is received (YES in step S101), each of the delays (for input signals) 110 is inputted to the input signal. The delay amount is added to the phase of (step S102). Specifically, each of the delayers (for input signals) 110 gives the input signal a delay amount that is uniquely determined based on the voltage of the capacitor 250. Each of the delayers (for input signals) 110 outputs the delay signals for each of the delayers (for input signals) 110 to the outside of the DLL circuit 200 (step S103).

Next, an example of processing in the DLL circuit 200 will be described with reference to FIG. 6. As shown in FIG. 6, in the DLL circuit 200, when there is an external signal (YES in step S201), the voltage of the capacitor is charged / discharged so as to phase-lock (step S202). Specifically, in the DLL circuit 200, the phase difference between the delayed signal and the external signal is always monitored by the phase comparator 230, and the processing is performed so that the two phase differences are eliminated. The control voltage of the capacitor 250 becomes a value for synchronizing the delay signal compared by the phase comparator 230 to an external signal.

[Effect of Example 1]

As described above, according to the first embodiment, the phase control apparatus, upon receiving the input of the input signal, phases the input signal by each of the delayers (for input signals) 110 that add a delay amount to the phase of the signal. The delay amount is added to the delay unit, and the delay signal for each delay unit (for the input signal) 110 is output. In addition, the phase control device includes a DLL circuit 200, and when the DLL circuit 200 receives an input of an external signal, each of the delayers (for the DLL) 220 with respect to the phase of the external signal. Add the delay amount. The phase control device includes a delay signal delayed by all of the plurality of delayers (for DLL) 220 of the voltage controlled delay line (for DLL) 210 and the voltage controlled delay line (for DLL) 210. Compare the phase difference with the external signal with no delay added in. In addition, the phase control apparatus controls a control voltage for synchronizing a delay signal compared by the phase comparator 230 to an external signal, and includes a voltage controlled delay line (for input signals) 100 and a voltage controlled delay line (for DLLs) 210. Input to each of a plurality of retarders. Accordingly, according to the first embodiment, the phase of the output signal can be finely controlled.

Specifically, each of the delay units can control the delay amount within a predetermined range, but the minimum delay amount has been present. For this reason, in the prior art, phase control in units of tens of psec has become a limit. The minimum delay amount is the minimum delay amount applied to the input signal as long as the input signal is delayed using the delay device. For this reason, it is not possible to make the delay amount of a delay apparatus less than the minimum delay amount.

Further, according to the first embodiment, the phase control apparatus generates an control signal corresponding to one cycle delay by inputting an external signal capable of switching frequency to a voltage controlled delay line. The phase control device supplies a control voltage generated from an external signal separate from the input signal to the voltage controlled delay line on the input signal side. Accordingly, according to the first embodiment, fine phase control of the output signal is possible differently from the conventional DLL circuit as shown in FIG. 7 is a diagram for explaining the effect of the phase control device according to the first embodiment.

Here, the relationship between each of the output signals and the delay amount will be described with reference to FIG. 8. In FIG. 8, the horizontal axis shows each output signal ("Output" of FIG. 8), and the vertical axis shows each delay amount added to each output signal. It is also assumed that there are "n" delays, and the output signals are from "OUT1" to "OUTn". In addition, the vertical axis | shaft shows the range of the delay amount which each delayer adds. 8 is a diagram for explaining the effect of the phase control device according to the first embodiment.

Here, "DIN" in FIG. 8 represents an input signal. In addition, the "non-control area" of FIG. 8 shows the minimum delay amount added to the input signal by the voltage controlled delay line. Specifically, for the input signal, the sum of the minimum delay amounts added by the n delay units is shown.

In addition, the "control area" of FIG. 8 shows the range of the delay amount which can be changed among the delay amounts which can be added by each delay apparatus. The delay amount given by each of the delay units is equal to or greater than the predetermined minimum value and equal to or less than the maximum value. For this reason, the sum (offset amount) of the said minimum value which each delayer gives with respect to an input signal is a part represented by a "non-control area." In addition, in addition to the "non-control area", the range of the amount of delay which each of the delayers may give to an input signal becomes a part represented by a "control area."

In addition, "A1"-"An" of FIG. 8 represent phase synchronization points. Specifically, when the delay signals compared in the phase comparator 230 are synchronized with the external signal by one cycle, the delay amounts added to each of the external signals are shown. For this reason, the sum of the delay amounts added to the input signals by each of the delay units is "A1" in the part (minimum delay amount) shown in the "non-control area" of FIG. 8, and the part shown in the "control area" of FIG. It becomes the part represented by-"An". In addition, the parts indicated by "A1" to "An" among the parts shown in the "control area" in FIG. 8 are delays that may be given to the input signal by each of the delay units in addition to the "uncontrol area". It is the sum of the amounts and the amount of delay that becomes a value within the range of the control area. For example, the part shown by "A1" of FIG. 8 is a value in a control area among the delay amount which "1 Tap" of FIG. 8 adds, Specifically, the boundary point of a control area and an uncontrol area, and "A1" It becomes the delay amount specified by.

And the sum total of delay amount turns into "T0 + (DELTA) t" from "T0" which is an initial period by switching an external signal. Here, the period difference "Δt" is equally distributed to each of the delayers, whereby the amount of delay added by the delayer can be finely changed.

In addition, the difference of the phase of an input signal ("DIN" of FIG. 9) and an output signal ("OUT1" to "OUTn" of FIG. 9) is demonstrated using FIG. As shown in FIG. 9, the phase of the output signal output as the delay signal which added the delay amount with respect to the said input signal is shifted compared with the phase of DIN (input signal). In addition, the difference between the phase of an input signal and the phase of the output signal ("OUTn" of FIG. 9) output from the delay terminal of a last stage becomes a delay amount corresponded to one period of an external signal. For this reason, the difference between the phase of an input signal and the phase of the output signal output from the delay stage of a last stage changes from "T0" to "T0 + (DELTA) t" by switching an external signal. 9 is a diagram for explaining the effect of the phase control device according to the first embodiment.

In addition, the phase difference "Δt" is distributed evenly to each output signal, and it is possible to change the phase of an output signal finely.

As described above, according to the first embodiment, by switching the external signal, the phase of the output signal can be minutely controlled at a value within the control range.

Further, according to the first embodiment, the phase control device further includes a phase synchronous circuit 400 capable of switching frequencies, and the phase synchronous circuit 400 receives a reference signal as an input, and the phase synchronous circuit 400 The external signal, which is a signal obtained by adjusting the frequency of the reference signal at a phase specified by the division ratio of the internal frequency divider 450, is output to the voltage-controlled delay line (for DLL) 210. Here, since the division circuit 450 receives the control signal specified by the user using the phase control device and uses the division ratio specified by the control signal, the division ratio can be controlled by the control signal. Design freedom can be improved on the user side.

[Example 2]

By the way, in the first embodiment, the load from the phase comparator 230 applied to the delay stage 220 (for the DLL) 220 in the last stage has not been considered, but the present invention is not limited thereto. Specifically, the load applied to the delay signal output from the delay stage 220 (for the DLL) 220 at the final stage by the phase comparator 230 may be considered.

That is, the phase comparator 230 gives a predetermined load to the delay stage 220 (for DLL) 220 at the last stage. In addition, the load provided from the phase comparator 230 is not given to the delay signal output from the delay (for DLL) 220 other than the delay (for DLL) 220 of the last stage. For this reason, the phase difference between the delay signal output from the delay stage (for DLL) 220 of the last stage and the delay signal output from the delay stage 220 (for DLL) before one of the final stages is continuous. The phase difference between each of the delay signals output from each of the two delayers 220 (for the DLL) is not the same.

In Example 1, although the difference in phase difference was not specifically considered, this invention is not limited to this, You may make phase difference equal.

Specifically, as shown in FIG. 10, the voltage controlled delay line (for input signals) 100 is provided to the phase comparator 230 for each of the delay signals output from each of the delayers (for input signals) 110. Each of the elements 500 imparts the same load as the predetermined load imparted by it. The voltage controlled delay line (for DLL) 210 is a phase comparator for each of the delay signals output from each of the delay (for DLL) 220 other than the delay (for DLL) 220 of the last stage. Each of the elements 500 imparts a load equal to a predetermined load imparted to the delay signal by 230. 10 is a diagram for illustrating an example of the configuration of the LSI according to the second embodiment.

In the second embodiment, an element 500 for applying a predetermined load to each of the delay signals output from the delay unit 110 for the voltage controlled delay line (for input signals) 100 is provided. For reasons of having, simply add. The voltage-controlled delay line (for input signals) 100 does not have a phase comparator, and the load from the phase comparator is any of the delayers (for input signals) 110 included in the voltage-controlled delay line (for input signals) 100. Not hanging

However, here, in the LSI disclosed in the phase control apparatus according to the second embodiment, the voltage controlled delay line (for input signals) 100 and the voltage controlled delay line (for DLLs) 210 have the same configuration and are the same. Operate at control voltage. For this reason, in consideration of the load by the phase comparator 230, when the voltage controlled delay line (for DLL) 210 adds the element 500, the voltage controlled delay line (for input signal) 100 is also used. The element 500 is added and it is set as the same structure.

That is, as described above, in the second embodiment, the phase control device is configured to provide a phase comparator (for all delayers) of the voltage controlled delay line (for input signals) 100 and the voltage controlled delay line (for DLLs) 210. Apply the same load as that given from 230). Accordingly, according to the second embodiment, the phase difference of each output signal can be made uniform.

Example 3

By the way, in Example 1 or Example 2, an external signal is input to the voltage controlled delay line (for DLL) 210 to generate a control voltage corresponding to a delay of one cycle of the external signal, and the generated control voltage is left as it is. The case where it supplies to the voltage controlled delay line (for input signals) 100 was demonstrated. However, the present invention is not limited thereto, and after the control voltage generated in the voltage controlled delay line (for DLL) 210 is adjusted, the adjusted control voltage is supplied to the voltage controlled delay line (for input signal) 100. You may also do it.

So, below, the method of supplying the adjusted control voltage to the voltage controlled delay line (for input signals) 100 is demonstrated. In addition, below, description is abbreviate | omitted about description common to Example 1 or Example 2 mentioned above.

Outline of Phase Control Apparatus According to Example 3

First, the outline | summary of the structure of the phase control apparatus which concerns on Example 3 is demonstrated using FIG. 11 is a figure for demonstrating an example of the structure of the phase control apparatus which concerns on Example 3. FIG.

Specifically, the phase control apparatus according to the third embodiment includes a control voltage generation circuit for generating a control voltage and a VCC 600 for adjusting the voltage value of the control voltage generated by the control voltage generation circuit. The phase control device according to the third embodiment uses a voltage controlled delay line (for an input signal) 100 or a voltage controlled delay line (a control voltage) that is a control voltage adjusted by a VCC 600 (Voltage Controlled Circuit). Input to each of the retarders 210).

The VCC 600 is also referred to as a voltage adjustment circuit.

Specifically, as shown in FIG. 11, in the phase control device according to the third embodiment, the VCC 600 is further added to an example of the structure of the phase control device according to the first embodiment described with reference to FIG. 2. Equipped. Here, the capacitor 250 in Example 3 is connected to the charge pump (for DLL) 240 and the VCC 600, and as shown by "Vin" in FIG. To send. The control voltage transmitted by the capacitor 250 in the third embodiment is the same as the control voltage described in the first and second embodiments.

In the third embodiment, the VCC 600 is connected to the capacitor 250 and is connected to each of the delayers (for input signals) 110 and the delayers (for DLLs) 220. In addition, the VCC 600 receives the control voltage from the capacitor 250 as shown in "Vin" in FIG. 11, and further controls the bias control signal as shown in "Dcnt2" in FIG. 11. Receive The VCC 600 then adjusts the voltage value of the received control voltage. The VCC 600 inputs the adjustment control voltage to each of the delayers (for input signals) 110 and the delayers (for DLLs) 220 as shown in "Vcnt" in FIG. 11.

In this regard, the phase control apparatus according to the third embodiment does not input the control voltage directly to each of the retarders, but inputs the adjustment control voltage adjusted by the VCC 600. Compared to the technique described above, finer phase control is possible.

[Example of Configuration of VCC in Example 3]

Next, an example of the structure of the VCC 600 in Example 3 is demonstrated using FIG. 12 is a diagram for explaining an example of the configuration of the VCC according to the third embodiment.

The VCC 600 according to the third embodiment may be any configuration as long as the control voltage can be adjusted. For example, the VCC 600 may be any configuration as long as the offset can be added to the control voltage. In the third embodiment, a method of realizing the VCC 600 using an inverted amplifier circuit by an operational amplifier will be described. However, the present invention is not limited thereto, and a non-inverted amplifier circuit by an operational amplifier may be used. .

In the example shown in FIG. 12, the VCC 600 includes a resistor 601, a resistor 602, an operational amplifier 603, a bias control unit 604, and a low pass filter unit 605. In addition, as shown by "Vin" in FIG. 12, the VCC 600 receives the control voltage from the outside of the VCC 600, and specifically, receives the control voltage from the capacitor 250. As shown in "Dcnt2" in FIG. 12, the VCC 600 receives a control signal for bias control for determining the voltage output by the bias control unit 604 from outside the VCC 600. In addition, the VCC 600 outputs the adjustment control voltage from the outside of the VCC 600, as shown in " Vcnt " in FIG. 12, and specifically, each of the delay units (for input signals) 110 and the delay units. An adjustment control voltage is output for each of (for DLL) 210. The control signal for the bias control unit is input from, for example, a user using the phase control device or another circuit using the phase control device.

The VCC 600 amplifies "Vin" based on the voltage shown in "Vref" in FIG. 12 as a control voltage shown in "Vin" in FIG. Moreover, the amplification factor which shows the ratio by which "Vin" is amplified is determined by the ratio of the resistance value of the resistance 601 and the resistance value of the resistance 602, and in Example 3, unless otherwise indicated, of the resistance 601 The case where ratio of the resistance value and the resistance value of the resistance 602 is "1" is demonstrated as an example.

Next, each part of the VCC 600 will be described with an emphasis on the operational amplifier 603. The operational amplifier 603 is connected to the resistor 601, the resistor 602, the bias control unit 604, and the low pass filter unit 605. In addition, the operational amplifier 603 has two inputs ("+" and "-"), is connected to the bias control unit 604 at the "+" input (non-inverting input), and "-" input (inverting input). ) Is connected to capacitor 250 via resistor 601.

In addition, the operational amplifier 603 has two inputs, and a voltage is applied to each of the two inputs.

Specifically, as shown in "Vref" in FIG. 12, the voltage transmitted from the bias control unit 604 is applied to the "+" input of the operational amplifier 603. In addition, as shown by "Vin" in FIG. 12, the control voltage from the capacitor 250 is applied to the "-" input of the operational amplifier 603.

In addition, the operational amplifier 603 has one output, and a voltage is output from one output. Specifically, as shown in " Vcnt " in FIG. 12, the voltage is output out of the VCC 600 through the low pass filter section 605, and the delay (for input signal) 110 or delay (for DLL) is used. 220). The voltage input from the operational amplifier 603 to the delay (for input signal) 110 or the delay (for DLL) 220 becomes the adjustment control voltage.

The operational amplifier 603 has a negative feedback from one output toward the "-" input, and the output voltage of the "+" input and the output voltage of the "-" input always coincide with the negative feedback effect. do. In other words, in the operational amplifier 603, the potential difference between the "-" input and the "+" input becomes "0".

The bias control unit 604 is connected to the operational amplifier 603 and applies a voltage to the "+" input of the operational amplifier 603. The voltage applied to the operational amplifier 603 by the bias control unit 604 becomes the reference voltage of the operational amplifier 603. For example, the bias control unit 604 receives the control signal for the bias control unit from the user who uses the phase control device according to the third embodiment, and determines the reference voltage using the received control signal for the bias control unit.

The bias control unit 604 may have any structure as long as it can input the reference voltage determined by the control signal for the bias control unit to the operational amplifier 603. For example, a method of realizing the bias control unit 604 using the DAC (Digital Analog Converter) will be described below, but the present invention is not limited thereto. In addition, below, although the method which implements the bias control part 604 using a resistance string type DAC among the method to which DAC was applied is demonstrated, this invention is not limited to this, For example, a resistance ladder type | mold and a weight resistance type | mold are described. Or the like may be used. In addition, in the example shown in FIG. 13, the bias control part 604 using the 3-bit bias control signal was used as an example. FIG. 13 is a view for explaining an example of the structure of a bias control unit using a resistance string type DAC in Example 3. FIG.

An example of the structure of the bias control unit 604 shown in FIG. 13 will be described how the reference voltage applied to the input of the + of the operational amplifier 603 by the bias control unit 604 is described. The bias control unit 604 controls the voltage applied to the "+" input of the operational amplifier by an n-bit control signal. In the example shown in FIG. 13, the bias control part 604 receives the 3-bit bias control signal, for example, when the control signal is "101", the bias control part 604 is a "MSB" of the Set the switch to "ON (1)", set the "BIT" switch to "OFF (0)", and set the "LSB" switch to "ON (1)". For example, the bias control unit 604 inputs the bias control reference voltage divided into 5/8 to the operational amplifier 603. The bias control reference voltage divided by 5/8 becomes the reference voltage in the operational amplifier 603.

The operational amplifier shown in FIG. 13 is a voltage follower inserted in order to cut off the load, and is different from the operational amplifier 603. In addition, the voltage output from the operational amplifier as the voltage follower shown in FIG. 13 becomes the reference voltage Vref. The reference voltage for the bias control unit is, for example, a voltage determined by the manufacturer who manufactures the VCC 600.

As described above, the negative feedback is applied to the operational amplifier 603. When the voltage applied by the bias control unit 604 to the "+" input of the operational amplifier 603 is changed, the operational amplifier 603 becomes the voltage. It operates to eliminate the difference, and as a result, the voltage according to the "-" input of the operational amplifier 603 is changed to the voltage of the "+" input of the operational amplifier 603.

In addition, in the operational amplifier 603, if a slight difference occurs in the voltages corresponding to the two inputs, the difference is reflected in the output voltage of the operational amplifier 603. However, this output voltage is soon fed back to the "-" input, and operates so that there is no difference in voltage between the two inputs.

The low pass filter 605 is connected to the operational amplifier 603 and is connected to each of the delay (for input signals) 110 and the delay (for DLLs) 220 that are outside the VCC 600. . In addition, the low pass filter unit 605 receives the adjustment control voltage from the operational amplifier 603 and removes noise included in the received adjustment control voltage, and then each of the delay units (for input signals) 110 and the delay unit. (For DLL) 220 are input to each.

[Relationship between Adjustment Control Voltage and Phase Difference]

Next, the relationship between the phase difference and control voltage which become a comparison result compared with the phase comparator 230 is demonstrated using FIG. 14 and FIG. 15. FIG. 14 and 15 are diagrams for showing the general characteristics established between the phase difference and the control voltage which are the comparison results compared in the phase comparators. In the example shown in FIG. 14, when the phase difference is "(pi)", for example, it described as the control voltage output from a capacitor being "Vh."

Similarly, normally (when there is no offset), the phase difference is controlled so that it becomes "0", and in this case, the control voltage becomes "(Vh + Vl) / 2". That is, the phase control device changes the phase slightly by setting an offset so that the phase difference is not "0".

In FIG. 14 and FIG. 15, the phase difference becomes "-π" from "π" because it is shifted for one cycle when the "2π" phase advances (or delays). That is, the absolute value of the phase difference does not become larger than "π". Similarly, "Vin" serving as a control voltage input to the VCC 600 also has a value within a range from "VI" corresponding to phase difference "-π" to "Vh" corresponding to "π".

Here, between the phase difference that is the comparison result compared in the phase comparator 230 and the control voltage input to the delay (for input signal) 110 or delay (for DLL) 220 output from the capacitor 250. The general characteristics shown in FIG. 14 and FIG. 15 hold. For this reason, the phase difference which becomes the comparison result compared with the phase comparator 230 is also controlled by controlling the voltage input into the delayer (for input signal) 110 or delayer (for DLL) 220.

As shown in FIG. 15, in the third embodiment, the "-" input of the operational amplifier 603 is the control shown in FIG. 14 from the "+" input of the operational amplifier 603 for the inverting input. The voltage is treated as the inverted voltage Vref.

Here, when the reference voltage input to the "+" of the operational amplifier 603 is changed by the bias control unit 604, the operational amplifier 603 operates to eliminate the voltage difference between the "+" input and the "-" input. do. As a result, the voltage according to the "-" input of the operational amplifier 603 changes to the reference voltage of the "+" input of the operational amplifier 603. That is, when the reference voltage which the bias control part 604 applies to the "+" input of the operational amplifier 603 changes, as shown in FIG. 15, the phase difference of an input signal changes with the phase difference corresponding to a reference voltage.

In other words, when the reference voltage of the bias control unit 604 is changed, the control voltage shown in the vertical axis of FIGS. 14 and 15 is changed, and the phase difference diagram of the output signal and the input signal shown in the horizontal axis of FIGS. It also changes. For this reason, the fineness of the pitch value of the reference voltage input from the bias control unit 604 becomes the resolution of the phase, and the finer the reference voltage input from the bias control unit 604, the better the phase resolution. For example, when controlling using an 8-bit control signal (external signal), 256 divisions are made. Here, the phase resolution can be set simply by determining the number of resistance divisions from the desired phase resolution.

Moreover, as shown in FIG. 16 or 17, the solid line shown to "Gain = 1" of FIG. 14 or FIG. 15 shows the case where DC gain (also called amplification factor) is "1", Specifically, The case where the ratio of the resistor 601 and the resistor 602 is 1 is shown. Similarly, "Gain = 0.5" and "Gain = 2" represent the cases where DC gain is "0.5" or "2", respectively. 16 and 17 are diagrams for showing general characteristics established between the phase difference and the control voltage when the DC gain is different.

Here, the DC gain of the operational amplifier 603 becomes [resistance 602 / resistance 601] and can be changed by changing the ratio of the resistance value of the resistance 601 and the resistance value of the resistance 602. As a result, it is possible to adjust the phase sensitivity per unit voltage by changing the ratio of the resistance values. In other words, when the DC gain changes, as shown in FIG. 16 and FIG. 17, the relationship established between the phase difference and the control voltage changes. For example, if the DC gain is changed from "1" to "2", the phase resolution becomes finer, and the delay is at the same control voltage when the DC gain is "2" compared to the case where the DC gain is "1". The phase difference becomes half. That is, it is possible to improve the resolution by raising the DC gain. In addition, as shown in FIG. 16 or FIG. 17, when DC gain is made into "2", compared with the case where DC gain is "1", the maximum control range of a phase becomes half in appearance.

In addition, a plurality of combinations of resistors that become different DC gains are prepared in advance, and a switching switch for determining which combination to use is determined by a signal received from the outside, whereby DC gain is obtained using a signal received from the outside. You may change it. That is, by controlling the DC gain, the delay amount added to the output signal may be controlled. For example, the bias control unit 604 receives a gain control signal specifying one of a combination of a plurality of resistors from a user who uses the phase control device. The bias control unit 604 then outputs the adjustment control voltage using a combination of the resistors specified by the received gain control signal.

[Effect of Example 3]

As described above, according to the third embodiment, the phase control device is provided with a VCC 600, and uses a voltage-controlled delay line (for input signals) 100 to adjust an adjustment control voltage which is a control voltage adjusted by the VCC 600. Or a delay of the voltage controlled delay line (for DLL) 210. As a result, compared with Example 1 or 2, phase resolution can be improved further.

That is, in order to improve the phase resolution, for example, the finer the division ratio of the division circuit 450, the better the phase resolution. Also, the higher the frequency, the better the phase resolution. Further, as the number of delay units provided in the voltage controlled delay line (for input signals) 100 or the voltage controlled delay line (for DLLs) 210 increases, the phase difference allocated to the individual delayers decreases, resulting in a phase resolution. This improves.

Here, the higher the frequency, the shorter the time equivalent to one cycle. As a result, the number of delay units provided in the voltage controlled delay line (for input signals) 100 or the voltage controlled delay line (for DLLs) 210 becomes smaller. . In other words, the technique of improving the phase resolution by increasing the frequency and the technique of increasing the number of delay units are opposed.

In the phase synchronizing circuit 400, when the frequency division ratio is changed, the phase relationship in the circuit is changed, and the reentry operation is performed. Here, when the re-entry operation is performed, it takes some time until the phase relationship is stabilized, for example, about tens of microseconds. In addition, the method of setting the division ratio finely and the method of setting the frequency high in the division circuit 450 may be a limitation in designing the circuit.

In addition, the case where phase control at a precision higher than about several psec is required in the future is also considered.

For example, in the optical transmission device, developments in which the transmission rates are 40 G, 100 G, and the like have been advanced. In the case of 100 G, the time corresponding to one cycle is 10 psec. As a result, when considering signal transmission using the phase information of the 100 G signal, there is a possibility that phase adjustment of 5 psec, 2.5 psec, and 1.25 psec may be required.

Here, according to the third embodiment, since the phase is controlled using the adjustment control voltage in which the control voltage is adjusted using the VCC 600, the phase resolution can be further improved as compared with the first and second embodiments. .

In addition, according to the third embodiment, the phase can be controlled without depending on the division ratio or the number of the delayers, and it is also possible to eliminate the time until the operation stability caused by the re-entry operation.

Here, the effect by Example 3 is further demonstrated. First, the phase resolution becomes "ΔΦ ₁ = Δt ÷ nTap" when the VCC 600 is not used. Moreover, ΔΦ ₁ represents the phase difference added to each retarder when the VCC 600 is not used. "ΔΦ ₁ " is a value obtained by dividing the phase difference "Δt" generated by the phase synchronization circuit 400 by the number of retarders "nTap".

In contrast, when the VCC 600 is used, "ΔΦ ₂ = T ₁ ÷ 2 ^nBit ÷ nTap". Here, "T ₁ " becomes an output signal period of the phase synchronization circuit 400 and corresponds to "2π" in FIGS. 16 and 17. "ΔΦ ₂ " represents the phase difference added to each retarder when the VCC 600 is used. "ΔΦ ₂ " is a value obtained by dividing "T ₁ " as the number of steps of adjusting the control voltage in the VCC 600. In the example shown in Example 3, for example, the case for dividing the reference voltage from the bias control unit 604 to "256", the value becomes a dividing "T _1" to "256".

Next, the effect of Example 3 is further demonstrated, showing a specific value using FIG. 18 is a table for explaining the effect of the third embodiment.

In the example shown in Fig. 18, the PREF REF signal (reference signal) is 20 MHz, the division ratio is 2 to n (n = 2 to 7), and the number of delay units provided in the voltage controlled delay line is 10 as an example. In the VCC 600, the case where the fineness of the pitch value of the voltage value is 8 bits (256 divisions) or 10 bits (1024 divisions) will be described as an example. In addition, it demonstrates based on the case where division ratio is "32".

As shown in "first phase control" in FIG. 18, when the division ratio is "16" and the VCC 600 is not used, the phase resolution is "3125.0 psec". In contrast, as shown in "second phase control" in FIG. 18, when the division ratio is "16" and the VCC 600 of "8 bit control" is used, "3125.0 psec" is divided into "256". The value becomes "1.22 psec".

As described above, according to the third embodiment, it is possible to supplement the constraint for obtaining the fine phase resolution and to improve the phase resolution. That is, according to the third embodiment, it is possible to supplement the constraint that the division ratio must be set fine and the constraint that the number of delay units as large as the voltage control delay line must be provided.

In addition, according to the third embodiment, it is possible to control the phase difference independently in the VCC 600 even if the division ratio is fixed, for example, even if the division ratio is fixed. It is also possible to improve the point that it is necessary.

Example 4

In the third embodiment, the phase comparator 230 compares the phase difference between the delayed signal delayed by all of the plurality of delayers (for DLL) 220 and the external signal outputted by the phase synchronization circuit 400. Although it demonstrated, this invention is not limited to this. For example, the phase difference between the delayed signal and the external signal delayed only by a part of the delayer (for the DLL) 220 provided in the voltage-controlled delay line (for the DLL) 210 may be compared.

For example, in the phase synchronization circuit 400, when the division ratio is greatly changed, the period of the external signal output from the phase synchronization circuit 400 is changed greatly. As a result, for example, if the phase difference is compared using the delay signal delayed by all of the delay units (for DLL) 220 irrespective of the division ratio, the "control area" described with reference to FIG. 8 will deviate. There is a case.

For example, as a result of the longer period of the external signal, each of the delayers (for the DLL) 220 corresponds to the external signal one cycle in the voltage-controlled delay line (for the DLL) 210 even though the maximum delay amount added is added. The delay amount may not be added. Further, for example, as a result of the decrease in the period of the external signal, even if each of the delayers 220 (for the DLL) 220 adds the minimum delay amount to be added, the voltage-controlled delay line (for the DLL) 210 is used in the external signal cycle. In some cases, a larger delay amount may be added than the corresponding delay amount.

For this reason, in Example 4, even if the period of the external signal output from the phase synchronizing circuit 400 changes significantly, the phase control apparatus which implements a fine phase control without leaving a "control area" is demonstrated.

As shown in FIG. 19, the phase control device according to the fourth embodiment further includes a selector circuit 700 (also referred to as a delay signal output unit). In addition, the selector circuit 700 receives a delay signal for each delay unit provided in the voltage controlled delay line (for DLL) 210 and outputs only a predetermined delay signal among the received delay signals. 19 is a figure for demonstrating an example of the structure of the phase control apparatus which concerns on Example 4. FIG. In FIG. 19, the selector circuit 700 is described only as "SEL" for convenience of description.

In the phase control apparatus according to the fourth embodiment, each of the retarder (for DLL) 220 provided in the voltage controlled delay line (for DLL) 210 is connected to the selector circuit 700. In the voltage-controlled delay line (for DLL) 210, when an external signal is received, each of the delayers (for DLL) 220 is connected to the foremost end of the plurality of delayers (for DLL) 220 connected in series. In order from the delay, the delay is added to the phase of the delay signal. In addition, each of the delay units (for DLL) 220 transmits a delay signal for each delay unit to the selector circuit 700. That is, each of the plurality of delayers (for DLL) 220 of the voltage-controlled delay line (for DLL) 210 is connected in series, and adds a delay amount to select a delay signal for each of the delay circuits. Also prints out.

For example, in the voltage controlled delay line (for DLL) 210, the delay unit "1" adds a delay amount to the external signal received from the phase synchronization circuit 400, and the delay unit "2" and the selector circuit 700 To send). Thereafter, the delay unit "2" adds a delay amount to the delay signal received from the delay unit "1" and transfers it to the delay unit "3" and the selector circuit 700.

The selector circuit 700 is connected to each of the retarders (for DLL) 220 and is also connected to the phase comparator 230. The selector circuit 700 receives a delay signal from each of the delayers (for the DLL) 220 and outputs only a predetermined delay signal among the received delay signals to the phase comparator 230. Specifically, as shown in "Dcnt1" in FIG. 19, the selector circuit 700 outputs a control signal for outputting a predetermined delay signal among the delay signals received from each of the delay units (for the DLL) 220. Receive. The selector circuit 700 then outputs only the delay signal specified by the received control signal to the phase comparator 230. In addition, in the example shown in FIG. 18, the case where the selector circuit 700 receives the same control signal as the control signal input also to the phase lock circuit 400 was described.

In addition, the selector circuit 700 includes, for example, a simple switch having a small propagation delay time. The switch is created using, for example, a transfer gate. For example, in the selector circuit 700, "ON" and "OFF" of the switch are controlled by a control signal, that is, which switches are closed and which switches are opened. In the selector circuit 700, each combination of "ON" and "OFF" of the switch outputs only one delay signal corresponding to each of the delay signals received from each of the delay units (for the DLL) 220. The circuit configuration of the selector circuit 700 may be any one as long as it can output a predetermined delay signal among the delay signals, and the present invention is not limited to the circuit configuration using a switch.

Here, the selector circuit 700 outputs a delay signal determined by the cycle length of the external signal. For example, the selector circuit 700 stores in advance the number of delay units (for DLL) 220 corresponding to the division ratio of the phase synchronization circuit 400. For example, the selector circuit 700 stores the number of the delayers (for DLL) 220 corresponding to the division ratio in advance by the manufacturer who manufactures the phase control apparatus. In addition, the division ratio is a value which determines the period length of an external signal as mentioned above. The selector circuit 700 outputs a delay signal to which a delay amount is added by the number of delay units 220 (for DLL) 220 corresponding to the division ratio selected by the phase synchronization circuit 400.

Moreover, the correspondence between the division ratio and the number of delay units (for DLL) 220 will be further described. In addition, if the division ratio "32", the case where the number of delay units (for DLL) 220 is "4" will be described using an example of the case where the "control area". For example, when the division ratio "16", the period of the external signal output from the phase synchronization circuit 400 is doubled compared with the period of the external signal output when the division ratio "32". For this reason, if the division ratio "16", the number of delay units (for DLL) 220 is "8" which is double the number of delay units (for DLL) 220 required when the division ratio "32". In this case, the selector circuit 700 stores the number of delay units (for DLL) 220 "8" in correspondence with the division ratio "16".

In the example shown in FIG. 18, the selector circuit 700 receives the same control signal as the control signal for determining the division ratio in the division circuit 450 of the phase synchronization circuit 400. In this case, the selector circuit 700 stores the number of delay units (for the DLL) 220 corresponding to the division ratio determined by the control signal for each control signal for determining the division ratio.

Thereafter, the phase comparator 230 compares the phase difference between the delay signal output by the selector circuit 700 and the external signal whose delay amount is not added in the voltage-controlled delay line (for the DLL) 210. Specifically, the phase comparator 230 compares the phase difference between the external signal received from the phase synchronization circuit 400 and the delay signal received from the selector circuit 700.

[Effect of Example 4]

As described above, according to the fourth embodiment, a delay signal for each of the delayers (for DLL) 220 included in the voltage-controlled delay line (for DLL) 210 is received, and only a predetermined delay signal is received among the received delay signals. A selector circuit 700 for outputting is further provided. The phase comparator 230 compares the phase difference between the delayed signal output by the selector circuit 700 and the external signal whose delay amount is not added in the voltage-controlled delay line (for the DLL) 210. As a result, in the fourth embodiment, by selecting the delay signal output from the selector circuit 700 in accordance with the fluctuation of the external signal, it is possible to realize minute phase control without departing from the "control area".

Here, the effect of Example 4 is further demonstrated using FIG. 20 and FIG. 20 and 21 are tables for explaining the effects of the fourth embodiment. When it demonstrates using FIG. 20 and FIG. 21, description about the same point as FIG. 18 is abbreviate | omitted.

In FIG. 20 and FIG. 21, the value of (DELTA) t etc. was illustrated based on the case where the division ratio "32" and the number of retarders (for DLL) 220 are "4". In addition, in the example shown in FIG. 20, the case where the number of the delayers (for DLL) 220 was fixed to "4" was shown. In addition, in the example shown in FIG. 21, the number of delayers (for DLL) 220 was set in inverse proportion to the division ratio, and the number of "1" to "32" was shown. In the following description, for example, the delay amount added by the four delay units (for DLL) 220 will be described as "1000 psec to 2000 psec".

As shown in FIG. 20, in the case of division ratio "4", the delay amount corresponding to one cycle of the external signal output from the phase synchronization circuit 400 becomes "12500.0 psec". In this case, when the VCC 600 is not used, "12500.0 psec" is added by the four delayers 220 (for the DLL), and the maximum delay rate of the four delays (for the DLL) 220 is added. The amount of delay exceeds "2000 psec".

In contrast, as shown in FIG. 21, the control range is deviated by changing the number of delay units (for the DLL) 220 in accordance with the period length of the external signal output from the phase synchronization circuit 400. Can be prevented. In the example shown in FIG. 21, as the number of division ratios increases, the period length of the external signal is reduced, so that the number of delay units (for DLL) 220 is reduced. For example, in the case of the division ratio "4", the number of delayers (for DLL) 220 is "32", and the delay amount added by the 32 delayers (for DLL) 220 is "12500.0 psec". . Here, if the delay amount added by the four delay units (for DLL) 220 is "1000 psec to 2000 psec", and the 32 delay units (for DLL) 220 are added, the delay amount of "8000 to 16000" is further increased. Done. That is, the delay amount added by each delay unit (for DLL) 220 is "12500.0 psec" and does not exceed the maximum value "16000 psec", and it is possible to realize minute phase control without departing from the control region.

As described above, according to the fourth embodiment, among the delayers (for DLL) 220 provided in the voltage-controlled delay line (for DLL) 210, how many delayers (for DLL) 220 are used. As a result, according to the fourth embodiment, it is possible to realize minute phase control without departing from the control region.

In addition, as shown in FIG. 21, since the number of stages of the delayer (for DLL) 220 may be increased or decreased in inverse proportion to the division ratio, when the division ratio is small, the number of delayers (for DLL) 220 increases, Even if the period of the external signal is large, it is possible to realize a minute phase resolution.

[Other Embodiments]

By the way, although the Example of this invention was described so far, this invention is not limited to the Example mentioned above, You may implement in another Example. So, below, another Example is demonstrated.

For example, in the phase control apparatus according to the first embodiment, a method of using the clock generator 300 when inputting an external signal to the DLL circuit 200 has been described. Specifically, the method in which the phase control device according to the first embodiment includes the clock generator 300 has been described. However, the present invention is not limited thereto. For example, in the phase control apparatus according to the third embodiment, an external signal may be received from the outside of the phase control apparatus according to the third embodiment and processed using the received external signal.

[Monitoring circuit]

Further, for example, the phase control device may further include a standard voltage storage unit that stores in advance a standard voltage to be input to each of the plurality of delay units of the second delay line, and a monitoring unit that monitors the control voltage or the adjusted control voltage. good. For example, the standard voltage storage unit stores the value of the standard voltage set by the user in advance.

That is, the monitoring unit monitors the control voltage or the adjustment control voltage input to the voltage controlled delay line (for input signals) 100 or the voltage controlled delay line (for DLLs) 210 and monitors whether the same as the preset standard voltage. . If the monitoring unit is not the same, the monitoring unit may feed back the monitoring result to the phase synchronization circuit 400 or the VCC 600 so that the control voltage and the adjustment control voltage are the same as the standard voltage.

For example, as shown in FIG. 22, the monitoring unit 701 is connected to the VCC 600. The monitoring unit 701 also includes a standard voltage storage unit that stores a standard voltage in advance. 22 is a figure for demonstrating an example of the structure of the phase control apparatus provided with a monitoring circuit. The monitoring unit 701 monitors the adjustment control voltage from the VCC 600 and refers to the standard voltage stored in the standard voltage storage unit to monitor whether the adjustment control voltage is equal to the standard voltage. And if the monitoring part 701 can obtain the monitoring result that is not the same, as shown to "Dcnt3" and "Dcnt4" of FIG. 22, the control signal which the value of the adjustment control voltage becomes the value of a standard voltage phases It transmits to the synchronous circuit 400 or the VCC 600.

When the phase synchronization circuit 400 receives the control signal from the monitoring circuit as shown in "Dcnt3" in FIG. 22, the phase synchronization circuit 400 changes to the division ratio determined by the received control signal, and further, the VCC 600. As shown in "Dcnt4" in FIG. 22, when a control signal is received from the monitoring circuit, the control voltage is adjusted using a reference voltage determined by the received control signal.

In addition, in the example shown in FIG. 22, although the monitoring part 701 demonstrated the case of monitoring adjustment control, this invention is not limited to this, For example, it monitors the control voltage from the capacitor 250, Also good. In addition, the monitoring unit 701 may monitor the control voltage and the adjustment control voltage.

[Distribution circuit]

In the first embodiment, the method of using the division circuit 450 as the method of switching the external signal in the phase synchronization circuit 400 has been described, but the present invention is not limited thereto. For example, the delay amount applied to the input signal by the phase synchronization circuit 400 may be fixed.

[System configuration]

In addition, the information (FIGS. 1-6, 9) containing the process step, control step, specific name, and various data and parameters shown in the said document or in figure can be changed arbitrarily except the case mentioned.

Regarding an embodiment including each of the above examples, the following supplementary notes are further disclosed.

(Book 1)

A first delay line which, upon receiving an input of an input signal, outputs a delay signal for each of the delayers by adding a delay amount to the phase of the input signal by each of the delayers adding a delay amount to the phase of the signal;

DLL circuit

And,

The DLL circuit,

A second delay line which adds a delay amount to the phase of the external signal by each of the delayers, when receiving an input of an external signal capable of switching frequency externally;

A phase comparator for comparing a phase difference between a delayed signal delayed by all of the plurality of delayers of the second delay line and an external signal to which the delay amount is not added in the second delay line;

A plurality of delays of the first delay line and the second delay line, the control voltages generated from the phase difference output by the phase comparator as a voltage for synchronizing the delay signals compared by the phase comparator with the external signal. Delay control circuit input to each

Phase control apparatus comprising a.

(Book 2)

The phase control device further includes a PLL circuit capable of switching frequency,

The PLL circuit receives a reference signal as an input and outputs an external signal, which is a signal obtained by adjusting a phase of the reference signal to a phase specified by a division ratio of a division circuit inside the PLL circuit, to the second delay line. The phase control apparatus of appendix 1 characterized by the above-mentioned.

(Supplementary Note 3)

The said division circuit receives the control signal specified by the user using the said phase control apparatus, and uses the division ratio specified by the said control signal, The phase control apparatus of the appendix 2 characterized by the above-mentioned.

(Appendix 4)

The retarder control circuit includes a control voltage generation circuit for generating a control voltage and a voltage adjustment circuit for adjusting a voltage value of the control voltage generated by the control voltage generation circuit, and adjusted by the voltage adjustment circuit. An adjustment control voltage as a control voltage is input to each of a plurality of retarders of said first delay line and said second delay line.

(Note 5)

The control voltage generation circuit generates a control voltage that becomes a fixed value,

The voltage control circuit according to Appendix 4, wherein the voltage adjustment circuit adjusts a voltage value of a control voltage which becomes a fixed value generated by the control voltage generation circuit.

(Note 6)

Each of the plurality of delay units of the second delay line is connected in series, and adds a delay amount to output a delay signal for each delay unit,

The phase control device may further include a delay signal output unit configured to receive a delay signal for each delay unit provided in the second delay line and to output only a delay signal determined by a period length of the external signal among the received delay signals. Equipped,

The phase control device according to Appendix 5, wherein the phase comparator compares a phase difference between a delay signal output by the delay signal output unit and an external signal to which a delay amount is not added in the second delay line.

(Appendix 7)

The voltage adjustment circuit includes a bias control unit and an operational amplifier, and the control voltage and the reference voltage value controlled by the bias control unit are the control voltages of the operational amplifier, whereby the control voltage is specified by the reference voltage value. Outputs an adjustment control voltage adjusted by

The operational amplifier according to Appendix 6, wherein the operational amplifier outputs an adjustment control voltage using a DC gain specified by a gain control signal specified by a user using the phase control apparatus.

(Appendix 8)

A storage unit which stores in advance a standard voltage to be input to each of the plurality of delay units of the second delay line;

Monitoring that the control voltage and / or the adjustment control voltage are equal to or equal to the standard voltage stored in advance in the storage unit, and if different, monitoring the feedback of the monitoring result to the control voltage generating circuit and / or the voltage adjusting circuit. More wealth,

And the control voltage generating circuit and / or the voltage adjusting circuit generate the control voltage and / or adjust the control voltage by using the feedback content from the monitoring unit.

(Appendix 9)

The phase comparator applies a predetermined load to the delay signal output from the delay unit of the last stage of the second delay line,

The first delay line has elements each for applying a load equal to a predetermined load imparted to the delay signal by the phase comparator for each of the delay signals output from each of the delayers,

The second delay line has elements each of which imparts a load equal to a predetermined load imparted to the delay signal by the phase comparator to each of the delay signals output from each of the delayers other than the delay terminal of the last stage. The phase control apparatus in any one of notes 1-8 characterized by the above-mentioned.

(Book 10)

A first delay line which, upon receiving an input of an input signal, outputs a delay signal for each of the delayers by adding a delay amount to the phase of the input signal by each of the delayers adding a delay amount to the phase of the signal;

DLL circuit

And,

The DLL circuit,

A second delay line which adds a delay amount to the phase of the external signal by each of the delayers, when receiving an input of an external signal capable of switching frequency externally;

A phase comparator for comparing a phase difference between a delayed signal delayed by all of the plurality of delayers of the second delay line and an external signal to which the delay amount is not added in the second delay line;

A plurality of delays of the first delay line and the second delay line, the control voltage generated from the phase difference output by the phase comparator as a voltage for synchronizing the delay signals compared by the phase comparator with the external signal. Delay control circuit input to each

Printed board equipped with a phase control device characterized in that it comprises a.

(Note 11)

Receiving a input of an input signal, the first delay process of outputting a delay signal for each of the delayers by adding a delay amount to the phase of the input signal by each of the delayers adding a delay amount to the phase of the signal;

DLL circuit

And,

The DLL circuit,

A second delay step of adding an amount of delay to the phase of the external signal by each of the delayers, when receiving an input of an external signal capable of switching frequency externally;

A phase comparison step of comparing a phase difference between a delayed signal delayed by all of the plurality of delayers in the second delay step and an external signal to which the delay amount is not added in the second delay step;

As a voltage for synchronizing the delayed signals compared by the phase comparison process with the external signal, a control voltage generated from the phase difference output by the phase comparison process is divided into a plurality of the first delayed process and the second delayed process. Retarder control process input to each retarder

Control method using a phase control device comprising a.

1 is a diagram for illustrating an example of the configuration of a phase control device according to a first embodiment.

FIG. 2 is a diagram for illustrating an example of the structure of the phase control device according to the first embodiment when a PLL circuit is used. FIG.

3 is a diagram for illustrating an example of the structure of a PLL phase synchronizing circuit according to the first embodiment.

FIG. 4 is a diagram for explaining a frequency divider circuit in Example 1. FIG.

Fig. 5 is a flowchart for explaining the flow of processing by the voltage controlled delay line (for input signals) in the first embodiment.

6 is a flowchart for explaining the flow of processing by the DLL circuit in the first embodiment.

7 is a view for explaining the effect of the phase control device according to the first embodiment;

8 is a diagram for explaining the effect of the phase control device according to the first embodiment;

9 is a view for explaining the effect of the phase control device according to the first embodiment;

10 is a diagram for illustrating an example of a configuration of a phase control device according to a second embodiment.

11 is a view for explaining an example of a configuration of a phase control device according to a third embodiment.

12 is a view for explaining an example of the configuration of a VCC according to the third embodiment;

FIG. 13 is a view for explaining an example of the structure of a bias control unit using a resistance string type DAC in Example 3. FIG.

FIG. 14 is a diagram for showing general characteristics established between a phase difference and a control voltage resulting from a comparison result of a phase comparator. FIG.

FIG. 15 is a diagram for showing general characteristics established between a phase difference and a control voltage resulting from a comparison result of a phase comparator. FIG.

FIG. 16 is a diagram for showing general characteristics established between a phase difference and a control voltage when the DC gain is different. FIG.

FIG. 17 is a diagram for showing general characteristics established between a phase difference and a control voltage when the DC gain is different. FIG.

18 is a table for explaining the effect of the third embodiment.

19 is a diagram for explaining an example of a configuration of a phase control device according to a fourth embodiment.

20 is a table for explaining the effect of the fourth embodiment.

21 is a table for explaining the effect of the fourth embodiment.

22 is a diagram for explaining an example of the configuration of a phase control device including a monitoring circuit.

<Explanation of symbols for main parts of the drawings>

100: voltage controlled delay line (for input signal) 110: delay (for input signal)

200: DLL circuit 210: voltage controlled delay line (for DLL)

220: delay unit (for DLL) 230: phase comparator

240: charge pump (for DLL) 250: capacitor

300: clock generator 400: phase locked circuit

410: phase frequency comparator 420: charge pump (for PLL)

430: low pass filter 440: voltage controlled oscillator

450: division circuit 500: element

600: VCC 601: resistance

602: resistance 603: operational amplifier

604: bias control unit 605: low pass filter unit

700: selector circuit

Claims (10)

A first delay line which, upon receiving an input of an input signal, outputs a delay signal for each of the delayers by adding a delay amount to the phase of the input signal by each of the delayers adding a delay amount to the phase of the signal; With DLL circuits, A clock generator that generates a signal, outputs the generated signal as an external signal to the DLL circuit, and switches the frequency of the generated external signal. And, The DLL circuit, A second delay line which, upon receiving an input of the external signal, adds a delay amount to the phase of the external signal by each of the delayers; A phase comparator for comparing a phase difference between a delayed signal delayed by all of the plurality of delayers of the second delay line and an external signal to which the delay amount is not added in the second delay line; A plurality of delays of the first delay line and the second delay line, the control voltage generated from the phase difference output by the phase comparator as a voltage for synchronizing the delay signals compared by the phase comparator with the external signal. Delay control circuit input to each Phase control apparatus comprising a. The clock generator of claim 1, wherein the clock generator includes a PLL circuit capable of switching to a signal having a different frequency. The PLL circuit outputs a signal obtained by adjusting the phase of the reference signal to a phase specified by a division ratio of a division circuit inside the PLL circuit as the external signal as the external signal to the second delay line. Phase control device characterized in that. The phase control device according to claim 2, wherein the frequency divider circuit receives a control signal specified by a user who uses the phase control device and uses a frequency division specified by the control signal. The said retarder control circuit is a control voltage generation circuit which produces a control voltage, and the voltage regulation circuit which adjusts the voltage value of the control voltage produced | generated by the said control voltage generation circuit, The said voltage control circuit is provided. And inputting an adjustment control voltage which is a control voltage adjusted by an adjustment circuit into each of the plurality of delays of the first delay line and the second delay line. The method of claim 4, wherein the control voltage generation circuit generates a control voltage that becomes a fixed value, And the voltage adjustment circuit adjusts a voltage value of a control voltage which becomes a fixed value generated by the control voltage generation circuit. The method of claim 5, wherein each of the plurality of delay units of the second delay line is connected in series, and adds a delay amount to output a delay signal for each delay unit, The phase control device may further include a delay signal output unit configured to receive a delay signal for each delay unit provided in the second delay line and to output only a delay signal determined by a period length of the external signal among the received delay signals. Including, And the phase comparator compares a phase difference between a delay signal output by the delay signal output unit and an external signal to which a delay amount is not added in the second delay line. 7. The voltage adjusting circuit according to claim 6, wherein the voltage adjusting circuit includes a bias control unit and an operational amplifier, and is specified by the reference voltage value by setting a control voltage and a reference voltage value controlled by the bias control unit as a control voltage of the operational amplifier. Outputting an adjustment control voltage obtained by adjusting the control voltage to a voltage that becomes And the operational amplifier outputs an adjustment control voltage using a DC gain specified by a gain control signal specified by a user using the phase control device. 8. The phase comparator according to claim 1, wherein the phase comparator applies a predetermined load to a delay signal output from the delay unit of the last stage of the second delay line. The first delay line has elements each for applying a load equal to a predetermined load imparted to the delay signal by the phase comparator for each of the delay signals output from each of the delayers, The second delay line has elements each of which imparts a load equal to a predetermined load imparted to the delay signal by the phase comparator to each of the delay signals output from each of the delayers other than the delay terminal of the last stage. Phase control device, characterized in that. A first delay line which, upon receiving an input of an input signal, outputs a delay signal for each of the delayers by adding a delay amount to the phase of the input signal by each of the delayers adding a delay amount to the phase of the signal; With DLL circuits, A clock generator that generates a signal, outputs the generated signal to the DLL circuit as an external signal, and can switch frequencies of the generated external signal. And, The DLL circuit, A second delay line which, upon receiving an input of the external signal, adds a delay amount to the phase of the external signal by each of the delayers; A phase comparator for comparing a phase difference between a delayed signal delayed by all of the plurality of delayers of the second delay line and an external signal to which the delay amount is not added in the second delay line; A plurality of delays of the first delay line and the second delay line, the control voltage generated from the phase difference output by the phase comparator as a voltage for synchronizing the delay signals compared by the phase comparator with the external signal. Delay control circuit input to each Print plate equipped with a phase control device, characterized in that it comprises a. Receiving a input of an input signal, the first delay process of outputting a delay signal for each of the delayers by adding a delay amount to the phase of the input signal by each of the delayers adding a delay amount to the phase of the signal; With DLL circuits, A clock generator that generates a signal, outputs the generated signal as an external signal to the DLL circuit, and switches the frequency of the generated external signal. And, The DLL circuit, A second delay step of adding a delay amount with respect to the phase of the external signal by each of the delayers, when receiving the input of the external signal; A phase comparison step of comparing a phase difference between a delayed signal delayed by all of the plurality of delayers in the second delay step and an external signal to which the delay amount is not added in the second delay step; As a voltage for synchronizing the delayed signals compared by the phase comparison process with the external signal, a control voltage generated from the phase difference output by the phase comparison process is divided into a plurality of the first delayed process and the second delayed process. Retarder control process input to each retarder Control method using a phase control device comprising a.

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