KR101034917B1 - Operating method of nonvolatile memory device - Google Patents

Abstract

PURPOSE: An operating method of a nonvolatile memory device is provided to prevent disturbance in program operation by controlling a voltage applied to each word line. CONSTITUTION: In an operating method of a nonvolatile memory device, a ground voltage is applied to a source selection line(SSL). A source selection transistor(SST) is turned off. A power source voltage(VCC) is applied to a drain select line(DSL). The power source voltage is applied to a drain voltage terminal(Vp). A first voltage(Vpass2) is applied to a first word line. A second voltage(Vpass3) is applied to a second word line. A third voltage(Vpass4) is applied to a third memory cell. A program voltage is applied to the selected word line.

Description

Operating method of nonvolatile memory device

The present invention relates to a method of operating a nonvolatile memory device, and more particularly, to a program operating method.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

In the nonvolatile memory device, a program operation for writing data into a memory cell, a read operation for reading data stored in the memory cell, an erase operation for erasing data stored in the memory cell, and the like are performed.

In the program operation, self-boosting occurs in a channel region in a string including an unselected memory cell. The self-boost is turned off by applying a power supply voltage (Vcc) to a bit line and applying a ground voltage to a source select line. In the state, the voltage is raised in the unselected cell string by applying the pass voltage and the program voltage to the word lines. This self-boosting reduces the potential difference between the program voltage and the channel to prevent programming of unselected memory cells.

However, during self-boosting, a hot carrier occurs due to a large voltage difference between the junction region and the channel region of the source select transistor, which causes carrier cells adjacent to the source select transistor in the string including the source select transistor. A hot carrier injection (HCI) phenomenon occurs, causing a threshold voltage of the corresponding memory cell to rise.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method of operating a nonvolatile memory device capable of preventing disturbance during programming.

The present invention provides a memory cell array including a plurality of memory cells connected in series, a drain select transistor connected between the memory cell and the bit line, and a source select transistor connected between the memory cell and the common source line. Precharging a channel region of the memory cells, applying a first voltage lower than a pass voltage to a first word line connected to a first memory cell adjacent to the source select transistor, and applying a first voltage to the first memory cell. Applying a second voltage lower than the first voltage to a second word line connected to an adjacent second memory cell, applying the pass voltage to the remaining word lines, and applying a program voltage to the selected word line. do. In this case, the first voltage may be set within a voltage range of 4V to 7V, the second voltage may be set within a voltage range of 0V to 3V, and the pass voltage may be set within a voltage range of 8V to 10V. have.

Precharging the channel region of the memory cells may include applying a ground voltage to a source select line connected to the gate of the source select transistor and a power supply voltage to a drain select line connected to the gate of the drain select transistor. And applying a ground voltage to a bit line connected to the memory cell to be programmed through the drain select transistor, and applying a power supply voltage to a bit line connected to the memory cell to be prohibited through the drain select transistor. can do.

The second voltage may be a voltage for turning off a channel of the second memory cell. A third voltage lower than the first voltage and higher than the second voltage may be applied to a third word line connected to a third memory cell adjacent to the second memory cell. In this case, the third voltage may be set within a voltage range of 4.5V to 5.5V.

According to the present invention, the voltage applied to each word line may be adjusted to prevent the disturbance phenomenon that may occur during a program operation. In particular, the memory cell adjacent to the source select transistor has an effect of preventing the failure caused by the threshold voltage is increased by hot carrier injection (HCI).

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 is a block diagram of a general nonvolatile memory device.

The nonvolatile memory device 100 includes a memory cell array 102, an X-decoder 104, a Y-decoder 106, a page buffer unit 108, a high voltage generator 110, a controller 112, and an IO buffer. Part 114 is included.

The memory cell array 102 includes a plurality of memory blocks. For example, the memory cell array 102 may include 1024 memory blocks.

The controller 112 performs overall control of the nonvolatile memory device 100, and generates a program command signal, an erase command signal, a read command signal, and the like according to a signal transmitted and received through the IO buffer unit 114. For example, when the chip enable signal / CE is enabled for the controller 112 and the write enable signal / WE is toggled, the controller 112 may respond to the IO buffer unit 114 in response thereto. Receives a command signal received through the command signal, and generates a program command, an erase command, a read command, and the like according to the command. In addition, the control unit 112 transmits a command signal according to a command latch enable (CLE) signal, and transmits an address signal according to an address latch enable (ALE) signal.

The high voltage generator 110 generates bias voltages in response to a program command, an erase command, or a read command of the controller 112, and supplies the bias voltages to the X-decoder 104.

The X-decoder 104 supplies the bias voltages supplied from the high voltage generator 110 to one of the blocks of the memory cell array 102 in response to the row address signal RADD generated by the controller 112. .

The Y-decoder 106 selects a specific page buffer from among a plurality of page buffers included in the page buffer unit 108 in response to the column address signal CADD. In addition, the Y-decoder 106 outputs the data stored in the page buffer unit 108 through the IO buffer unit 114 during a read operation.

The page buffer unit 108 stores data signals received through the IO buffer unit 114 and the Y-decoder 106 under the control of the control unit 112 and is shared by the blocks of the memory cell array 102. A plurality of page buffers are output to the bit lines. In addition, when each page buffer receives a read operation command from the controller 112, the page buffers store data read from the memory cell array 102 and then externally through the Y-decoder 106 and the IO buffer unit 114. Output it.

2 illustrates a structure of a general memory cell array.

Referring to FIG. 2, a memory cell array includes a plurality of memory cell blocks, but one memory cell block is shown for convenience.

The memory cell array includes a plurality of memory cell blocks, and a plurality of strings connected to each bit line BL are connected in parallel to a common source line CSL. The string includes memory cells MC0 to MCn in which data is stored, a drain select transistor DST connected between the bit line and the memory cell, and a source select transistor connected between the memory cell and the common source line CSL. SST). Gates of the drain select transistors DST are connected to form a drain select line DSL, gates of the source select transistors SST are connected to form a source select line SSL, and gates of memory cells included in different strings. Are connected to each word line WL0 to WLn. As shown in FIG. 2, each word line is called a page. In addition, the even bit line BLe and the odd bit line BLO are alternately connected to the cell strings, respectively.

3 is a cross-sectional view of a typical memory cell string. 3 illustrates an embodiment in which 32 memory cells MC0 to MC31 are included, and a bias is applied to a memory cell string including a program inhibit cell in which a threshold voltage does not change even when a program voltage is applied when a program operation is performed. A case where a voltage is applied will be described. In FIG. 3, the memory cells MC0 to MC31 include floating gates FG0 to FG31, control gates CG0 to CG31, a dielectric film (not shown), and a tunnel oxide film (not shown).

Referring to FIG. 3, a ground voltage is applied to the source select line SSL connected to the source select transistor SST to turn off the source select transistor SST. The power supply voltage VCC is applied to the drain select line DSL connected to the drain select transistor, and the power supply voltage VCC is applied to the drain voltage terminal V _D connected to the drain of the drain select transistor through a bit line. .

The pass voltage Vpass1 is applied to all word lines, thereby forming a channel region in the well region including the memory cells MC0 to MC31, the source select transistor SST, and the drain select transistor DST. The program voltage Vpgm is applied to the selected word line. That is, the program voltage Vpgm is applied to the memory cell MC4 connected to the selected word line.

At this time, as the pass voltage Vpass1 is applied to all word lines, the channel region of the memory cells MC0 to MC31 is boosted to a voltage of a predetermined size by a coupling phenomenon. Thus, even when a relatively high voltage program voltage Vpgm is applied to the memory cell MC4 connected to the selected word line, charge tunneling does not occur because the difference between the channel potential is not large. Accordingly, it is possible to prevent the threshold voltage of the memory cell MC4 connected to the selected word line from changing.

At this time, the source select transistor SST is in an off state and no channel is formed. That is, in the interface A between the channel region and the junction region of the source select transistor SST, a gate induced drain leakage (GIDL) phenomenon occurs in which hot carrier occurs due to a voltage difference between the channel regions. Accordingly, the hot carrier is injected into the floating gate FG0 of the first memory cell MC1 adjacent to the source select transistor SST, and the threshold voltage of the first memory cell MC1 increases to cause a fail. Done.

4 is a cross-sectional view of a memory cell string for explaining an operating method according to an exemplary embodiment. 4 illustrates an example in which 32 memory cells MC0 to MC31 are included, and a bias voltage is applied to a memory cell string including a program inhibiting cell when a program operation is performed. . In FIG. 4, the memory cells MC0 to MC31 include floating gates FG0 to FG31 and control gates CG0 to CG31.

Referring to FIG. 4, a ground voltage is applied to the source select line SSL connected to the source select transistor SST to turn off the source select transistor SST. The power supply voltage VCC is applied to the drain select line DSL connected to the drain select transistor, and the power supply voltage VCC is applied to the drain voltage terminal V _D connected to the drain of the drain select transistor.

The first voltage Vpass2 is applied to a first word line connected to the first memory cell MC0 adjacent to the source select transistor SST, and is applied to the second memory cell MC1 adjacent to the first memory cell MC0. The second voltage Vpass3 is applied to the second word line to be connected, the third voltage Vpass4 is applied to the third memory cell MC2 adjacent to the second memory cell MC1, and the pass voltage is applied to the remaining memory cells. Apply (Vpass1). The program voltage Vpgm is applied to the selected word line. That is, the program voltage Vpgm is applied to the memory cell MC4 connected to the selected word line.

In this case, the second voltage Vpass3 is a voltage for turning off the channel of the second memory cell MC1. Therefore, in the present invention, two channels, a first channel (channel 1) and a second channel (channel 2), are formed on the basis of the second memory cell MC1. The first voltage Vpass2 lower than the pass voltage Vpass1 is applied to the first word line so that the potential of the second channel (channel 2) is lower than that of the first channel (channel 1) even when channel boosting occurs. do. Therefore, in the present invention, since the potential difference between the source select transistor SST and the first word line WL1 is not large, the GIDL phenomenon does not occur in the source select transistor SST. Accordingly, the first memory cell MC0 is floated. Injecting charge into the gate FG0 can be prevented.

On the other hand, similarly to the case of the first memory cell MC0, the third memory cell MC2 may be charged with an HCI phenomenon from the adjacent second memory cell MC1 with the channel turned off. Therefore, the third voltage Vpass4 may be applied to the third word line connected to the third memory cell MC2 to prevent the charge from being injected into the floating gate FG2 of the third memory cell MC2. In the present invention, the third voltage Vpass4 is preferably lower than the pass voltage Vpass1 and higher than the second voltage Vpass3. As such, since the third voltage Vpass4 that is lower than the pass voltage Vpass1 is applied to the third word line, the voltage difference between the third voltage and the first channel (channel 1) is relatively small. Therefore, it is possible to prevent a phenomenon in which hot carriers are injected into the floating gate region FG2 of the third memory cell MC2.

Now, a method of operating the present invention will be described with reference to a timing diagram to which a specific bias voltage is applied. 5 is a timing diagram of a voltage bias according to an embodiment of the present invention.

Referring to FIG. 5, a voltage is applied to each word line in a T1 section, and a different voltage is applied to each word line in a T2 section. That is, the pass voltage Vpass1 is 9V, the first voltage Vpass2 is 7V, the second voltage Vpass3 is 3V, and the third voltage Vpass4 is 5V. In the T3 section, the program voltage Vpgm is applied to the selected word line. The program voltage Vpgm is 23V. The bias voltage value set in the embodiment of FIG. 5 is just one embodiment, and may be implemented by variously setting the bias voltage value according to the embodiment. For example, the pass voltage Vpass1 may be set within a voltage range of 8V to 10V, the first voltage Vpass2 may be set within a voltage range of 4V to 7V, and the second voltage Vpass3 may be set. The third voltage Vpass4 may be set within a voltage range of 0V to 3V, and the third voltage Vpass4 may be set within a voltage range of 4.5V to 5.5V.

As such, the first word line connected to the first memory cell MC0 is applied with a first voltage Vpass2 of 7V, which is lower than 9V, which is a pass voltage Vpass1, and thus has a relatively low channel potential. The GIDL phenomenon that may occur in the junction region of the transistor SST can be prevented. In addition, a second voltage of 3 V, which is a voltage for turning off a channel of the second memory cell MC1, is applied to the second word line connected to the second memory cell MC1. In addition, a third voltage Vpass4 of 5V lower than the pass voltage Vpass1 and higher than the second voltage Vpass3 is applied to the third word line connected to the third memory cell MC2 to lower the potential of the channel region. Charge is injected into the floating gate FG2 of the third memory cell MC2 to prevent the threshold voltage from rising.

While the invention has been described using some preferred embodiments, these embodiments are illustrative and not restrictive. Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the invention and the scope of the rights set forth in the appended claims.

1 is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

2 is a diagram illustrating a memory cell array according to an exemplary embodiment of the present invention.

3 is a cross-sectional view of a memory cell string.

4 is a cross-sectional view of a memory cell string in accordance with an embodiment of the present invention.

5 is a timing diagram of a voltage bias according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

102 Memory Cell Array 104 X-Decoder

106 Y-decoder 108 page buffer

110 High voltage generator 112 Control unit

114 IO buffer unit 100 Nonvolatile memory device

Claims (10)

Providing a memory cell array comprising a plurality of memory cells connected in series, a drain select transistor connected between the memory cell and the bit line, and a source select transistor connected between the memory cell and the common source line; Precharging a channel region of the memory cells; A first voltage lower than a pass voltage is applied to a first word line connected to a first memory cell adjacent to the source select transistor, and the second word line is connected to a second word cell connected to a second memory cell adjacent to the first memory cell. Applying a second voltage lower than one voltage and applying the pass voltage to the remaining word lines; And Applying a program voltage to the selected word line Method of operating a nonvolatile memory device comprising a. The method of claim 1, Precharging the channel region of the memory cells, Applying a ground voltage to a source select line connected to the gate of the source select transistor and applying a power supply voltage to a drain select line connected to the gate of the drain select transistor; And Applying a ground voltage to a bit line connected to the memory cell to be programmed through the drain select transistor, and applying a power supply voltage to the bit line connected to the memory cell to be prohibited through the drain select transistor; How the memory device works. The method of claim 1, And wherein the second voltage is a voltage at which a channel of the second memory cell is turned off. The method of claim 1, And applying a third voltage lower than the first voltage and higher than the second voltage to a third word line connected to a third memory cell adjacent to the second memory cell. The method of claim 1, And the first voltage is set within a voltage range of 4V to 7V. The method of claim 1, And the second voltage is set within a voltage range of 0V to 3V. The method of claim 1, And the pass voltage is set within a voltage range of 8V to 10V. The method of claim 4, wherein And the third voltage is set within a voltage range of 4.5V to 5.5V. Providing a memory cell array including a cell string comprising a plurality of memory cells connected in series, a drain select transistor connected between the memory cell and the bit line, and a source select transistor connected between the memory cell and the common source line; Inputting a program command for memory cells fifth from the source select transistor among the memory cells; Precharging a channel region of the memory cells; And A fifth to fourth pass voltage applied to first to fourth word lines respectively connected to first to fourth memory cells adjacent to the source select transistor, and a fifth to a memory cell selected for the program. Applying a program voltage to a word line, and then applying the fourth pass voltage to word lines connected to the remaining memory cells to perform a program Method of operating a nonvolatile memory device comprising a. The method of claim 1, The first pass voltage is a voltage higher than the second pass voltage, The third pass voltage is higher than the second pass voltage, The first pass voltage is higher than the third pass voltage, And the fourth pass voltage is higher than the first pass voltage.

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