KR101026376B1 - Method for forming the isolation layer - Google Patents

Abstract

The present invention relates to a device isolation film manufacturing method for improving the characteristics and the reliability of the device by preventing the occurrence of the mot and the electric field concentration phenomenon of the gate channel due to INWE.

The method of manufacturing an isolation layer according to the present invention includes forming a mask pattern defining a isolation region on a silicon substrate on which a well region is formed, forming a growth oxide layer on the silicon substrate exposed by the mask pattern, and forming the growth oxide layer. Forming a first oxide film over the grown substrate, selectively etching the first oxide film and the grown oxide film to form a first oxide spacer on the lower sidewall of the mask pattern, and using the first oxide spacer as a mask Etching to form a trench having a predetermined depth, forming a second oxide layer on the entire surface of the substrate on which the trench is formed, and selectively etching the second oxide layer to form a first oxide spacer and a second oxide spacer on the sidewalls of the trench. Etching the substrate exposed by the trench to a predetermined depth by over-etching the gap; Comprises the steps of, a step of removing the pad nitride layer to chemical mechanical polishing to the point where the first oxide film is removed, the gaeppil oxide film embedded in the oxide film.

Device Separation, Mortise, Growth Oxide, LOCOS, Trench, Field Concentration

Description

Method for forming the device isolation layer {Method for forming the isolation layer}             

1 is a view illustrating a problem of a device isolation film manufactured by a conventional device isolation film manufacturing method.

2A to 2F are cross-sectional views sequentially illustrating a method of manufacturing a device isolation layer according to an exemplary embodiment of the present invention.

 -Explanation of symbols for the main parts of the drawing-

100 silicon substrate 113 pad oxide film

116: pad nitride film 120: growth oxide film

135 first oxide spacer 138 second oxide spacer

140: trench 150: gap fill oxide film

160: gate

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a device isolation layer for preventing electric field concentration phenomenon of the gate channel due to the generation of the moat and the inverse narrow width effect (INWE).

In general, in the process of forming transistors, capacitors, and the like on a silicon substrate, an isolation region for forming a device isolation region for preventing a device from being electrically energized with an active region that is electrically conductive to the silicon substrate and separating the devices from each other.

By the way, in the step of forming the device isolation region, after forming a trench having a constant depth in the silicon substrate, depositing a gapfill oxide film in the trench, polishing the unnecessary portion of the gapfill oxide film by a chemical mechanical polishing process ( BACKGROUND OF THE INVENTION A shallow trench isolation (STI) process for forming an isolation layer on a silicon substrate by etching is widely used in recent years.

However, according to the method of manufacturing a device isolation film according to the prior art, a screen formed to reduce the damage of the active region during the pad nitride film removal process or the implantation of the threshold ion on the surface of the active region proceeds after the chemical mechanical polishing of the gapfill oxide film A portion of the edge of the device isolation film made of the gap fill oxide film is lost due to an oxide film removing process, and a moat is generated, and when the device is driven, an electric field is concentrated in a channel of a gate adjacent to the moat.

In addition, there is a problem in that an electric field is more concentrated in a channel of a gate due to INWE generated due to a decrease in design rules of devices due to high integration of semiconductor devices.                         

More specifically, as shown in FIG. 1A, during the pad nitride film removal process used as an etching mask for forming the trench, the active region is formed by different etching rates of the gap fill oxide film and the pad nitride film with the trench embedded therein. A moat, such as "Q", is formed at an edge portion of the device isolation layer adjacent to the bar, and when driving the gate 30 in which the gate oxide layer 31 and the gate electrode 35 are sequentially stacked thereon, the moat is formed. And a fringing field in which an electric field is concentrated in a channel of an adjacent gate 30 (FIG. 1B is a plan view schematically showing a substrate divided into a device isolation region and an active region, and FIG. A in Fig. 1 is a cross-sectional view taken along the line II 'of Fig. 1B).

On the other hand, the field concentration is more concentrated in the channel of the gate due to the INWE according to the reduction of the design rule of the device, thereby not only causing the electrical degradation of the device, but also changes in the threshold voltage due to the hump Is generated, and a leakage current is generated. This lowers the refresh characteristics of the semiconductor device and causes a problem of abnormally driving the device.

Accordingly, an aspect of the present invention is to provide a method of manufacturing a device isolation layer which prevents an electric field concentration phenomenon in which an electric field is concentrated in a gate channel due to generation of a moat and an INWE caused by a decrease in design ratio of a device.

In order to achieve the above object, the present invention comprises the steps of forming a mask pattern defining a device isolation region on a silicon substrate formed with a well region, forming a growth oxide film on the silicon substrate exposed by the mask pattern, Forming a first oxide film on an entire surface of the substrate on which the growth oxide film is grown, selectively etching the first oxide film and the growth oxide film, and forming a first oxide spacer on a lower sidewall of the mask pattern; Etching the silicon substrate by using an oxide spacer as a mask to form a trench having a predetermined depth, forming a second oxide layer on the entire surface of the trench, and selectively etching the second oxide layer to etch the first oxide. A second oxide spacer is formed on the spacer and the sidewalls of the trench, but is excessively etched by the trench. Etching the exposed substrate to a predetermined depth, filling the trench with a gapfill oxide film, chemically polishing the gapfill oxide film to the point where the first oxide film is removed, and removing the pad nitride film. The manufacturing method of the element isolation film containing is provided.

Here, the growth oxide film is preferably formed by using a Locos process to 100 ~ 500 ,, thereby preventing the occurrence of the moat in the upper edge portion of the device isolation layer adjacent to the active region during the subsequent pad nitride film removal process It serves as a reward.

The method may further include an ion implantation process of implanting the same ions as the ions constituting the well region into a region where the growth oxide film is formed, after the forming of the growth oxide film, wherein the ions are located under the growth oxide film. It is preferable to inject from the surface to the point having a depth of 50 ~ 500Å. Accordingly, it is possible to reduce the decrease in the threshold voltage caused by the moat generated in the upper corner portion of the device isolation layer.

In addition, the mask pattern is formed by sequentially stacking a pad oxide film and a pad nitride film.

In addition, the trench may have a depth of 1500 to 5000 으로부터 from the surface of the silicon substrate. In the etching process for forming the second oxide spacer, the silicon substrate exposed to the trench bottom may be excessively etched to a depth of 500 to 1500 의. It is desirable to form a deeper depth. Accordingly, the active regions neighboring each other may be safely insulated based on the trench.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

2A to 2F are cross-sectional views sequentially illustrating a method of manufacturing a device isolation layer according to an exemplary embodiment of the present invention.                     

First, as shown in FIG. 2A, a pad oxide film 113 and a pad nitride film 116 are sequentially formed on a silicon substrate 100 on which a well region (not shown) is formed, and then an element isolation region is defined thereon. A photosensitive film pattern (not shown) is formed. Here, the pad oxide layer 113 is deposited to a thickness of about 100 GPa to reduce stress of the silicon substrate 100 and the pad nitride layer 116.

Thereafter, the pad nitride layer 116 and the pad oxide layer 113 are etched using the photoresist pattern (not shown) as a mask to form a mask pattern 110 defining an isolation region on the silicon substrate 100. The mask pattern 110 has a structure in which the pad oxide layer 113 and the pad nitride layer 116 are sequentially stacked, which serves as a growth prevention layer and a trench etching process to prevent the growth oxide layer from growing laterally during the subsequent LOCOS process. It acts as an etch mask.

Next, a growth oxide layer 120 is formed by performing a LOCOS process on the silicon substrate 100 exposed by the mask pattern 110. At this time, the growth oxide film 120 is preferably grown to have a thickness of 100 ~ 500Å, which is the upper edge portion of the device isolation layer adjacent to the active region during the subsequent removal process of the pad nitride film 116 of the mask pattern 110 It is positioned above and serves as a compensation film to minimize the occurrence of the moat in the upper corner portion of the device isolation layer.

In addition, the same ions as the ions forming the well region on the surface of the growth oxide film 120 and the silicon substrate 100 positioned below the mask pattern 110 as an ion implantation mask, for example, BF2 and boron Inject ions of At this time, the implanted ions are preferably implanted to a point having a depth of 50 ~ 500Å from the surface of the silicon substrate 100 (see dotted line in Fig. 2a). Accordingly, when the moat occurs in the upper edge portion of the conventional isolation layer, it is possible to minimize the reduction of the threshold voltage due to the moat.

On the other hand, such an ion implantation process can be omitted as a secondary method for further minimizing the moat phenomenon that is primarily minimized by the growth oxide film.

Subsequently, as illustrated in FIG. 2B, the first oxide film 133 is formed on the entire surface of the substrate 100 on which the growth oxide film 120 is formed. Thereafter, the first oxide spacer 133 and the growth oxide layer 120 are selectively etched to form a first oxide spacer in which the growth oxide layer 120 and the first oxide layer 133 are sequentially stacked on the lower sidewall of the mask pattern 110. And form 135. In this case, a surface of the silicon substrate 100 corresponding to the device isolation region is exposed by an etching process for forming the first oxide spacer 135.

As illustrated in FIG. 2C, the trench 140 is formed by etching the silicon substrate 100 exposed with the first oxide spacer 135 as a mask for a predetermined depth. At this time, the trench 140 is formed to have a depth of 1500 ~ 5000Å from the surface of the silicon substrate 100, more preferably to have a depth of about 3500Å.

Next, as shown in FIG. 2D, a second oxide film (not shown) is formed on the entire surface of the substrate 100 on which the trench 140 is formed, and then selectively etched to form the first oxide spacer 135 and the trench ( The second oxide spacer 138 formed of the second oxide layer is formed on the sidewalls of the sidewall, and is excessively etched and exposed by the bottom surface of the trench 140 during the etching process for forming the second oxide spacer 138. The silicon substrate 100 is removed by a predetermined thickness, for example, by a thickness of 500-1500 Å to form a deeper depth of the trench 140. Accordingly, the active regions located on both sides of the trench 140 may be safely insulated from the trench 140 without an ion implantation process for preventing device isolation defects. That is, the present invention can simplify the overall manufacturing process of the semiconductor device while preventing device isolation defects in which adjacent active regions are shorted.

Next, as shown in FIG. 2E, a gap fill oxide film (not shown) is deposited to be sufficiently thick so that the trench 140 is buried in the entire surface of the substrate 100 on which the trench 140 is formed, and then the first oxide spacer is formed. The resultant isolation layer 150 made of a gapfill oxide layer is formed by chemical mechanical polishing of the resultant portion until the first oxide layer 133 is removed. In this case, the device isolation layer 150 is formed higher than the surface of the substrate 100 in the active region by the growth oxide layer 120 positioned at both sides.

In addition, during the chemical mechanical polishing process on the substrate 100 on which the device isolation layer 150 is formed, the remaining pad nitride layer 116 is removed using a phosphoric acid solution, and then a cleaning process is performed.

Meanwhile, in the etching process and the cleaning process for removing the pad nitride layer 116, a portion of the upper edge of the adjacent device isolation layer is lost, causing a moat phenomenon. According to an embodiment of the present invention, the pad nitride layer 116 The growth oxide film 120 and the second oxide spacer 138 are located at both sides of the upper edge of the device isolation layer adjacent to the second isolation layer, so that the loss margin is secured by the growth oxide film 120 and the second oxide spacer 138. It is possible to prevent the occurrence of mou, which is a conventional problem.                     

Next, the gate 160 is formed by sequentially forming the gate oxide layer 161 and the gate electrode 165 on the substrate 100 on which the device isolation layer 150 is formed.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, the present invention forms a growth oxide film on the upper edge portion of the device isolation layer adjacent to the active region by using the LOCOS process, and additionally implants the same ions as the well region, thereby causing the phenomenon of moist phenomenon and STI application. Prevents INWE from occurring

In addition, the hump and the field concentration phenomenon are prevented due to the prevention of the moat phenomenon and the INWE, thereby improving the refresh characteristics of the device and reducing the leakage current due to the lowering of the threshold voltage.

In addition, the present invention by forming a deeper depth of the trench, it is possible to safely insulate neighboring active areas without a separate device isolation defect prevention ion implantation process, it is possible to simplify the overall manufacturing process of the device.

Claims (7)

Forming a mask pattern defining a device isolation region on the silicon substrate on which the well region is formed; Forming a growth oxide film on the silicon substrate exposed by the mask pattern; An ion implantation step of implanting the same ions constituting the well region into the silicon substrate region where the growth oxide film is formed; Forming a first oxide film on an entire surface of the substrate on which the growth oxide film is grown; Selectively etching the first oxide film and the growth oxide film to form a first oxide spacer on a lower sidewall of the mask pattern; Etching the silicon substrate using the first oxide spacer as a mask to form a trench having a predetermined depth; Forming a second oxide film on an entire surface of the substrate on which the trench is formed; Selectively etching the second oxide layer to form a second oxide spacer on the first oxide spacer and the sidewalls of the trench, and excessively etching the substrate to be exposed by the trench to a predetermined depth; Filling the trench with a gapfill oxide film; Chemical mechanical polishing the gapfill oxide layer to a point where the first oxide layer is removed; And removing the mask pattern. The method of claim 1, The growth oxide film is a method of manufacturing a device isolation film to form a 100 ~ 500Å by using a Locos process. delete The method of claim 1, The ion implantation process is a method of manufacturing a device isolation film to ion implant to a point having a depth of 50 ~ 500Å from the surface of the silicon substrate located below the growth oxide film. The method of claim 1, The mask pattern is a method of manufacturing a device isolation film in which a pad oxide film and a pad nitride film are sequentially stacked. The method of claim 1, Before the forming of the second oxide layer, the trench has a depth of 1500 to 5000 으로부터 from the surface of the silicon substrate. The method of claim 1, When the second oxide spacer is formed, the step of over-etching the substrate exposed by the trench is to etch by 500 ~ 1500Å depth.

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