KR101017751B1 - Method for Fabricating Contact of Semiconductor Device - Google Patents

Abstract

The present invention relates to a method for forming a contact of a semiconductor device, and more particularly, to provide a substrate having a cell region having a high density gate and a peripheral circuit region having a low density gate; Depositing a first insulating film on the entire surface of the substrate; Selectively etching the first insulating layer on the peripheral circuit region to form a first spacer on a gate sidewall of the peripheral circuit region; Depositing a first nitride film over the cell region and the entire peripheral circuit region to form a second spacer on a gate surface of the peripheral circuit region; Removing the first insulating film and the first nitride film on the cell region to expose a gate of the cell region; Depositing a second nitride film on the gate of the exposed cell region and the entire gate of the peripheral circuit region to form a third spacer on the gate surface of the peripheral circuit region; Forming a planarized second insulating film over the cell region and the peripheral circuit region; And forming a contact for a landing plug by performing a two-step self-aligned etching process of etching the second insulating film and the second nitride film of the cell region, respectively, using the gate and the substrate of the cell region as an etch barrier. It provides a contact forming method of.

Description

Method for forming a contact of a semiconductor device {Method for Fabricating Contact of Semiconductor Device}

The present invention relates to a method for forming a contact of a semiconductor device.

Today, with the rapid spread of information media such as personal portable devices and personal computers equipped with memory devices, a process for manufacturing reliable highly integrated semiconductor devices having a large storage capacity and an improved operation speed for accessing data. Development of equipment and process technology is urgently needed.

A memory cell of a DRAM device is basically composed of a transistor that serves as a switch for transferring information and a capacitor that stores data. Data is transferred as the charge in the capacitor moves to the bitline through the Landing Plug Contact (LPC) when the gate is turned on. In this case, the landing plug contact is a structure in which a source and a bit line are connected to facilitate the movement of charge.

Generally, there is no power consumption or data loss while charge is accumulated in the capacitor. However, when leakage current occurs in the capacitor, the data is lost while the charge disappears to the outside. In this case, the process of periodically recharging the capacitor back to the initial charge amount before data is lost is called a refresh operation.

On the other hand, as the size of memory devices is gradually integrated to 50 nm or less, it is difficult to form landing plug contacts due to lack of spacing between gates. Conventionally, the process thickness was secured by reducing the spacer thickness of the gate sidewall. However, when the spacer thickness was reduced, boron phosphorous silicate glass (BPSG), which is used as an interlayer insulating film, was deposited and a subsequent thermal process was performed. Another problem arises in that boron penetrates into the gate and affects the transistor characteristics of the peripheral circuit region.

In the current mass production process of the memory device, instead of reducing the thickness of the gate sidewall spacers to secure the process margin between gates, a method of reducing the line width of the gate is applied. However, in the above method, since the aspect ratio of the gate is increased, not only the lining occurs in a subsequent process but also voids are formed in the insulating film during the deposition of the interlayer insulating film, or the landing plug contact is formed in the subsequent etching process. It causes another disadvantage of not opening.

It is an object of the present invention to provide a method for forming a contact of a semiconductor device including a two-step etching process to secure a gate line width and a sidewall spacer thickness of a peripheral circuit region and to easily form a landing plug contact. .

More specifically, in the present invention, the sidewall spacer deposition process is performed in several stages to form sidewall spacers having different thicknesses in the cell region and the peripheral circuit region, and then the two stages of self-aligned etching processes having different etching conditions are stable. Provided are a method for forming a contact of a semiconductor device capable of forming a landing plug contact that is opened in a manner.

Thus, in a preferred embodiment of the present invention

Providing a substrate comprising a cell region with a high density gate and a peripheral circuit region with a low density gate;

Depositing a first insulating film on the entire surface of the substrate;

Selectively etching the first insulating layer of the peripheral circuit region to form a first spacer on a gate sidewall of the peripheral circuit region;

Depositing a first nitride film over the cell region and the entire peripheral circuit region to form a second spacer on a gate surface of the peripheral circuit region;

Exposing a gate of the cell region by removing the first nitride layer and the first insulating layer of the cell region;

Depositing a second nitride film over the cell region and the entire peripheral circuit region to form a first spacer on the gate surface of the cell region, and forming a third spacer on the gate surface of the peripheral circuit region;

Embedding a planarized second insulating layer in front of the cell region and the peripheral circuit region; And

And forming a contact for a landing plug by performing a self aligned contact using the gate and the substrate in the cell region as an etch barrier.

In one embodiment of the present invention, the first insulating film is deposited using an oxide film.

The first spacer of the peripheral circuit region is formed by forming a photoresist pattern selectively exposing the peripheral circuit region on the first insulating film, and then using the same as an etching mask to anisotropically etch the first insulating film until the substrate is exposed. do.

The first nitride layer is deposited in a conformal form on top of the first insulating layer of the cell region and along the surface of the first spacer of the peripheral circuit region, and two spacers are formed on the gate surface of the peripheral circuit region. . The sum of the thicknesses of the two-layer spacers including the first and second spacers in the peripheral circuit region is preferably 400 kPa to 10,000 kPa.

In an embodiment, exposing the gate of the cell region may include forming a photoresist pattern selectively exposing the cell region by a photolithography process on the entire surface of the first nitride layer; Selectively removing only the first nitride film of the cell region using the photoresist pattern as an etching mask until the first insulating layer of the cell region is exposed; And removing the first insulating layer and the remaining photoresist pattern of the exposed cell region by using a wet etchant mixed with NH ₄ F, HF, and water.

At this time, the method of the present invention further includes the step of removing the etching residue by further performing a discum process on the entire surface of the substrate after the wet process.

In an exemplary embodiment, the second nitride layer is formed in a conformal form along the gate surface of the gate region exposed to the cell region and the gate surface of the peripheral circuit region. As a result, a single layer of first spacer is formed in the gate of the cell region, and a third spacer is formed in the gate surface of the peripheral circuit region. In this case, the gap between gates including the first spacer in the cell region may be appropriately changed according to the device size. Preferably, at least 30 nm or more, more preferably, between 30 nm and 100 nm intervals may be performed to perform a subsequent ion implantation process. It is desirable to have a process margin, in which case the maximum value is not particularly limited. In addition, after the deposition of the boron phosphorus silicate glass, which is a subsequent insulating film, the third spacer is deposited to a thickness of at least 50 mW, preferably 50 to 100 mW, to prevent boron from penetrating into the gate during the annealing process.

The second insulating layer may be an oxide layer, specifically, a gap fill material such as borophosphosilicate glass or spin on dielectric (SOD). After the second insulating film is buried, the method may further include performing an annealing process to improve gap fill characteristics. At this time, since the three-layer spacer is formed on the gate surface of the peripheral circuit region of the present invention as described above, it is possible to prevent boron from penetrating into the gate of the peripheral circuit region from the second insulating film during the annealing process. have.

The second insulating film is planarized by a chemical mechanical polishing process (CMP) or an etch back process.

In one embodiment of the present invention, the self-aligned etching process for forming the landing plug contact includes a two-step etching process performed under different etching process conditions. The self-aligned etching process is to form a contact hole using a step of the surrounding structure, the contact hole of various sizes can be obtained without a mask according to the height of the surrounding structure, the thickness of the insulating material to be formed and the etching method. Therefore, it is currently used in various methods in the mass production process of semiconductor devices refined by high integration.

In detail, the self-aligned etching process may include forming a mask pattern on the second insulating layer to selectively expose a cell region; Performing a first self-aligned etching process of forming the first contact by removing the second insulating layer using the mask pattern and the first spacer of the cell region as an etching barrier; Forming an etch barrier layer on the entire surface including the first contact; And performing a second self-aligned etching process using the gate of the cell region as an etching mask until the substrate is exposed.

The mask pattern may include forming a hard mask film including an amorphous carbon layer and a PE-TEOS film on the entire surface of the second insulating film, and a laminated film of an anti-reflection film; Forming a photoresist pattern on the laminated layer to selectively expose a cell region by a photolithography process; Etching the stacked layer using the photoresist pattern as an etch mask until the second insulating layer of the cell region is exposed. In this case, the etching process uses nitrogen (N ₂ ) and argon (Ar) gas.

The first self-aligned etching process is performed under a condition where the etching rate of the nitride film is low to etch the second insulating film until the first spacer of the cell region, that is, the second nitride film is exposed. For example, the first self-aligned etching process is performed with an etching gas in which argon gas and oxygen gas are combined with carbon fluoride gas made of C ₄ F ₆ , C ₄ F _8, or a combination thereof.

In addition, the etch barrier layer may be buffered so as not to damage the upper part of the gate and the inside of the landing plug contact during the second self-aligned etching process. Deposition is performed using a buffered oxide undoped silica glass and a nitride spacer for landing plug contacts. In this case, the buffer oxide layer is an oxide layer deposited to protect the upper portion of the gate. Since the step coverage is low, the buffer oxide layer is deposited only on the upper portion of the gate, and is not deposited on the gate sidewall and the bottom portion. In addition, the nitride film spacer for the landing plug contact may prevent damage to the gate sidewall during an etching process for opening the landing plug contact.

The secondary self-aligned etching process is an etch back etching process under conditions where the etching selectivity is different from that of the primary self-aligned etching process, specifically, the etching selectivity with respect to the nitride film until the substrate is exposed, that is, the nitride etching rate is high. Is performed. For example, the secondary self-aligned etching process is performed under polymer rich process conditions using an etching gas in which oxygen gas and argon gas are combined with C ₄ F ₄ gas until the substrate is exposed. The polymer rich process is a method applied to prevent shoulder damage of a spacer when performing an etching process in a self aligned contact (SAC) structure, and intentionally retains a polymer during an etching process for forming a contact hole. The contact hole sidewall is etched to have a slight slope.

The method further includes forming the landing plug contact and then filling the planarized conductive material over the contact front to form the landing plug contact. The method may further include depositing a third insulating film on the entire surface including the landing plug contact, and etching a predetermined region of the third insulating film to form a bit line contact bonded to the contact. have.

In the method of the present invention as described above, the first and second spacers are first formed on the gate sidewall of the peripheral circuit region, and then the first spacer is formed on the gate sidewall of the cell region and the third spacer is formed on the gate surface of the peripheral circuit region. By simultaneously performing the step of forming a, a single layer of spacers can be formed on the sidewalls of the cell region, and three spacer thicknesses can be ensured on the sidewalls of the peripheral circuit region. As a result, it is possible to secure a process margin of 10 nm or more compared to the current process during the landing plug contact forming process of the cell region, and to prevent boron from penetrating into the gate of the peripheral circuit region even during the annealing process for the interlayer insulating film. Thus, deterioration of transistor characteristics can be prevented.

Furthermore, in the method of the present invention, when the contact for the landing plug is formed, a two-step self-aligned etching process in which the etching rates with respect to the nitride film are different from each other is performed, so that even when fabricating a memory device in which design rules are highly integrated to 50 nm or less. The disadvantage of the landing plug contact not opening can be improved.

Therefore, in the present invention, instead of reducing the gate line width, a process margin for forming a landing plug contact can be secured by changing a spacer structure of a gate using a process method, thereby improving resistance and characteristics of a cell transistor.

According to the method of the present invention, even if the design rule is reduced, the process margin for forming the landing plug contact can be secured, so that the landing plug contact can be easily formed without reducing the gate line width. Therefore, the resistance and device characteristics of the cell transistor can be improved, and the production yield of the semiconductor device can be improved.

1A to 1J are schematic views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, a conductive layer (not shown) and a hard mask nitride layer (not shown) are deposited on an entire surface of a substrate 11 including a cell region A and a peripheral region B. By patterning, a high-density gate pattern 13-1 in which a conductive layer pattern (not shown) and a hard mask nitride film pattern (not shown) are stacked on the cell region A is formed, and the peripheral circuit region B is formed. The low density gate pattern 13-2 is formed.

Referring to FIG. 1B, the first insulating layer 15 is deposited on the entire surface of the substrate 11 including the gate pattern 13-1 of the cell region and the gate pattern 13-2 of the peripheral circuit region.

The first insulating film may be an oxide film.

Subsequently, after forming a photoresist pattern (not shown) exposing the peripheral circuit region on the entire surface of the first insulating film 15, and using the photoresist pattern as an etch mask until the substrate is exposed, The first insulating layer 15 is selectively anisotropically etched to form a first spacer 15-1 on the gate sidewall of the peripheral circuit region.

Subsequently, a first nitride film 17 is deposited on the entire surface including the first insulating layer 15 of the cell region and the first spacer 15-1 of the peripheral circuit region, and the second spacer is formed on the gate surface of the peripheral circuit region. (17-1) is formed. In this case, the thickness of the two-layer spacer including the first and second spacers in the peripheral circuit region is preferably 400 kV to 10,000 kPa.

Referring to FIG. 1C, a photoresist pattern 19 is formed on the entire surface on which the first nitride layer 17 is deposited, and a photoresist pattern 19 for selectively exposing a cell region is formed, and then the photoresist pattern 19 is formed. Is used as an etching mask to remove the first nitride layer 17 of the cell region until the first insulating layer 15 is exposed.

Referring to FIG. 1D, the exposed first insulating layer 15 and the remaining photoresist pattern 19 are removed by a wet etching process to expose the gate 13-1 of the cell region.

In this case, the wet etching process is performed using a wet etchant in which NH ₄ F, HF, and water are mixed. In addition, after the wet process, a discom process on the entire surface of the substrate is further performed to remove all of the etching residues remaining between the gates 13-1.

Referring to FIG. 1E, the gate of the cell region is deposited by depositing a conformal second nitride film on a surface of the exposed cell region gate 13-1 and the peripheral circuit region gate pattern 13-2. The first spacer 21 is formed on the sidewalls, and the third spacer 21-1 is formed on the gate surface of the peripheral circuit region.

In this case, it is preferable that the gap between gates of the cell part including the first spacer has a process margin of at least 30 nm so as to perform a subsequent ion implantation process. In the case of the third spacer, after deposition of the boron phosphorous silicate glass, which is a subsequent insulating film, it is preferable to deposit a thickness of 50 kPa or more so as to prevent boron from penetrating into the gate during the annealing process (see FIG. 2).

1F and 1G, a second insulating film 23 is deposited on the entire surface including the gate 13-1 of the cell region and the gate 13-2 of the peripheral circuit region, and then the gap fill characteristic is improved. In order to achieve the above, an annealing process is performed on the entire surface.

Subsequently, the planarization process is performed until the gate 13-1 of the cell region and the upper portion of the gate 13-2 of the peripheral circuit region are exposed. In this case, the second insulating layer is formed of a gap fill material such as borofossilicate glass. The second insulating film planarization method is performed by a chemical mechanical polishing process or an etch back process.

Referring to FIG. 1H, a stacked layer of a hard mask film such as an amorphous carbon layer (not shown) and a PE-TEOS film (not shown) and an antireflection film (not shown) are sequentially deposited on the second insulating film 23. Next, a photoresist pattern (not shown) in which a cell region is exposed by a photolithography process is formed on the antireflection film.

Using the photoresist pattern (not shown) as an etch mask, a stacked layer (not shown) is etched to form a mask pattern (not shown) until the second insulating layer 23 is exposed. In this case, the etching process uses nitrogen (N ₂ ) and argon (Ar) gas as an etching gas.

The second insulating layer 23 between the gate pattern 13-1 is removed by a first self-aligned etching process using the mask pattern, the gate of the cell region, and the first spacer 21 as an etching barrier. To form a first contact (not shown).

The first etching process is performed under a condition where the etching rate of the nitride film is low to etch the second insulating film until the first spacer of the cell region, that is, the second nitride film is exposed. For example, the first etching process may be performed using an etch gas in which argon gas and oxygen gas are combined with carbon fluoride gas made of C ₄ F ₆ , C ₄ F _8, or a combination thereof.

Subsequently, a buffer is placed on the gate and inside the primary contact so that the landing plug contacts are not damaged by the subsequent etching process. An etch barrier film (not shown) using an oxide film and a nitride film spacer for landing plug contact is deposited.

Next, the second contact for landing plugs is removed by removing the first spacer 21 of the cell region by a second self-aligned etching process using the buffer oxide layer (not shown) as an etching mask until the substrate 11 is exposed. To form 25.

The secondary etching process may be performed as an etch back etching process under conditions where the etching selectivity is different from the primary etching process, specifically, the etching selectivity with respect to the nitride layer until the substrate is exposed, that is, the nitride etching rate is high. For example, the secondary etching process is performed under polymer rich process conditions by using an etching gas in which oxygen gas and argon gas are combined with C ₄ F ₄ gas until the substrate is exposed.

Referring to FIG. 1I, a conductive material (not shown) is formed on the entire surface including the second contact 25, and then planarized to form a landing plug contact 27 until the upper portion of the gate is exposed.

Referring to FIG. 1J, a planarized third insulating layer 29 is deposited on the entire surface including the landing plug contact 27, and then a predetermined region of the third insulating layer 29 is etched to form the landing plug contact 27. ) To form a bit line contact 31 bonded thereto.

1A to 1J are process schematic diagrams illustrating a method for forming a contact of a semiconductor device of the present invention.

2 is an electron micrograph of several planes in cross section of the device of FIG.

<Brief description of the main parts of the drawing>

11: substrate 13-1: gate of cell region

13-2: Gate 15 of peripheral circuit region 15: First insulating film of cell region

15-1: First spacer of peripheral circuit region 17: First nitride film of cell region

17-1: second spacer of the peripheral circuit region 19: photoresist pattern

21: first spacer of the cell region

21-1: Third spacer of peripheral circuit area

23: second insulating film 25: contact for landing plug

27: landing plug contact 29: third insulating film

31: Bitline contact

A: cell area B: peripheral circuit area

Claims (11)

Providing a substrate comprising a cell region having a gate and a peripheral circuit region; Depositing a first insulating film on the entire surface of the substrate; Selectively etching the first insulating layer of the peripheral circuit region to form a first spacer on a gate sidewall of the peripheral circuit region; Depositing a first nitride film over the cell region and the entire peripheral circuit region to form a second spacer on a gate surface of the peripheral circuit region; Exposing a gate of the cell region by removing the first nitride layer and the first insulating layer of the cell region; Depositing a second nitride film over the cell region and the entire peripheral circuit region to form a first spacer on the gate surface of the cell region, and forming a third spacer on the gate surface of the peripheral circuit region; Embedding a planarized second insulating layer in front of the cell region and the peripheral circuit region; And And forming a landing plug contact by performing a self-aligned etching process using the gate and the substrate in the cell region as an etch barrier. The method according to claim 1, The first spacers of the peripheral circuit region form a photoresist pattern selectively exposing the peripheral circuit region by a photolithography process on the first insulating layer, and then use the same as an etching mask until the substrate is exposed. A contact forming method for a semiconductor device, characterized in that formed by performing. The method according to claim 1, The sum of the thicknesses of the spacers including the first spacer and the second spacer in the peripheral circuit region is 400 kPa to 10,000 kPa. The method according to claim 1, Exposing the gate of the cell region, Forming a photoresist pattern on the entire surface on which the first nitride film is deposited to selectively expose a cell region by a photolithography process; Selectively removing only the first nitride film of the cell region using the photoresist pattern as an etching mask until the first insulating layer of the cell region is exposed; And And removing the remaining first photoresist pattern and the remaining photoresist pattern in the exposed cell region by a wet etching process. The method according to claim 4, And after the wet process, performing a discom process on the entire surface of the substrate. The method according to claim 1, And the second insulating film is a gap fill material. The method according to claim 1, And filling the second insulating film, and then performing an annealing process. The method according to claim 1, The self-aligned etching process Forming a mask pattern over the second insulating layer to selectively expose a cell region; Performing a first self-aligned etching process of forming the first contact by removing the second insulating layer using the mask pattern and the first spacer of the cell region as an etching barrier; Forming an etch barrier layer on the entire surface including the first contact; And And performing a second self-aligned etching process using the gate of the cell region as an etching mask until the substrate is exposed. The method according to claim 8, The first self-aligned etching process is a contact forming method of a semiconductor device, characterized in that the etching gas is a combination of argon gas and oxygen gas to carbon fluoride carbon gas consisting of C ₄ F ₆ , C ₄ F ₈ or a combination thereof. . The method according to claim 8, And the etching barrier layer is a buffer oxide layer and a nitride spacer for a landing plug contact. The method according to claim 8, The second self-aligned etching process is a contact forming method of a semiconductor device, characterized in that the etching gas is a combination of oxygen gas and argon gas combined with C ₄ F ₄ gas under the polymer rich process conditions.

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