KR101015780B1 - Printed circuit board containing fine pattern and method for fabricating the same - Google Patents

Abstract

The present invention relates to a printed circuit board including a fine pattern and a method of manufacturing the same, forming an inner circuit pattern on a core substrate, and forming a conical bump using a conductive paste on the inner circuit pattern. And hardening the bumps, penetrating an insulating layer over the core substrate including the bumps, and penetrating the insulating layer over the core substrate including the bumps. Performing an etch back process on the insulation layer, performing a plasma treatment process on the surface of the insulation layer on which the etch back process is performed, and laminating copper foil on the insulation layer. And forming a layer circuit pattern by patterning the laminated copper foil, thereby manufacturing a printed circuit board having improved contact reliability between bumps and circuit patterns.

Description

Printed circuit board including fine pattern and manufacturing method therefor {PRINTED CIRCUIT BOARD CONTAINING FINE PATTERN AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board including a fine circuit pattern and a method of manufacturing the same. In particular, an external circuit and a flip chip of a memory module printed circuit board for flip-chip mounting in a printed circuit board for a solid state drive (SSD). The present invention relates to a technique for interconnecting bump pads with internal circuits using B2it (Buried Bump Interconnection Technology) bumps and manufacturing a high density and high reliability substrate.

As the electronic industry develops, high performance, high functionality, and miniaturization of electronic components are required. Accordingly, substrates for high-density surface-mount components such as SIP (System In Package) and 3D packages are emerging. As such, high density connection between circuit pattern layers is required in order to meet the demand for higher density and thinner substrates.

In the conventional multilayer printed circuit board, an inner layer circuit is formed by applying an additive method or a subtractive method to the surface of a core substrate such as a copper clad laminate (CCL), and an insulating layer and a metal layer are sequentially formed. It is manufactured by forming an outer layer circuit in the same way as an inner layer circuit while building up.

In the manufacturing process of multilayer printed circuit boards, the interstitial via hole (IVH), blind via hole (BVH), and plated through hole (PTH) are used for electrical connection between circuit patterns of each layer, and electrical connection between circuit patterns and electronic devices. Various via holes are formed. Among these, the PTH formed through the entire thickness of the substrate on the cross-section serves as a heat dissipation hole for dissipating heat generated in the substrate to the outside of the substrate, in addition to the aforementioned electrical connection function.

That is, in the manufacturing process of the multilayered printed circuit board according to the prior art, first, the IVH is drilled into the core board such as CCL by mechanical drilling, etc. After forming, the inner space of the IVH is filled, the surface is polished, and the inner layer circuit is formed by applying an additive method or a subtractive method to the surface of the core substrate.

Next, after the insulating material is laminated on the surface of the core substrate, a metal layer is formed on the surface or an insulating material on which the metal layer is formed on the surface, such as Resin coated copper (RCC), and the electrical connection between the metal layer and the inner layer circuit is performed by laser drilling. For example, by processing the BVH, perforating the PTH through the entire cross-section of the printed circuit board by mechanical drilling, forming an outer layer circuit on the surface of the insulating material in the same manner as the inner layer circuit and plating the inner circumferential surface of the PTH. Function as a heat radiation hole.

However, such a conventional technique requires a complicated process, requires a costly and time-consuming plating process, insufficient heat dissipation effect through PTH, and forms a circuit pattern after forming a plated layer, thereby forming a circuit by a plated layer. There is a problem that the increase in the thickness of the pattern is an obstacle to the formation of the microcircuit.

1A and 1B are cross-sectional views illustrating a via connection method according to the prior art.

1A and 1B illustrate cross-sectional photographs of a printed circuit board of a step via 5 and a skip via 7 according to the related art. In the case of such a multi-layer connection method, it is difficult to secure uniform laser drilling and copper plating quality, and there is a limit in implementing a fine circuit due to an increase in the surface thickness. In addition, there is a problem in that productivity increases due to an increase in the number of process treatments and a cost and lead time.

On the other hand, a technique for simplifying such a complicated process of the prior art and manufacturing a multilayer printed circuit board by batch lamination has been developed.

2A to 2C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to the prior art.

Referring to FIG. 2A, a copper thin plate 20 is formed on the core substrate 10, and a paste 30 is printed on the copper substrate 20 to form a bump 30.

Referring to FIG. 2B, the insulating layer 40 is stacked on the bump 30 to complete a substrate to which fine circuit wiring is applied.

Referring to FIG. 2C, the copper foil pattern 50 is formed on the insulating layer 40 including the bumps 30 to complete the printed circuit board. As described above, a method of manufacturing a printed circuit board by a simple and easy lamination process is called a so-called 'Burit bump interconnection technology' (B2it) technology, which is already commercialized.

However, as can be seen with reference to FIG. 3, the bumps 30 are not normally energized while the insulating layers 40 are stacked, and thus a problem of contact reliability with respect to the wiring connection may occur.

3 is a cross-sectional view illustrating a problem of the B2it technology according to the prior art, and is an enlarged view of a region 'A' in FIG. 1C.

In the normal B2it technology, the bump 30 must be exposed through the insulating layer 40 while the insulating layer 40 is stacked. Such a process is referred to as a piercing process, and when this process is not normally performed, a problem as shown in FIG. 2 occurs.

In addition, a problem may occur in that the surface of the outer copper foil pattern 50 formed on the bump 30 by the bump 30 protruding from the insulating layer 40 is also convex.

As described above, according to the B2it technology or the problem that the surface state of the insulating layer 40 is rough, the B2it technology may have a problem of deterioration of reliability in which bump-to-bump connection is not possible, or a short circuit may occur in a high voltage and high frequency environment. For this reason, B2it technology has a problem that cannot be applied to manufacturing a printed circuit board requiring a fine circuit pattern such as an SSD substrate.

According to the present invention, a printed circuit board manufacturing method using a B2it connection is performed by adding an etch back process and a plasma process after performing an insulating layer piercing process on the B2it bump. It is an object of the present invention to provide a method for manufacturing a printed circuit board to improve contact reliability between circuit patterns and to facilitate formation of a fine circuit pattern.

In addition, an object of the present invention is to provide a printed circuit board using the new B2it method described above to improve contact reliability, and to eliminate additional copper plating processes or unnecessary process waste elements, thereby improving production yield and reliability.

The method of manufacturing a printed circuit board including a fine pattern according to the present invention includes the steps of forming an inner circuit pattern on a core substrate, forming a conical bump on the inner circuit pattern using a conductive paste, and forming the bump. Hardening the insulating layer and penetrating the insulating layer on the core substrate including the bump; Performing an etch back process on the insulation layer, performing a plasma treatment process on the surface of the insulation layer on which the etch back process is performed, and laminating copper foil on the insulation layer. Steps and

And patterning the laminated copper foil to form an outer layer circuit pattern.

The core substrate may include a blind via hole (BVH), the BVH may be connected to the bumps, and the bumps may be formed using silver paste. The bag process includes microetching the surface of the insulating layer using a mixture of potassium permanganate and sodium hydroxide, and dissolving and removing glass fibers exposed to the surface of the insulating layer using fluoride. The plasma treatment process is characterized by using any one or more of Ar, CF ₄ , O ₂ , H ₂ plasma, characterized in that the thickness of the outer circuit pattern is formed to 12 ~ 18㎛, the outer circuit pattern is It is formed to include a line / space pattern of less than 3mil.

In addition, the present invention includes a printed circuit board formed by the above-described manufacturing method.

According to the method of manufacturing a printed circuit board using the B2it connection according to the present invention, the bump and the circuit pattern by adding an etch back process and a plasma process after piercing the insulating layer of the B2it bump It provides an effect that can improve the contact reliability.

In addition, the use of the B2it method according to the present invention ensures contact reliability, thereby eliminating the need for an additional copper plating process. Therefore, unnecessary process waste is eliminated and the fine pattern formation is more easily provided.

The present invention is a method of manufacturing a printed circuit board for SSD by using a B2it technology to form a circuit pattern on the surface of the core substrate, a paste bump (tope bump) on the circuit pattern, and then laminated an insulating layer thereon To provide.

In this case, in order to improve the reliability of the outer circuit pattern formed on the insulating layer, the present invention performs an etch back and plasma treatment process after the piercing process to treat the surface of the insulating layer and the upper part of the bump.

Hereinafter, a preferred embodiment of a printed circuit board and a manufacturing method including the fine pattern according to the present invention will be described in detail with reference to the accompanying drawings.

In the description with reference to the accompanying drawings, the same components will be denoted by the same reference numerals regardless of the reference numerals and redundant description thereof will be omitted.

4A to 4E are cross-sectional views illustrating a method of manufacturing a printed circuit board using the B2it technology according to the present invention, and FIG. 5 is a cross-sectional view illustrating a printed circuit board according to the present invention.

Referring to FIG. 4A, a copper foil plate 120 constituting an internal circuit is formed on an upper portion of the core substrate 100, and a conical bump 130 is formed on the upper portion of the copper plate 120 using a conductive paste.

Here, the copper plate 120 is preferably formed to correspond to the position of the blind via hole (BVH) formed in the core substrate 100. In general, the core substrate 100 is effective to form a circuit pattern by using a copper clad laminate (CCL) in which a copper foil layer is laminated on a surface thereof. In the present embodiment, BVH is described as an example of the via hole, but the via hole according to the present invention is not necessarily limited to the BVH.

Next, the bump 130 is formed by printing a bump shape on the surface of the copper plate 120 using a conductive paste, and curing the printed paste bump.

Referring to FIG. 4B, an insulating layer 140 is stacked on the entire surface of the core substrate 100 including the bumps 130. At this time, the stacking process of the insulating layer 140 is performed by roll pressing, and the piercing process is performed at the same time so that the bumps 130 may be exposed through the insulating layer 140.

Here, since the bump 30 must be able to penetrate the insulating layer 140 by a piercing process, it is preferable to form the bump 30 using a conductive paste having a greater strength than the insulating layer 140. In the present invention, a silver paste may be used as a material of the bump 130, but other types of paste may be used within a range apparent to those skilled in the art in consideration of the strength, cost, and applicability of the paste.

Referring to FIG. 4C, an etch back process is performed on the surface of the insulating layer 140. An etch back process is mainly used for a planarization process in a general semiconductor process, and in the present invention, the etch back process may be used by borrowing a process of etching back an interlayer insulating film.

As an example, the etch bag first microetches the surface of the insulating layer 120 using a mixture of potassium permanganate and sodium hydroxide, and the insulating layer remaining on the upper part (tip) of the bump 130 after the piercing process ( 140) The organic resin or glass fiber of the component can be removed. Next, the organic resin or glass fiber 160 exposed on the surface of the insulating layer 140 and the tip of the bump 130 is dissolved and removed using fluoride.

As such, the bump 130 may be reliably energized through the etch back process.

Referring to FIG. 4D, a plasma treatment process is performed on the surface of the insulating layer 140 and the bump 130 on which the etch back process is performed to prepare the surface state. At this time, the plasma treatment process uses plasma such as Ar, CF ₄ , O ₂ , H ₂ . Plasma treatment removes the organic resin or glass fibers exposed to the tip surface of the bump 130 and changes the chemical and physical properties of the surface of the insulating layer 140 to further form a circuit pattern or other insulating layer formed in a subsequent process. It helps to form well.

Thus, by arranging the surface state, it is possible to improve the connection reliability of the bump 130 and to form an outer layer circuit pattern more finely.

In this case, since the plasma has sufficient energy to break the intermolecular bonds of the organic resin on the surface of the insulating layer, the plasma decomposes and vaporizes impurities that are harmful to the manufacture of the circuit board. At this time, the glass fiber is also decomposed and vaporized on the same principle. Since the plasma-based method is a dry method, there is no waste water generation and no liquid management is required, which facilitates work management.

Next, the process of laminating | stacking copper foil on an insulating layer upper part after a plasma process is continued. Lay-up the copper foil to the conductor bump penetrating the insulating layer and put it in the press with the heated roller to melt and harden the insulator by high pressure and high temperature so that the bump and the copper foil can be electrically connected. Allow it to bond.

Referring to FIG. 4E, the copper foil is patterned to form an outer circuit pattern 150 electrically connected to the bumps 130 on the surface of the insulating layer 140 to complete the multilayer printed circuit board.

As such, by treating the surface of the insulating layer 140 using an etch back process and a plasma treatment process after the piercing process, the thickness of the copper foil layer is increased by laminating and plating an RCC or the like on a core substrate as in the prior art. Since does not occur, a process such as additional plating is unnecessary.

In addition, since the organic resin or glass fibers remaining on the bump top after the piercing process are removed by an etch back process and a plasma process, the contact failure between the bumps and the circuit pattern due to the residual of the organic resin or glass fibers is prevented, and the interlayer contact reliability is improved. There is an effect that can be improved.

5 is a cross-sectional view showing a printed circuit board according to the present invention.

Referring to FIG. 5, it can be seen that the bump formed by the B2it technique and the copper foil pattern serving as the inner layer or outer layer circuit pattern are normally connected. At this time, the contact area between the copper foil pattern and the bump is increased by the etch back process and the plasma treatment process, thereby further improving the contact reliability.

Therefore, in the implementation of the outer layer circuit pattern, the thickness thereof may be adjusted to 12 to 18 μm, and a fine circuit pattern including a line / space pattern of 3 mil or less may be easily formed.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be modified in various forms, and having ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1A and 1B are cross-sectional views illustrating a via connection method according to the prior art.

2A to 2C are cross-sectional views illustrating a method of manufacturing a printed circuit board according to the prior art.

3 is a cross-sectional view showing a problem of the B2it technology according to the prior art.

4A-4E are cross-sectional views illustrating a method of manufacturing a printed circuit board using the B2it technology according to the present invention.

Figure 5 is a cross-sectional photograph showing a printed circuit board according to the present invention.

Claims (9)

Forming an inner circuit pattern on the core substrate; Forming a conical bump on the inner circuit pattern using a conductive paste; Curing the bumps; Penetrating the insulating layer on the core substrate including the bump step; Performing an etch back process on the insulating layer; Performing a plasma treatment process on a surface of the insulating layer on which the etch back process is performed; Stacking copper foil on the insulating layer; And Printed circuit board manufacturing method comprising a fine pattern comprising the step of forming the outer layer circuit pattern by patterning the laminated copper foil. The method of claim 1, The core substrate includes a blind via hole (BVH), and the BVH includes a fine pattern, wherein the PCB is connected to the bump. The method of claim 1, The bump is a printed circuit board manufacturing method comprising a fine pattern, characterized in that formed using a silver paste (silver paste). The method of claim 1, The etch back process may include microetching the surface of the insulating layer using a mixture of potassium permanganate and sodium hydroxide; And Printed circuit board manufacturing method comprising a fine pattern comprising the step of melting and removing the glass fiber exposed on the surface of the insulating layer using fluoride. The method of claim 1, The plasma processing process is a printed circuit board manufacturing method comprising a fine pattern, characterized in that using any one or more of Ar, CF ₄ , O ₂ , H ₂ plasma. The method of claim 1, Printed circuit board manufacturing method comprising a fine pattern, characterized in that the thickness of the outer circuit pattern is formed to 12 ~ 18㎛. delete delete delete

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