KR101011228B1 - Solar Cell and Method For Fabricating The Same - Google Patents

Abstract

A solar cell and a method of manufacturing the same are disclosed. A solar cell according to the present invention includes a substrate including a plurality of unit cell regions and a plurality of wiring regions located between the unit cell regions; A lower electrode formed on the unit cell area on the substrate; A lower connection electrode formed on the wiring area on the substrate and connected to the same layer as one side of the lower electrode; An optoelectronic device formed on the lower electrode; A dummy photoelectric device facing the lower connection electrode and formed on the wiring area on the substrate connected to the same layer as one side of the optoelectronic device; An upper electrode formed on the optoelectronic device and the dummy photoelectric device; A sidewall insulating layer disposed on the wiring area on the substrate and formed on a side of the dummy photoelectric device; An electrode connection layer formed on the sidewall insulating layer and electrically connecting a lower connection electrode of another unit cell region adjacent to the upper electrode; Characterized in that it comprises a.

Solar Cell, Double Nozzle, Inkjet, Tandem Structure, Polycrystalline, Crystallization

Description

Solar cell and method for manufacturing the same {Solar Cell and Method For Fabricating The Same}

The present invention relates to a solar cell and a method of manufacturing the same, and more particularly, to a solar cell and a method of manufacturing the photoelectric device is connected in series per unit cell.

The unit cell of a typical solar cell is composed of a single photovoltaic device, in order to produce a large amount of power, a single tandem photoelectric device is connected in series to obtain a required voltage, or a stack of optoelectronic devices has a good tandem with good photoelectric conversion efficiency. To form a solar cell.

However, in the series connection structure of the prior art, since the upper electrode extends to the wiring region and contacts between the unit cells are made, the side surfaces of the upper electrode and the optoelectronic device are electrically shorted to cause unnecessary leakage current. do.

In addition, an N-type or P-type semiconductor layer having a low resistance is formed between the lower electrodes of neighboring unit cells because impurities are doped in the semiconductor layer of the optoelectronic device, which may cause a short circuit, resulting in a decrease in photoelectric conversion efficiency due to leakage current. Can be.

On the other hand, in order to overcome the problems of a single photovoltaic solar cell, a double junction tandem structured solar cell in which photovoltaic devices are stacked can generate a larger amount of electricity in the same substrate area. The advantage is that improved photoelectric conversion efficiency can be obtained.

Saitoh et al., For example, used a Plasma Enhanced Chemical Vapor Deposition (PECVD) to form pin-shaped amorphous silicon (a-Si) / microcrystalline Si (μc-Si) tandem structures. A solar cell was manufactured, wherein the initial conversion efficiency was 9.4% and the stabilized conversion efficiency was 8.5% in an area of 1 cm ² .

However, the tandem silicon solar cell developed by Saitoh et al. Is difficult to mass-produce such that the deposition time is too long due to the low deposition pressure and high deposition power condition required when forming microcrystalline silicon using PECVD. The lower the lower layer due to reflection, refraction, etc. occurring in the photoelectric conversion efficiency is limited.

In addition, the tandem structure has a problem that the short circuit phenomenon is further increased in the structure in which the upper electrode is extended in series as described above because the height is increased (step difference).

Accordingly, the present invention is to solve the above problems of the prior art, to provide a solar cell and a method of manufacturing the same that can connect the photoelectric elements in series without extending the upper electrode, and insulate the photoelectric elements. The purpose is.

In addition, an object of the present invention is to provide a solar cell and a method of manufacturing the same that can insulate the lower electrode between unit cells.

In addition, an object of the present invention is to provide a tandem solar cell and a method of manufacturing the same, which employs high-quality polycrystalline silicon and receives light having a different wavelength for each stacked photoelectric device, thereby improving photoelectric conversion efficiency.

In addition, an object of the present invention is to provide a solar cell and a method for manufacturing the same, which can reduce the manufacturing cost by reducing the process in series connection between unit cells.

The object of the present invention is a substrate comprising a plurality of unit cell regions and a plurality of wiring regions located between the unit cell regions; A lower electrode formed on the unit cell area on the substrate; A lower connection electrode formed on the wiring area on the substrate and connected to the same layer as one side of the lower electrode; An optoelectronic device formed on the lower electrode; A dummy photoelectric device facing the lower connection electrode and formed on the wiring area on the substrate connected to the same layer as one side of the optoelectronic device; An upper electrode formed on the optoelectronic device and the dummy photoelectric device; A sidewall insulating layer disposed on the wiring area on the substrate and formed on a side of the dummy photoelectric device; An electrode connection layer formed on the sidewall insulating layer and electrically connecting a lower connection electrode of another unit cell region adjacent to the upper electrode; It is achieved by a solar cell comprising a.

The optoelectronic device includes a first polycrystalline semiconductor layer; A second polycrystalline semiconductor layer formed on the first polycrystalline semiconductor layer; A third polycrystalline semiconductor layer formed on the second polycrystalline semiconductor layer; A first amorphous semiconductor layer formed on the third polycrystalline semiconductor layer; A second amorphous semiconductor layer formed on the first amorphous semiconductor layer; And a third amorphous semiconductor layer formed on the second amorphous semiconductor layer. It is a solar cell comprising a.

In addition, the object of the present invention (a) providing a substrate on which a unit cell region and a wiring region is formed; (b) forming a lower electrode on the wiring region on the substrate while forming a lower electrode on the unit cell region on the substrate; (c) forming a photovoltaic device on the lower electrode and simultaneously forming a dummy photoelectric device on the wiring region on the substrate, and forming an upper electrode on the photoelectric device and the dummy photoelectric device; And (d) forming a sidewall insulating layer on the side of the dummy photoelectric device and forming an electrode connection layer formed on the sidewall insulating layer and electrically connecting the lower connection electrode of another unit cell region adjacent to the upper electrode. Making; It is also achieved by a method of manufacturing a solar cell comprising a.

The forming of the optoelectronic device in (c) may include: (a) forming a lower first amorphous semiconductor layer on the lower electrode; (b) forming a lower second amorphous semiconductor layer on the lower first amorphous semiconductor layer; (c) forming a lower third amorphous semiconductor layer on the lower second amorphous semiconductor layer; (d) crystallizing the lower first, second, and third amorphous semiconductor layers into first, second, and third polycrystalline semiconductor layers; (e) forming an upper first amorphous semiconductor layer on the third polycrystalline semiconductor layer; (f) forming an upper second amorphous semiconductor layer on the upper first amorphous semiconductor layer; And (g) forming an upper third amorphous semiconductor layer on the upper second amorphous semiconductor layer; It is a method of manufacturing a solar cell comprising a.

According to the present invention, the upper electrode is not extended to prevent unnecessary connection with the optoelectronic device, and the electrode connection layer is formed on the sidewall insulating layer to obtain a short circuit prevention effect of the optoelectronic device.

In addition, according to the present invention, a sidewall insulating layer is provided between the lower electrodes between the unit cells, thereby preventing short circuiting.

In addition, according to the present invention, it is possible to improve the photoelectric conversion efficiency by adopting high-quality polycrystalline silicon and receiving light of different wavelengths for each of the photoelectric elements stacked in duplicate.

In addition, according to the present invention, it is possible to simultaneously form different patterns of sidewall insulating layers and electrode connection layers using a double nozzle in one inkjet printing process, thereby reducing process time and cost. In addition, since different patterns are simultaneously processed in one process, defects due to foreign matter inflow, such as particles, may be reduced.

Details of the above object, technical configuration and effects according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

1A to 1E are views illustrating a method of manufacturing a solar cell according to the present invention.

2A and 2B are views illustrating a method of manufacturing the sidewall insulating layer 400 and the electrode connection layer 500 of the solar cell according to the present invention.

First, referring to FIG. 1A, a substrate 100 including a plurality of unit cell regions a and a plurality of wiring regions b positioned between the unit cell regions a is prepared. The material of the substrate 100 may be both a transparent material and an opaque material, and the material of the substrate 100 may include glass, plastic, silicon, metal, stainless steel (SUS), or the like.

In this case, the surface of the substrate 100 may be textured. Texturing is to prevent the phenomenon of deterioration due to the optical loss caused by the reflection of light incident on the substrate surface of the solar cell, and to make the surface of the substrate rough, that is, to form an uneven pattern on the substrate surface. Say that. When the surface of the substrate is roughened by texturing, the light reflected once from the surface is re-reflected to decrease the reflectance of the incident light, thereby increasing the amount of light trapped, thereby improving the photoelectric conversion efficiency of the solar cell.

In addition, an anti-reflection layer (not shown) may be further formed on the substrate 100. The anti-reflection layer serves to prevent a phenomenon in which solar light incident through the substrate 100 is not absorbed by the silicon layer and is directly reflected to the outside, thereby reducing the efficiency of the solar cell. The material of the anti-reflection layer may be silicon oxide (SiO _x ) or silicon nitride (SiN _x ), but is not limited thereto. The method of forming the reflective ring layer may include low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), and the like.

Subsequently, a lower conductive layer 110 of a conductive material is formed on the substrate 100. The material of the lower conductive layer 110 may be any one of molybdenum (Mo), tungsten (W), and molybdenum tungsten (MoW) or an alloy thereof in which electrical properties are not degraded even when a high temperature process is performed while the contact resistance is low. However, the present invention is not limited thereto, and may include copper, aluminum, titanium, and the like, which are conventional conductive materials. The lower conductive layer 110 may be formed by physical vapor deposition (PVD), such as thermal evaporation, e-beam evaporation, sputtering, and LPCVD, PECVD, and metal organic compounds. Chemical Vapor Deposition (CVD), such as Metal Organic Chemical Vapor Deposition (MOCVD).

Next, referring to FIG. 1B, the lower conductive layer 110 is patterned to form the lower electrode layer 111 of a predetermined pattern. Laser scribing, which is an etching method using a laser light source, may be used. . In this case, the lower electrode layer 111 formed in the unit cell region (a) is the lower electrode 112 and the lower electrode layer 111 formed in the wiring region (b) has a lower portion in order to explain equivalently to the electrical driving circuit of the solar cell. The description will be made by separating the connection electrode 113.

That is, the lower electrode 112 functions as an electrode of a photovoltaic device to be formed later, and the lower connection electrode 113 functions as a connection part in which the optoelectronic devices are connected in series.

Accordingly, the lower electrode 112 is formed in the unit cell region a on the substrate 100, and at the same time, the lower electrode 112 is formed in the wiring region b on the substrate 100. The lower connection electrode 113 of the pattern is formed.

Meanwhile, a reflective layer (not shown), which is a transparent conductive layer, may be further formed on the lower electrode 112. That is, the reflective layer is positioned between the lower electrode 112 and the optoelectronic device to be formed later. The reflective layer may improve the photoelectric conversion efficiency by reflecting sunlight incident from the upper side of the substrate 100 while being electrically connected to the lower electrode 112. The reflective layer is preferably AZO (ZnO: Al) in which Al is added to ZnO, but is not limited thereto. Indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), SnO may include a small amount of FSO (SnO: F) doped with F. The method of forming the reflective layer may include physical vapor deposition such as sputtering and chemical vapor deposition such as LPCVD, PECVD, and MOCVD.

In addition, the surface of the lower electrode 112 may be textured as described above to improve the photoelectric conversion efficiency of the solar cell, similar to the surface of the substrate 100.

Next, referring to FIG. 1C, the p-type and n-type semiconductor layers or the p-type, i-type, and n-type semiconductor layers may be stacked on the entire upper portion of the substrate 100. , i-type and n-type semiconductor layers were formed in this order, and a stacked silicon layer 200 may be formed using silicon, which is generally used as a semiconductor material. The silicon layer 200 may be formed by a chemical vapor deposition method such as PECVD or LPCVD, and may be an optoelectronic device capable of producing electric power using photovoltaic power generated by receiving light by a subsequent process.

Subsequently, an upper conductive layer 310 is formed on the entire upper surface of the substrate 100. The material of the upper conductive layer 310 is a transparent conductive material, but preferably any one of ITO, ZnO, IZO, AZO (ZnO: Al), and FSO (SnO: F), but is not necessarily limited thereto. The method of forming the upper conductive layer may include a physical vapor deposition method such as sputtering and a chemical vapor deposition method such as LPCVD, PECVD, and MOCVD.

Next, referring to FIG. 1D, the upper conductive layer 310 and the silicon layer 200 are patterned to simultaneously form the upper electrode 300 and the photoelectric conversion layer 210 of a predetermined pattern, using an etching method using a laser light source. Phosphor laser scribing can be used. At this time, the photoelectric conversion layer 210 formed in the unit cell region (a) is the photoelectric conversion layer 210 formed in the wiring region (b) as the photoelectric device 220 in order to explain equivalently to the electric driving circuit of the solar cell. Is divided into dummy photoelectric device 230 will be described.

That is, the photoelectric device 220 receives light to generate electric power with photovoltaic power generated while electrons and holes move to the lower electrode 112 and the upper electrode 300 to be formed later, the dummy photoelectric device 230 It does not actually generate power.

Therefore, the photoelectric device 220 is formed on the lower electrode 112, the wiring region b on the substrate 100 facing the lower connection electrode 113 and connected to the same layer as one side of the photoelectric device 220. On the dummy photoelectric device 230 is formed. At the same time, the upper electrode 300 is formed on the optoelectronic device 220 and the dummy photoelectric device 230.

A more detailed description of the optoelectronic device 220 described above will be understood by the following detailed description with reference to FIGS. 3A and 3B.

Next, referring to FIG. 1E, the sidewall insulating layer 400 positioned on the wiring area a on the substrate 100 and positioned on the side of the dummy photoelectric device 230 is formed. In addition, an electrode connection layer 500 is formed on the sidewall insulating layer 400 and electrically connects the upper electrode 300 and the lower connection electrode 113 of another neighboring unit cell region.

In this case, the sidewall insulating layer 400 and the electrode connection layer 500 may be formed at the same time in a single process. The dual inkjet printing method may be used in which different inks are sprayed by using dual nozzles. The sidewall insulating layer 400 may use any ink of a known insulating material without limitation. For example, the sidewall insulating layer 400 may be any one of silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ). The electrode connection layer 500 may be formed by using a conductive ink of a known conductive material without limitation. For example, the electrode connection layer 500 may be any one of Ag and carbon nanotubes (CNTs).

Accordingly, the side surface of the dummy photoelectric device 230 connected to the photoelectric device 220 may be electrically insulated, and may be electrically connected in series with another neighboring photoelectric device.

More specifically, referring to FIGS. 2A and 2B, the double nozzles 21 and 22 positioned in the process chamber 10 may have a height H different from the predetermined interval D and may be different from the scan unit 30. It is provided.

The double nozzles 21 and 22 spray ink of different materials on the substrate 100 along the scanning direction 40 at a constant speed. The gap D between the first nozzle 21 and the second nozzle 22 is used. ) And the position and shape of the pattern formed on the substrate 100 by the height difference (H).

That is, the sidewall insulating layer 400 is formed on the substrate 100 and the electrode connection layer 500 is formed to cover the sidewall insulating layer 400 so that two patterns can be simultaneously formed.

Therefore, since two different patterns can be simultaneously formed in one process, the number of processes and time can be shortened, and the sidewall insulating layer 400 and the electrode connection layer are simultaneously processed in one process chamber 10. Foreign matters such as particles may be prevented from flowing between the particles 500.

Meanwhile, after the sidewall insulating layer 400 and the electrode connecting layer 500 are formed by using an inkjet printing method, the sidewall insulating layer 400 and the electrode connecting layer 500 are thermally cured or UV cured. UV curing may remove the solvent and the like present in the layers. In this case, it is more preferable to use an ultraviolet curing method, and for this purpose, the scan unit 30 may include an ultraviolet irradiator (not shown). In this case, printing and ultraviolet curing of the sidewall insulating layer 400 and the electrode connecting layer 500 may be simultaneously performed in one process chamber 10.

Meanwhile, in the above, the sidewall insulating layer 400 and the electrode connecting layer 500 are formed at the same time, but the present invention is not limited thereto, and the sidewall insulating layer 400 and the electrode connecting layer 500 are sequentially formed, that is, the sidewall insulation. The electrode connection layer 500 may be formed after the layer 400 is formed first and after a predetermined time difference.

In the above detailed description, the sidewall insulating layer 400 is formed on the wiring area b on the substrate 100. The sidewalls of the dummy photoelectric device 230 and the electrode connection layer 500 connected in the same layer as the photoelectric device 220 are provided. ), The photoelectric device 220 may be prevented from being shorted, and leakage current between the lower electrodes 112 may be prevented.

In addition, when the electrode connection layer 500 is connected to the lower connection electrode 113 of the neighboring unit cell and includes the side surface of the lower connection electrode 113 to be connected, the connection area is increased to obtain better electrical reliability. It may be.

Figure 3a is a detailed view of the optoelectronic device according to the present invention.

3B is a detailed view of another form of the optoelectronic device according to the present invention.

Referring first to FIG. 3A, a lower electrode 112 is formed in the unit cell region a on the substrate 100, and three amorphous silicon layers are formed on the lower electrode 112, although not shown. In more detail, the lower first amorphous silicon layer is formed on the lower electrode 112, and then the lower second amorphous silicon layer is formed on the lower first amorphous silicon layer, and the lower first amorphous silicon layer is then formed on the lower second amorphous silicon layer. Three amorphous silicon layers are formed to form one optoelectronic device. In this case, the lower first, second and third amorphous silicon layers may be formed using a chemical vapor deposition method such as PECVD or LPCVD.

Subsequently, the lower first, second and third amorphous silicon layers are crystallized. That is, the lower first amorphous silicon layer is the first polycrystalline silicon layer 201, the lower second amorphous silicon layer is the second polycrystalline silicon layer 202, and the lower third amorphous silicon layer is the third polycrystalline silicon layer 203. Respectively).

As a result, the optoelectronic device 220 including the first, second, and third polycrystalline silicon layers 201, 202, and 203 is formed on the lower electrode 112. The optoelectronic device 220 is a structure in which a polycrystalline silicon layer is stacked and a pin diode in which p-type, i-type, and n-type polycrystalline silicon layers, which can generate power with photovoltaic power generated by receiving light, are sequentially stacked. Can be. Here, the i-type means an intrinsic semiconductor which is not doped with impurities. In the n-type or p-type doping, the dopant is preferably doped in situ during the formation of the amorphous silicon layer. Boron (B) is used as an impurity in p-type doping, and phosphorus (P) or arsenic (As) is used as an impurity in n-type doping, but the present invention is not limited thereto, and known techniques may be used without limitation.

In this case, the crystallization method of the amorphous silicon layer may be any one of a solid phase crystallization (SPC), an excimer laser annealing (ELA), a sequential lateral solidification (SLS), a metal induced crystallization (MIC), and a metal induced lateral crystallization (MILC). Can be used. Since the amorphous silicon crystallization method is a known technique, a detailed description thereof will be omitted herein.

In the above description, the lower first, second, and third amorphous silicon layers are all formed, but the crystallization is performed simultaneously. However, the present invention is not limited thereto. For example, the crystallization process may be performed separately for each lower amorphous silicon layer, and the two lower amorphous silicon layers may be simultaneously crystallized, and the other lower amorphous silicon layer may be separately crystallized.

In addition, the first polycrystalline silicon layer 201, the second polycrystalline silicon layer 202, and the third polycrystalline silicon layer 203 may further perform a defect removal process to further improve the properties of the polycrystalline silicon. In the present invention, the polycrystalline silicon layer may be subjected to high temperature heat treatment or hydrogen plasma treatment to remove defects (eg, impurities and dangling bonds) present in the polycrystalline silicon layer.

Next, referring to FIG. 3B, the optoelectronic device 220 may have a stacked structure of two first and second optoelectronic devices 204 and 208. In more detail, after forming the same stacked structure as in FIG. 2A, an optoelectronic device is further formed on the third polycrystalline silicon layer 203, and the upper first amorphous silicon layer 205 is formed on the third polycrystalline silicon layer 203. ), Followed by forming an upper second amorphous silicon layer 206 on the upper first amorphous silicon layer 205, and then forming an upper third amorphous silicon layer 207 on the upper second amorphous silicon layer 206. The second photoelectric device 208 may be formed. In this case, the upper first, second, and third amorphous silicon layers 205, 206, and 207 may be formed using chemical vapor deposition such as PECVD or LPCVD.

Although not shown, a connection layer (not shown), which is a transparent conductor, may be further formed on the third polycrystalline silicon layer 203. The connection layer allows a tunnel junction between the third polycrystalline silicon layer 203 and the upper first amorphous semiconductor layer 205, resulting in better photoelectric conversion efficiency of the solar cell. In this case, the connection layer is preferably AZO (ZnO: Al) in which a small amount of Al is added to ZnO, but is not necessarily limited thereto, and a transparent conductive material such as conventional ITO, ZnO, IZO, and FSO (SnO: F) may be used. have.

As a result, a tandem solar cell composed of a first photovoltaic device 204 made of a polycrystalline silicon layer and a second photovoltaic device 208 made of an amorphous silicon layer can be obtained. At this time, since the first photoelectric device 204 is made of a polycrystalline silicon layer, the photoelectric conversion efficiency is good with respect to the long wavelength light, and since the second photoelectric device 208 is made of an amorphous silicon layer, the photoelectric conversion is performed with respect to the short wavelength light. Since the conversion efficiency is good, the tandem structured solar cell according to the present invention can absorb light in various wavelength bands, thereby improving the photoelectric conversion efficiency.

In addition, the tandem structured solar cell of the present invention has an advantage in that deterioration characteristics are superior to that of a conventional tandem structured solar cell employing microcrystalline silicon (by which deterioration does not proceed well) by employing high quality polycrystalline silicon. That is, due to the characteristics of silicon, amorphous silicon has poor deterioration characteristics, and unlike microcrystalline silicon, almost no amorphous silicon is present in polycrystalline silicon, and thus, the tandem structure of the present invention deteriorates well with use. It doesn't work.

In the present invention, the structure of the photoelectric device 220, that is, the first and second photoelectric devices 204 and 208 may be formed in four arrangements as follows. The meaning of + and-below indicates the relative difference in doping concentration and means that + has a higher concentration of doping than-. For example, n + is higher doped than n-. In addition, when there is no indication of + or-, it means that there is no particular limitation of the doping concentration.

First, the first, second, and third polycrystalline silicon layers 201, 202, and 203 have conductivity types n, i, and p, respectively, and the upper first, second, and third amorphous silicon layers 205, 206, 207 may be n, i, or p, respectively. In this case, the first, second, and third polycrystalline silicon layers 201, 202, and 203 may have n +, i, and p + conductivity types, respectively.

Second, the first, second, and third polycrystalline silicon layers 201, 202, and 203 have conductivity types n, n, and p, respectively, and the upper first, second, and third amorphous silicon layers 205, 206, 207 may be n, i, or p, respectively. In this case, the first, second, and third polycrystalline silicon layers 201, 202, and 203 may have n +, n−, and p + conductivity types, respectively.

Third, the first, second, and third polycrystalline silicon layers 201, 202, and 203 have conductivity types p, i, and n, respectively, and the upper first, second, and third amorphous silicon layers 205, 206, 207 may be p, i and n, respectively. In this case, the first, second, and third polycrystalline silicon layers 201, 202, and 203 are more preferably conductive types p +, i, and n +, respectively.

Fourth, the first, second, and third polycrystalline silicon layers 201, 202, and 203 have p, p, and n conductivity types, respectively, and the upper first, second, and third amorphous silicon layers 205, 206, 207 may be p, i and n, respectively. In this case, the first, second, and third polycrystalline silicon layers 201, 202, and 203 are more preferably conductive types p +, p-, and n +, respectively.

In the above detailed description, a tandem structure in which the first and second optoelectronic devices 204 and 208 are stacked has been described as an example, but if necessary, the optoelectronic devices may be stacked in double or more, and a pn type, not a pin type, may be used. Can also be used.

In the above detailed description, a tandem structure in which the first and second optoelectronic devices 200 and 300 are stacked has been described as an example, but a plurality of optoelectronic devices may be stacked as necessary.

Although the present invention has been shown and described with reference to preferred embodiments as described above, it is not limited to the above embodiments and various modifications made by those skilled in the art without departing from the spirit of the present invention. Modifications and variations are possible. Such modifications and variations are intended to fall within the scope of the invention and the appended claims.

1a to 1e is a view showing a manufacturing method of a solar cell according to the present invention.

2A and 2B illustrate a method of manufacturing the sidewall insulating layer 400 and the electrode connection layer 500 of the solar cell according to the present invention.

Figure 3a is a detailed view of the optoelectronic device according to the present invention.

Figure 3b is a detailed view of another form of the optoelectronic device according to the present invention.

<Brief description of the major reference numerals>

10: process chamber

21: first nozzle

22: second nozzle

40: Scan direction

100: substrate

111: lower electrode layer

112: lower electrode

113: lower connection electrode

201: first polycrystalline silicon layer

202: second polycrystalline silicon layer

203: third polycrystalline silicon layer

205: upper first amorphous silicon layer

206: upper second amorphous silicon layer

207: upper third amorphous silicon layer

220: photoelectric device

230: dummy photoelectric device

300: upper electrode

400: sidewall insulation layer

500: electrode connection layer

Claims (23)

A substrate including a plurality of unit cell regions and a plurality of wiring regions positioned between the unit cell regions; A lower electrode formed on the unit cell area on the substrate; A lower connection electrode formed on the wiring area on the substrate and connected to the same layer as one side of the lower electrode; An optoelectronic device formed on the lower electrode; A dummy photoelectric device facing the lower connection electrode and formed on the wiring area on the substrate connected to the same layer as one side of the optoelectronic device; An upper electrode formed on the optoelectronic device and the dummy photoelectric device; A sidewall insulating layer disposed on the wiring area on the substrate and formed on a side of the dummy photoelectric device; And An electrode connection layer formed on the sidewall insulating layer and electrically connecting a lower connection electrode of another unit cell region adjacent to the upper electrode; Including; The optoelectronic device includes a first polycrystalline semiconductor layer; A second polycrystalline semiconductor layer formed on the first polycrystalline semiconductor layer; And a third polycrystalline semiconductor layer formed on the second polycrystalline semiconductor layer. The method of claim 1, The electrode connection layer is a solar cell, characterized in that the conductor. The method of claim 1, The sidewall insulating layer is any one of silicon nitride (SiN _x ), silicon oxide (SiO ₂ ). The method of claim 1, The side wall insulating layer and the electrode connection layer is a solar cell, characterized in that formed by the inkjet printing method of a double nozzle. delete The method of claim 1, The optoelectronic device may include a first amorphous semiconductor layer formed on the third polycrystalline semiconductor layer; A second amorphous semiconductor layer formed on the first amorphous semiconductor layer; And a third amorphous semiconductor layer formed on the second amorphous semiconductor layer. The method of claim 6, And the first, second and third polycrystalline semiconductor layers are n, i and p, respectively, and the first, second and third amorphous semiconductor layers are n, i and p, respectively. The method of claim 6, The first, second, and third polycrystalline semiconductor layers are n, n, and p, and the first, second, and third amorphous semiconductor layers are n, i, and p. The method of claim 6, And wherein the first, second and third polycrystalline semiconductor layers are p, i and n, and the first, second and third amorphous semiconductor layers are p, i and n. The method of claim 6, And wherein the first, second and third polycrystalline semiconductor layers are p, p and n, and the first, second and third amorphous semiconductor layers are p, i and n. The method of claim 1, Each of the first, second, and third polycrystalline semiconductor layers includes solid phase crystallization (SPC), excimer laser annealing (ELA), sequential lateral solidification (SLS), metal induced crystallization (MIC), and metal induced lateral crystallization (MILC), respectively. Solar cell, characterized in that crystallized by any one of the methods. 7. The method according to claim 1 or 6, The first, second, third polycrystalline semiconductor layer is a solar cell, characterized in that the polycrystalline silicon layer. The method of claim 6, The first, second, and third amorphous semiconductor layers are amorphous silicon layers. 7. The method according to claim 1 or 6, And a reflective layer, which is a transparent conductor, is further formed between the lower electrode and the first polycrystalline semiconductor layer. The method of claim 6, And a connection layer, which is a transparent conductor, is further formed between the third polycrystalline semiconductor layer and the first amorphous semiconductor layer. (a) providing a substrate on which unit cell regions and wiring regions are formed; (b) forming a lower electrode on the wiring region on the substrate while forming a lower electrode on the unit cell region on the substrate; (c) forming a photovoltaic device on the lower electrode and simultaneously forming a dummy photoelectric device on the wiring region on the substrate, and forming an upper electrode on the photoelectric device and the dummy photoelectric device; And (d) forming a sidewall insulating layer on the side of the dummy photoelectric device and forming an electrode connecting layer formed on the sidewall insulating layer and electrically connecting the lower connection electrode of another unit cell region adjacent to the upper electrode; step; Including, In the step (c), the forming of the optoelectronic device may include: (a) forming a lower first amorphous semiconductor layer on the lower electrode; (b) forming a lower second amorphous semiconductor layer on the lower first amorphous semiconductor layer; (c) forming a lower third amorphous semiconductor layer on the lower second amorphous semiconductor layer; And (d) crystallizing the lower first, second and third amorphous semiconductor layers into first, second and third polycrystalline semiconductor layers. delete The method of claim 16, In the step (c), the forming of the optoelectronic device may include forming an upper first amorphous semiconductor layer on the third polycrystalline semiconductor layer; Forming an upper second amorphous semiconductor layer on the upper first amorphous semiconductor layer; And forming an upper third amorphous semiconductor layer on the upper second amorphous semiconductor layer. The method of claim 16, The side wall insulating layer and the electrode connecting layer is a solar cell manufacturing method, characterized in that formed in the inkjet printing method by a double nozzle in the same process. The method of claim 19, The double nozzle has a different height manufacturing method of the solar cell, characterized in that The method of claim 16, The crystallization may be performed by any one of methods of solid phase crystallization (SPC), excimer laser annealing (ELA), sequential lateral solidification (SLS), metal induced crystallization (MIC), and metal induced lateral crystallization (MILC). Method for manufacturing a solar cell. The method according to claim 16 or 18, The first, second, third polycrystalline semiconductor layer is a method of manufacturing a solar cell, characterized in that formed of a polycrystalline silicon layer. The method of claim 18, The first, second and third amorphous semiconductor layer is a method of manufacturing a solar cell, characterized in that formed of an amorphous silicon layer.

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