KR101072531B1

KR101072531B1 - Solar cell and method for fabricating the same

Info

Publication number: KR101072531B1
Application number: KR1020100007540A
Authority: KR
Inventors: 이영호; 이유진; 이시우; 김동제
Original assignee: 주식회사 티지솔라
Priority date: 2010-01-27
Filing date: 2010-01-27
Publication date: 2011-10-11
Also published as: KR20110087895A

Abstract

A solar cell and a method of manufacturing the same are disclosed. A solar cell according to the present invention includes a substrate 100 including a plurality of unit cell regions (a) and a plurality of wiring regions (b) positioned between the unit cell regions (a); A lower electrode 200a formed on the unit cell region a on the substrate 100; A lower connection electrode 200b formed on the wiring area b on the substrate 100 and connected to one side of the lower electrode 200a in the same layer; An optoelectronic device portion 300a formed on the lower electrode 200a and having a plurality of semiconductor layers stacked thereon; A dummy photoelectric device 300b formed on the lower connection electrode 200b in the same layer as the photoelectric device part 300a and having a portion of the semiconductor layer patterned thereon; And an upper electrode 500 formed on the optoelectronic device portion 300a and formed on the patterned dummy photoelectric device 300b and electrically connected to the optoelectronic device portion 300a of the neighboring unit cell region a. Characterized in that it comprises a.

Description

SOLAR CELL AND METHOD FOR FABRICATING THE SAME

The present invention relates to a solar cell and a method of manufacturing the same. More specifically, the number of pattern processes can be reduced by collectively patterning the lower electrode and the semiconductor layer, and only a part of the upper electrode and the semiconductor layer (for example, the n-type semiconductor layer) can be removed to efficiently form a series method. The present invention relates to a solar cell and a method of manufacturing the same.

Conventional thin film solar cells have a variety of difficulties in actual commercialization because the photoelectric conversion efficiency is less than about 10%. In order to solve this problem, a technique for realizing excellent photoelectric conversion efficiency by connecting a plurality of photoelectric devices in series has been developed.

Looking at a general series solar cell, a method of forming a tandem structure to obtain a good photoelectric conversion efficiency by stacking photoelectric devices, and connecting a plurality of horizontally arranged photoelectric devices in series with electrodes (wiring) The typical method is to obtain the required power.

First, a solar cell having a tandem structure has an advantage in that a larger amount of electricity can be produced in the same substrate area, thereby obtaining an improved photoelectric conversion efficiency than a conventional single junction solar cell. Saitoh et al., For example, used a Plasma Enhanced Chemical Vapor Deposition (PECVD) to form pin-type amorphous silicon (a-Si) / microcrystalline Si (μc-Si) tandem structures. A solar cell was manufactured, wherein the initial conversion efficiency was 9.4% and the stabilized conversion efficiency was 8.5% in an area of 1 cm ² .

However, the tandem silicon solar cell developed by Saitoh et al. Requires low deposition pressure and high deposition power conditions when forming microcrystalline silicon using PECVD. Therefore, deposition time becomes too long, process conditions are difficult to match, and mass-production efficiency is low. In addition, there is a limit in that the photoelectric conversion efficiency is lowered toward the lower layer due to reflection, refraction or the like occurring between the plurality of layers.

Next, referring to a conventional solar cell of the series connection method, Figure 1 is a view showing the configuration of a conventional solar cell.

Referring to FIG. 1, a conventional solar cell is provided with a substrate 10 including a plurality of unit cell regions a ′ and a wiring region b ′ positioned between the unit cell regions a ′. In this case, the lower electrode 11 is formed in the unit cell region a` on the substrate 10, and the optoelectronic device 20 having the semiconductor layer stacked thereon is formed on the lower electrode 11.

Subsequently, the upper electrode 30 is formed on the optoelectronic device 20 to form one solar cell unit cell, and the upper electrode 30 is interconnected with an upper portion of the lower electrode 11 of another neighboring unit cell a ′. They are connected on area b` and connected electrically in series.

However, in the conventional series solar cell, when the connection between the unit cells of the solar cell is made in the wiring area b`, the side surface of the photoelectric device 20 and the upper electrode 30 are short-circuited (Short Circuit: SC) to prevent unnecessary leakage. Current may occur. In addition, an n-type or p-type semiconductor layer having a low resistance is formed between the lower electrodes 11 of neighboring unit cells due to the doping of impurities in the semiconductor layer of the optoelectronic device 20. Circuit) may cause a decrease in the photoelectric conversion efficiency.

In particular, in the conventional solar cell, after the first pattern of the lower electrode 11 is formed by the laser scribing method, the photovoltaic device 20 is formed, and only the optoelectronic device 20 is formed by the laser scribing method. do. Subsequently, the upper electrode 30 may be formed, and the upper electrode 30 and the photoelectric device 20 may be third patterned by a laser scribing method to implement a solar cell.

Therefore, the conventional solar cell requires at least three laser scribing processes, which increases the processing time and cost, and reduces the area ratio of the unit cell area (i.e., increases the wiring (dead) area of the solar cell). The photoelectric conversion efficiency is lowered. In this case, in the case of the third pattern, since the upper electrode 30 and the photoelectric device 20 are formed of different materials, there is a problem that it is difficult to collectively remove them by laser scribing.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and the number of pattern processes can be reduced by collectively patterning the lower electrode and the semiconductor layer (for example, laser scribing). It is an object to provide a solar cell and a method of manufacturing the same.

In addition, an object of the present invention is to provide a solar cell having a simpler process and structure and a method of manufacturing the same by removing only a portion (eg, an n-type semiconductor layer) of the upper electrode and the semiconductor layer.

The object of the present invention is a substrate comprising a plurality of unit cell regions and a plurality of wiring regions located between the unit cell regions; A lower electrode formed on the unit cell area on the substrate; A lower connection electrode formed on the wiring area on the substrate and connected to the same layer as one side of the lower electrode; An optoelectronic device portion formed on the lower electrode and having a plurality of semiconductor layers stacked thereon; A dummy photoelectric device formed on the lower connection electrode in the same layer as the optoelectronic device portion and having a portion of the semiconductor layer patterned thereon; And an upper electrode formed on the optoelectronic device portion, the upper electrode being formed on the patterned dummy photoelectric device and electrically connected to the optoelectronic device portion of a neighboring unit cell region. .

In this case, the lower electrode and the optoelectronic device portion may be collectively patterned.

The semiconductor layer may be a semiconductor layer having the least resistance among the stacked semiconductor layers.

The partial semiconductor layer may be an n-type semiconductor layer.

A sidewall insulating layer may be further formed on the wiring area on the substrate and disposed between the lower electrode and the side surface of the optoelectronic device portion and the upper electrode.

In addition, the object of the present invention (a) providing a substrate including a plurality of unit cell region and a plurality of wiring region located between the unit cell region; (b) sequentially forming a lower conductive layer and a plurality of semiconductor layers on the entire surface of the substrate; (c) collectively first patterning the lower conductive layer and the semiconductor layer on the wiring region on the substrate; (d) forming an upper conductive layer on the entire surface of the substrate; And (e) second patterning a portion of the upper conductive layer and the patterned semiconductor layer on the wiring region on the substrate, the second patterning of the semiconductor layer.

In this case, the first patterning may be performed using laser scribing.

The second patterning may be performed using laser scribing or mechanical scribing.

The partial semiconductor layer may be an n-type semiconductor layer.

In the step (c), the method may further include forming a sidewall insulating layer in contact with the sidewalls of the patterned lower conductive layer and the patterned semiconductor layer on the wiring area on the substrate.

According to the present invention, the lower electrode and the semiconductor layer are collectively patterned to reduce the number of pattern processes, the process time and the process cost, and to increase the area of the unit cell region.

In addition, according to the present invention, only a part of the upper electrode and the semiconductor layer (for example, the n-type semiconductor layer having the least resistance among the p-, i-, and n-type semiconductor layers) is removed, thereby simplifying the process and structure, and simultaneously connecting in series. It is possible to effectively prevent a short circuit occurring at the time of.

1 is a view showing the configuration of a conventional solar cell.
2 to 6 are views sequentially showing a manufacturing process of a solar cell according to an embodiment of the present invention.
7 is a view illustrating a detailed configuration of an optoelectronic device portion according to an embodiment of the present invention.
8 is a view showing the detailed configuration of another type of optoelectronic device portion according to an embodiment of the present invention.

DETAILED DESCRIPTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. In the drawings, like reference numerals refer to the same or similar functions throughout the several aspects, and length, area, thickness, and the like may be exaggerated for convenience.

DETAILED DESCRIPTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

In the present specification, the unit cell region (a) refers to a region in which a photoelectric device (semiconductor layer) is positioned in the solar cell to perform photoelectric conversion.

In addition, in the present specification, the wiring area (b) refers to an area that is located between the unit cell areas (a) and performs a function of electrically connecting (eg, a series connection method) while separating the unit cells. Meaning, it can be understood as a dead region since substantially no photoelectric conversion occurs.

In addition, in the present specification, the optoelectronic device portion is meant to encompass that one optoelectronic device or a plurality of optoelectronic devices are stacked.

2 to 6 are views sequentially showing a manufacturing process of a solar cell according to an embodiment of the present invention.

First, referring to FIG. 2, a substrate 100 including a plurality of unit cell regions a and a plurality of wiring regions b positioned between the unit cell regions a may be provided. The material of the substrate 100 may be a transparent glass substrate, but is not limited thereto, and may be a transparent material such as glass or plastic or silicon or metal [for example, SUS (Stainless Steel) according to a direction in which solar cells receive light. All opaque materials such as)] can be used.

In this case, texturing may be performed on the surface of the substrate 100. Texturing in the present invention is intended to prevent the phenomenon that the characteristics of the light is reduced by reflecting the light incident on the substrate surface of the solar cell is optically lost. In other words, the surface of the substrate is roughened to form an uneven pattern (not shown) on the surface of the substrate. For example, if the surface of the substrate is roughened by texturing, the light reflected once from the surface may be reflected back toward the solar cell, thereby reducing the loss of light and increasing the amount of light trapping to increase the photoelectric conversion efficiency of the solar cell. Can be improved.

In this case, a sand blasting method may be used as a representative texturing method. Sand blasting in the present invention includes both dry blasting for etching by etching the etching particles with compressed air and wet blasting for etching by etching the etching particles together with the liquid. On the other hand, the etching particles used in the sand blasting of the present invention can be used without limitation, particles that can form irregularities on the substrate by physical impact, such as sand, small metal.

Subsequently, an antireflection layer (not shown) may be formed on the substrate 100. The anti-reflection layer serves to prevent a phenomenon of decreasing the efficiency of the solar cell by being reflected directly to the outside rather than being absorbed by the photovoltaic device incident to the photovoltaic device. The material of the anti-reflection layer may be silicon oxide (SiO _x ) or silicon nitride (SiN _x ), but is not limited thereto.

The method of forming the reflective ring layer may include low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), and the like.

Subsequently, a lower conductive layer 200 of a conductive material may be formed on the entire upper surface of the substrate 100. The material of the lower conductive layer 200 may use a transparent or opaque conductive material without limitation, depending on the direction of receiving light. For example, TCO (Transparent Conductive Oxide), which is a transparent electrode having a low contact resistance and having a transparent property, may be used. For example, AZO (ZnO: Al), ITO (Indium-Tin-Oxide), or GZO (ZnO: Ga ), BZO (ZnO: B), and SnO ₂ (SnO ₂ : F). In addition, any one of opaque molybdenum (Mo), tungsten (W), molybdenum tungsten (MoW) or an alloy thereof may be included.

The lower conductive layer 200 may be formed using physical vapor deposition (PVD), LPCVD, PECVD, metal organic compounds, such as thermal evaporation, E-beam evaporation, and sputtering. Chemical Vapor Deposition (CVD), such as Metal Organic Chemical Vapor Deposition (MOCVD).

Subsequently, a semiconductor layer 300 having p-type and n-type conductivity may be stacked on the upper entire surface of the lower conductive layer 200, or p-type, i-type, and n-type semiconductor layers 300 may be stacked. In an embodiment of the present invention, the p-type, i-type, and n-type semiconductor layers 300 may be formed in order, and the material of the semiconductor layer 300 may be silicon (Si) that is commonly used. Hereinafter, a description will be given assuming that p-type, i-type, and n-type silicon layers 300 are stacked.

The silicon layer 300 may be formed by a chemical vapor deposition method such as PECVD or LPCVD, and may perform a function of an optoelectronic device that may receive power in the unit cell region (a) to produce power by a subsequent process. This will be described in detail with reference to the following detailed description with reference to FIGS. 7 and 8.

Next, referring to FIG. 3, the lower conductive layer 200 and the silicon layer 300 are collectively first patterned 10 in the wiring region b to form a predetermined unit pattern separated from each other (isolated). Can be.

The first patterning 10 may be performed using a laser scribing method, which is an etching method using a laser light source. The laser may use an infrared ray-nanosecond (IR-ns) or infrared ray-picosecond (IR-ps) laser. Patterning may be simultaneously performed through a mechanism for popping the silicon layer 300 during blow-up of the lower conductive layer 200 by laser irradiation. In this case, the irradiation direction of the laser may be irradiated directly from the top, it may be irradiated from the bottom through the substrate 100. However, the present invention is not limited thereto, and an etching method including a known photolithography method may be used without limitation.

In the following description, the patterned lower conductive layer 200 is a lower electrode 200a on the unit cell region a and the lower connection electrode 200b on the wiring region b in order to be equivalently described with the driving circuit of the solar cell. Explain separately. In the same principle, the patterned silicon layer 300 is divided into the optoelectronic device portion 300a on the unit cell region a and the dummy photoelectric device 300b on the wiring region b.

The photoelectric device unit 300a generates photovoltaic power (power) while electrons and holes generated by receiving light move to the lower electrode 200a and the upper electrode 500 to be formed later. On the other hand, the dummy photoelectric device 300b is electrically separated from the photoelectric device part 300a (the upper electrode is patterned) or physically separated (the photoelectric device part is patterned) by a process (see FIG. 6). Practically no power.

The lower connection electrode 200b has a function of connecting the lower electrode 200a of the unit cell region a with the upper electrode 500 of another unit cell region a adjacent thereto to implement a series connection structure of a solar cell. Can be performed.

Next, referring to FIG. 4, the sidewall insulating layer 400 may be formed on the side surfaces of the optoelectronic device portion 300a and the lower electrode 200a and the wiring area b. The sidewall insulating layer 400 may be any one of a silicon nitride film (SiN _x ) or a silicon oxide film (SiO _x ) or a laminated film thereof. In addition, the sidewall insulating layer 400 may be various known materials such as resin and polymer. By the sidewall insulating layer 400, good electrical insulating properties between solar cell unit cells may be obtained.

The method of forming the sidewall insulating layer 400 may use ink jet printing in which ink is sprayed through a head configured as a nozzle, but is not limited thereto, and the photolithography method is not limited thereto. Can be used.

Next, referring to FIG. 5, an upper conductive layer 510 of a conductive material may be formed on the entire upper surface of the substrate 100. The material of the upper conductive layer 510 may use a transparent or opaque conductive material without limitation, depending on the direction of receiving light. For example, a transparent conductive oxide (TCO), which is a transparent conductive material, or a metal such as copper (Cu), aluminum (Al), titanium (Ti), silver (Ag), or an alloy thereof, which is a conventional conductive material. have. In addition, the upper conductive layer 510 may be formed in a laminated film structure in which a TCO film and a metal film are stacked.

The method of forming the upper conductive layer 510 may include a physical vapor deposition method such as sputtering and a chemical vapor deposition method such as LPCVD, PECVD, and MOCVD.

Next, referring to FIG. 6, only a portion of the upper conductive layer 510 and the patterned silicon layer 300 on the wiring region b is second patterned 20 to form the upper electrode 500 and the dummy photoelectric device 300b. ) Can be formed respectively.

The second patterning 20 may be performed by using a laser scribing method, which is an etching method using a laser light source. In this case, the irradiation direction of the laser may be directly irradiated on the substrate 100. . In addition, in the present invention, the second patterning 20 may be performed by using a mechanical scribing method instead of the laser scribing method, in which a known mechanical scribing method may be used without limitation. Can be. However, the present invention is not limited thereto, and an etching method including a known photolithography method may be used without limitation.

In more detail, among the patterned silicon layer 300 in which p-type, i-type, and n-type silicon layers are sequentially stacked, the n-type semiconductor layer having the smallest resistance is collectively removed together with the upper conductive layer 510. As a result, the series connection structure of the second patterning process 20 and the solar cell can be simplified.

Meanwhile, the upper electrode 500 is formed on the optoelectronic device portion 300a, and is formed on the dummy photoelectric device 300b at regular intervals by the second patterning 20 so that the adjacent unit cell regions a are adjacent to each other. May be electrically connected in series with the optoelectronic device portion 300a.

In this case, the dummy photoelectric device 300b may be formed on the lower connection electrode 200b in the same layer as the photoelectric device unit 300a except for the patterned silicon layer (eg, the n-type semiconductor layer). Although the dummy photoelectric device 300b is physically the same layer, since the upper electrode 500 is electrically patterned, the dummy photoelectric device 300b may be interpreted as being electrically separated from the photoelectric device part 300a.

In addition, the upper electrode 500 may function as an electrode of the optoelectronic device portion 300a on the unit cell region a, and another optoelectronic device portion adjacent to the optoelectronic device portion 300a on the wiring region b. The wire may be connected to the 300a (ie, to connect the solar cell unit cells in series). In the present invention, the upper surface of the lower connection electrode 200b of the other wiring region b adjacent to the upper surface of the photoelectric device portion 300a of the unit cell region a is electrically connected through the upper electrode 500.

As described above, the solar cell according to the exemplary embodiment of the present invention may reduce the number of pattern processes compared to the conventional three times by performing only two pattern processes 10 and 20 in total. That is, since the solar cell of the present invention patterns the lower conductive layer 200 and the silicon layer 300 collectively, the area of the unit cell region a is relatively increased (that is, the wiring (dead) region b). ) Area can be reduced], excellent photoelectric conversion efficiency can be obtained.

In addition, only a part of the silicon layer 300 of the upper electrode 500 and the dummy photoelectric device 300b (for example, the n-type semiconductor layer having the least resistance among the p-, i-, and n-type semiconductor layers) is removed, thereby removing the solar cell. In addition to simplifying the manufacturing process and the series connection structure of the above, it is possible to effectively prevent the short-circuit phenomenon occurring during the series connection in the above-described prior art. This is because only the relatively low resistance n-type semiconductor layer is patterned and the relatively high resistance p-type and i-type semiconductor layers are left.

As a result, in the present invention, only the n-type silicon layer having a relatively low resistance of the dummy photoelectric device 300b is patterned, so that the upper electrode 500 of the unit cell region a is the dummy photoelectric device 300b of the wiring region b. By allowing only the i-type and p-type silicon layers having a relatively high resistance among the silicon layers 300), a series connection structure of a solar cell can be implemented in a simple and cost-saving manner.

Optoelectronic device Configuration

7 is a view illustrating a detailed configuration of an optoelectronic device portion according to an embodiment of the present invention.

Referring to FIG. 7, the optoelectronic device portion 300a formed on the unit cell region a of the substrate 100 may be a polycrystalline optoelectronic device 310. In more detail, although not shown, a first amorphous silicon layer (not shown) is formed on the lower electrode 200a on the substrate 100, and then a second amorphous silicon layer (not shown) is formed on the first amorphous silicon layer. ), And a third amorphous silicon layer (not shown) may be formed on the second amorphous silicon layer to form one optoelectronic device. In this case, the first, second and third amorphous silicon layers may be formed using a CVD method such as PECVD or LPCVD.

Subsequently, the first, second, and third amorphous silicon layers may be subjected to high temperature heat treatment to crystallize. That is, the first amorphous silicon layer is the first polycrystalline silicon layer 311, the second amorphous silicon layer is the second polycrystalline silicon layer 312, and the third amorphous silicon layer is the third polycrystalline silicon layer 313, respectively. Can be crystallized. As a result, the polycrystalline optoelectronic device 310 including the first, second, and third polycrystalline silicon layers 311, 312, and 313 may be formed.

Crystallization methods of the first, second, and third amorphous silicon layers include solid phase crystallization (SPC), excimer laser annealing (ELA), sequential lateral solidification (SLS), metal induced crystallization (MIC), and metal induced lateral crystallization (MILC). Can be used. Since the crystallization method of such amorphous silicon is a known technique, a detailed description thereof will be omitted herein.

In the above description, the first, second, and third amorphous silicon layers are all formed, but the crystallization is performed simultaneously. However, the present invention is not limited thereto. For example, the crystallization process may be performed separately for each amorphous silicon layer, and the two amorphous silicon layers may simultaneously undergo a crystallization process and the other amorphous silicon layer may be separately crystallized.

The polycrystalline photovoltaic device 310 may have a structure of a p-i-n diode in which p-type, i-type, and n-type polycrystalline silicon layers, which may generate power with photovoltaic power generated by receiving light, are sequentially stacked. Where i means intrinsic without impurities. In addition, in the n-type or p-type doping, it is preferable to dope the impurities in situ when forming the amorphous silicon layer. It is common to use boron (B) as an impurity in P-type doping and phosphorus (P) or arsenic (As) as an impurity in n-type doping, but it is not limited to this, and well-known techniques can be used without limitation.

On the other hand, in addition to p, i, n type, the polycrystalline photoelectric device 310 is p +, i, n + type, n, i, p type (especially n +, i, p +), p, n, n type (especially p +, p-, n +) or n, n, p-type (especially n +, n-, p +) silicon layers. Here, the meaning of + and-represents a relative difference in doping concentration, and means that + has a higher concentration of doping than-. For example, n + is higher doped than n−. If there is no indication of + or-, there is no particular restriction on the doping concentration. In addition, the semiconductor layer located between p and n type functions as a light absorbing layer (for example, i type).

Although not shown, a defect removal process may be further performed to further improve the properties of the polycrystalline silicon layers 311, 312, and 313. In the present invention, the polycrystalline silicon layer may be subjected to high temperature heat treatment or hydrogen plasma treatment to remove defects (eg, impurities and dangling bonds) present in the polycrystalline silicon layer.

On the other hand, if the photoelectric device portion 300a of FIG. 7 is applied to the solar cell of FIG. 6 as an example, in the present invention, the first polycrystalline silicon layer 311 and the lower electrode 200a of any unit cell of the solar cell are The lower electrode 200a is connected to the lower connection electrode 200b, the lower connection electrode 200b is connected to the upper electrode 500, and the upper electrode 500 is connected to the adjacent cell of the unit cell. Electrical connection between the unit cells connected to the third polycrystalline silicon layer 313 is realized. Therefore, when the optoelectronic device portion 300a has a structure in which p, i and n type polycrystalline silicon layers are stacked, the p-type polycrystalline silicon layer and the n-type polycrystalline silicon layer are electrically connected directly between unit cells. Solar cells can be implemented.

8 is a view showing the detailed configuration of another type of optoelectronic device portion according to an embodiment of the present invention.

Referring to FIG. 8, another optoelectronic device 310 may be further formed on the polycrystalline optoelectronic device 310 including the first, second, and third polycrystalline silicon layers 311, 312, and 313 described above. The optoelectronic device may be an amorphous optoelectronic device 320 in which upper first, second, and third amorphous silicon layers 321, 322, and 323, which are amorphous silicon layers, are stacked. As described above, according to the exemplary embodiment of the present invention, the optoelectronic device portion 300a in which the optoelectronic devices 310 and 320 have a tandem structure may be implemented. On the other hand, such a tandem structure may mean a multi-junction structure in which the photoelectric device is stacked in triple or more.

Although not shown, a connection layer (not shown), which is a transparent conductor, may be further formed between the polycrystalline optoelectronic device 310 and the amorphous optoelectronic device 320. The connection layer allows a tunnel junction between the polycrystalline optoelectronic device 310 and the amorphous optoelectronic device 320 to serve to improve photoelectric conversion efficiency of the solar cell. The connection layer is preferably AZO (ZnO: Al) in which a small amount of Al is added to ZnO, but is not limited thereto. A transparent conductive material such as ITO, ZnO, IZO, and FSO (SnO: F) may be used without particular limitation. Can be.

In the foregoing detailed description, the present invention has been described by specific embodiments such as specific components and the like, but the embodiments and drawings are provided only to help a more general understanding of the present invention, and the present invention is limited to the above embodiments. However, one of ordinary skill in the art can make various modifications and variations from this description. Therefore, the spirit of the present invention should not be construed as being limited to the above-described embodiments, and all of the equivalents or equivalents of the claims, as well as the following claims, I will say.

100: substrate
200: lower conductive layer
200a: lower electrode
200b: lower connection electrode
300: semiconductor layer (silicon layer)
300a: photoelectric element (photoelectric element)
300b: dummy photoelectric device
310: polycrystalline photoelectric device
320: amorphous photoelectric device
400: sidewall insulation layer
500: upper electrode
510: upper conductive layer

Claims

A substrate including a plurality of unit cell regions and a plurality of wiring regions positioned between the unit cell regions;
A lower electrode formed on the unit cell area on the substrate;
A lower connection electrode formed on the wiring area on the substrate and connected to the same layer as one side of the lower electrode;
An optoelectronic device portion formed on the lower electrode and having a plurality of semiconductor layers stacked thereon;
A dummy photoelectric device formed on the lower connection electrode in the same layer as the optoelectronic device portion and patterned with an n-type semiconductor layer, the semiconductor layer having the least resistance among the stacked semiconductor layers; And
An upper electrode formed on the optoelectronic device portion, the upper electrode being formed on the patterned dummy photoelectric device and electrically connected to the optoelectronic device portion of a neighboring unit cell region
Solar cell comprising a.

The method of claim 1,
And the lower electrode and the optoelectronic device portion are collectively patterned.

delete

The method of claim 1,
And a sidewall insulating layer disposed on the wiring region on the substrate and positioned between the side surface of the lower electrode and the optoelectronic device portion and the upper electrode.

(a) providing a substrate including a plurality of unit cell regions and a plurality of wiring regions located between the unit cell regions;
(b) sequentially forming a lower conductive layer and a plurality of semiconductor layers on the entire surface of the substrate;
(c) collectively first patterning the lower conductive layer and the semiconductor layer on the wiring region on the substrate;
(d) forming an upper conductive layer on the entire surface of the substrate; And
(e) second patterning an n-type semiconductor layer, the semiconductor layer having the least resistance among the upper conductive layer and the patterned semiconductor layer on the wiring region on the substrate;
Method for manufacturing a solar cell comprising a.

The method of claim 6,
The first patterning method of manufacturing a solar cell, characterized in that performed using laser scribing.

The method of claim 6,
The second patterning method of manufacturing a solar cell, characterized in that performed using laser scribing or mechanical scribing.

delete

The method of claim 6,
The step (c) further comprises the step of forming a sidewall insulating layer in contact with the side of the patterned lower conductive layer and the patterned semiconductor layer on the wiring area on the substrate.