KR101006665B1 - Subscriber identity module simulator using programmable logic device - Google Patents

Abstract

The present invention relates to a design technique of a SIM simulator that virtually supports the function of a SIM card inserted into a GSM terminal. The present invention includes a clock divider 401 for dividing a clock signal input through the signal terminal unit 303 at a predetermined frequency; A clock counter 402 for counting the divided clock signal and transferring the count value to the ETU processor 405; An input sensitivity processor that checks various signals CLK, RST, Vpp, and IO input through the signal terminal unit 303 and passes the input / output contents to the data sampling processor 404 when a specific condition is satisfied. 403; A data sampling processor 404 for combining the output content with the start flag, the parity bit, and the guard bit and outputting the output flag to the input sensitivity processor 403 in synchronization with the ETU input from the ETU processor 405; An ETU processor 405 for outputting an element time unit (ETU) which is a basic timing of the SIM; All commands defined in the SIM specification are defined by the SIM command processing unit 406, which defines and responds appropriately to all commands necessary for SIM simulation.

Description

SIM SIM USING PELDI {SUBSCRIBER IDENTITY MODULE SIMULATOR USING PROGRAMMABLE LOGIC DEVICE}

1 is an overall schematic diagram of a shim simulator according to the prior art;

2 is a detailed block diagram of a shim simulator according to the prior art;

3 is a schematic block diagram of a shim simulator according to the present invention;

4 is a detailed block diagram of a shim simulator according to the present invention;

*** Description of the symbols for the main parts of the drawings ***

301: JTAG port 302: CPLD

303: signal terminal 304: probe

401: Clock divider 403: Clock counter

403: input sensitivity processing unit 404: data sampling processing unit

405: ETU processing unit 406: SIM command processing unit

407: output control unit PT1-PT4: port

The present invention relates to a design technology of a SIM simulator that virtually supports the function of a SIM (SIM) card inserted into a GSM terminal. In particular, the present invention provides timely test data in place of an expensive SIM simulator. It is about a sim simulator using a programmable logic device (PLD).

In the conventional SIM card simulation technology, a SIM card is simulated using a simulator of a company that specializes in producing a SIM simulator. In this technology, all the scenarios specified in the test case are entered, so when the user enters only the number of the scenario, the user processes the batches and outputs the results. A detailed description with reference to FIG. 2 is as follows.

The SIM card simulation system according to the prior art is largely composed of a PC 101, a SIM simulator 102 and a GSM terminal (hereinafter referred to as "terminal") 103 as shown in FIG. The PC 101 is equipped with a PC slot card for connecting with the SIM simulator 102, and inputs information transmitted from the SIM simulator 102 through a connection cable and the PC slot card. In addition, a SIM card probe is connected to the SIM simulator 102 to receive information from the terminal 103, and the probe is mounted on the SIM adapter portion of the terminal 103, thereby providing a virtual SIM. It will act as a card.

When the SIM card simulation system is constructed as described above, the PC 101 reads and executes a predetermined simulation scenario from the SIM simulator 102 in units of files, and the generated files are passed through the SIM simulator 102. The data is converted into the same data format as that of the actual SIM card and transmitted to the terminal 103. At this time, the terminal 103 takes a response or action when data of a predetermined format is input, and all such information is extracted from the SIM simulator 102 and compared with a test case, and the result is the PC. Is sent to 101.

On the other hand, Figure 2 shows an operation model for a conventional SIM simulator, this technique can be largely divided into three parts, where the PC interface is excluded. The interface unit 201 interfaces with the terminal 103, which is further subdivided into a measurement and load module 204, a measurement data unit 205, and a measurement parameter unit 206. The operation can be classified into a transmission to the terminal 103 and a reception from the terminal 103.

First, the transmission operation to the terminal 103 will be described. The scenario file is first requested from the PC 101, and the contents are transmitted to the SIM simulator 102 via the interface card. The transmitted content is converted into a simulator format through a transmission and switching layer 212, and headers and data are extracted from the simulation application unit 210 and output to the SIM 209. At this time, in the SIM 209, a command and a response transmitted to the terminal 103 are determined by the GSM 11.11 spec, and the contents thereof in the seventh manipulation unit 208. Is transmitted to the first layer control and moneyfusion 207. Afterwards, the electrical characteristics complying with the SIM specification are finally transmitted through the measurement and load module 204 and transmitted to the terminal 103.

On the other hand, the reception operation from the terminal 103 will be described. When the terminal 103 issues a command toward the SIM simulator 102, it is transmitted as follows. The command received from the terminal 103 is transmitted to the SIM simulator 102 through the dummy SIM card 203 replacing the SIM card, and the measurement data unit 205 extracts what data is currently received. Done. In addition, the protocol application unit 210 confirms the protocol, and the result of the confirmation is transmitted to the PC 101 through the transmission and switching layer 212. As the processing proceeds, communication with the first layer and the upper layer is performed, and is transmitted to the PC 101 through a protocol satisfying the GSM 11.11.

However, when using such a conventional SIM simulator, there was a problem in that the initial installation cost (price per unit of billions) is spent a lot.

In addition, there is a problem that it is difficult to quickly support the test case of the SIM that is constantly updated, and the cost of upgrading the software module is high.

In addition, other tests, which are not defined as test cases or scenarios, for example, have a problem in that developers cannot test the performance of terminals other than the test cases.

Accordingly, an object of the present invention is to provide a SIM simulator that provides test data in a timely manner in place of an expensive SIM simulator.

Figure 3 is a block diagram showing an embodiment of a SIM simulator according to the present invention, as shown here, JTAG port 301 for downloading the formware (Firmware) required for the virtual SIM simulation; CPLD 302 programmed in a VHDL language to perform a virtual SIM simulation role; A signal terminal unit 303 for transmitting and receiving with the terminal; Like the SIM, a probe 304 is provided to provide various signals CLK, RST, Vpp, and IO to the signal terminal unit 303.

FIG. 4 is a detailed block diagram of the CPLD in FIG. 3. As shown in FIG. 3, the clock signal CLK inputted through the signal terminal unit 303 is divided at a predetermined frequency so that the clock counter 402 and the input sensitivity processing unit ( A clock divider 401 output to 403; A clock counter 402 for counting the divided clock signal and transferring the count value to the ETU processor 405; An input sensitivity processor that checks various signals CLK, RST, Vpp, and IO input through the signal terminal unit 303 and passes the input / output contents to the data sampling processor 404 when a specific condition is satisfied. (403, or first processing unit); A data sampling processor 404 (or second processor) for combining the output contents with the start flag, the parity bit, and the guard bit, and outputting them to the input sensitivity processor 403 in synchronization with the ETU input from the ETU processor 405; ; An ETU processor 405 (or a timing signal generator) for outputting an elementary time unit (ETU) which is a basic timing of the SIM; A SIM command processing unit 406 or a command control unit, in which all commands defined in the SIM specification are defined to respond appropriately to all commands necessary for SIM simulation; The control unit 407 controls the signal input / output operation between the signal terminal unit 303 and the input sensitivity processing unit 403 under the control of the SIM command processing unit 406. The operation of the present invention configured as described above will be described in detail. Is as follows.

First, in FIG. 3, the JTAG port 301 is a port for downloading the required formware, and the CPLD 302 is a main part of the present invention which performs a virtual SIM role. In addition, the signal terminal unit 303 is for transmitting and receiving with the terminal, the probe 304 is a probe (probe) that can provide the signals of the signal terminal unit 303 like a SIM.

The operation of the CPLD 302 will be described in more detail with reference to FIG. 4 as follows.

The control of the CPLD 302 is mostly programmed in a schematic or a specific language. In the present invention, the CPLD 302 is programmed in a VHDL language most commonly used. For this reason, the characteristics of the VHDL language divide and explain each block by processing area, and the actual VHDL code is written in this structure.

Here, the functions are explained by subdividing them into seven processing areas. The signals input through the signal terminal unit 303 are required for communication, such as a clock signal CLK, a reset signal RST, a voltage Vpp required for driving a program, and an input / output signal IO. The processing unit that receives such a control signal is an input sensitivity process, that is, a signal terminal unit 303.

When the clock signal CLK is input through the signal terminal unit 303, the clock divider 401 divides the clock signal at a predetermined frequency (13/4 MHz) and outputs it to the clock counter 402 on the other hand. Outputs to the input sensitivity processing unit 403.

In this case, the input sensitivity processing unit 403 compares the clock signal CLK with the reset signal RST, the voltage Vpp, and the input / output signal IO and initializes them in the following cases.

When this condition is satisfied, the input sensitivity processing unit 403 passes the input / output (IO) contents to the data sampling processing unit 404.

At this time, the clock counter 402 counts the clock signal divided by the clock divider 401. Initially, the clock counter 402 counts a predetermined value (for example, 372), but if an improved speed is applied, Count 64. The counted value is an elementary time unit (ETU), which is a basic timing of the SIM, and the value is transmitted to the ETU processor 405.

The SIM command processing unit 406 is a main part of the present invention, in which all commands defined in the SIM specification are defined, which are further classified into a command processing unit and a length process unit.

The SIM command processing unit 406 may implement an appropriate response to all commands. However, since the gist of the present invention is to implement a test case rather than a virtual SIM, a test case necessary at that time is programmed.

Meanwhile, a process for a specific test case will be described with reference to FIG. 4 as follows. An example of a test case to be described later is GSM 27.11.2.6, which is a test case for supporting enhanced speed. The test case is taken as an example because the test case has not yet been updated in the commercial SIM simulator.

" 조건이 만족되면, 이는 콜드 리세트 조건이다. 이때, 상기 SIM 커맨드 처리부(406)에서는 ATR(ATR: Answer To Reset) 신호를 출력하는 모드로 진입하게 되는데, 이 모드는 전송모드로서 출력 제어부(407)로 하여금 출력 선택을 하도록 한다. 이때, 입출력신호를 받아들이는 양방향의 입출력포트(PT4)는 상기 출력 제어부(407)의 제어를 받아 출력포트로 전환된다. When the power switch of the terminal is turned on, the SIM simulator of the present invention starts to be driven. At this time, the input sensitivity processing unit 403 is driven to continuously check the input state. Above check result "

"Condition is satisfied, this is a cold reset condition. At this time, the SIM command processing unit 406 enters a mode for outputting an ATR (ATR) answer, which is a transmission mode. In this case, the controller 407 selects the output, and the bidirectional input / output port PT4 receiving the input / output signal is switched to the output port under the control of the output controller 407.

Thereafter, the SIM command processing unit 406 outputs an ATR signal. At this time, in response to a given specification, the TS is first outputted, then T0 is outputted, and then TA1 is outputted. The output information is combined with a start flag, a parity bit, and a guard bit in the data sampling processor 404 and then synchronized with an ETU input from the ETU processor 405. It is output to the input / output port PT4. Here, TS, T0 and TA1 are preset protocols.

Accordingly, when the terminal receives the ATR signal, it starts to respond to it. Any terminal that correctly recognizes TA1 and supports increased speed will output a PTS procedure. If the correct PTS is sent, this test case is considered a pass. In this case, in order to find out the response from the terminal, an oscilloscope may be connected to the signal terminal unit 303 to compare data.

As described in detail above, the present invention has the effect of significantly reducing the cost for SIM simulation by allowing test data to be provided in a timely manner in PDL in place of the expensive SIM simulator.

In addition, any specification has the effect of being applied and tested immediately, and has the effect of performing a complementary role of a commercial SIM simulator.

Claims (6)

A clock divider for dividing a clock signal input through the signal terminal unit at a predetermined frequency; A clock counter for counting the divided clock signal and generating a count value; A timing signal generator for receiving a count value of the clock counter and outputting a basic timing signal of a subscriber identity module (SIM); The data signal input through the signal terminal unit is transferred to the second processing unit based on the control signals CLK, RST, and Vpp input through the signal terminal unit, and the response signal flowing through the second processing unit is transmitted to the signal terminal unit. A first processing unit for outputting through; The data signal received from the first processor is transferred to a command controller, and the response signal of the command controller is combined with a start flag, parity bit, and guard bit, and then output to the first processor in synchronization with the basic timing signal. A second processor; And And a command controller configured to output a response signal corresponding to the SIM command according to the received data signal to the second processor when the data signal is received from the second processor. The method of claim 1, The first processor is a control signal input through the signal terminal unit "Vpp (High), RST (Low-> High), CLK (swing)" And the input data signal is transmitted to the second processor if the condition is satisfied. The method of claim 1, wherein the second processing unit Simulating the PIM, when simulating a test case for supporting the increased speed, combining the response signal of the command controller with a start flag, a parity bit, and a guard bit, and then synchronizing with the basic timing signal. Simulator. The method of claim 1, wherein the command control unit A SIM simulator using PDL, characterized by outputting an ATR signal when a cold reset condition is satisfied when simulating a test case for supporting an increased speed. A first processing unit transferring a data signal input through a signal terminal unit to a second processing unit, or outputting a response signal flowing through the second processing unit through the signal terminal unit; A clock counter for counting the divided clock signal when the clock signal inputted through the signal terminal unit is divided at a predetermined frequency; A timing signal generator for receiving a count value of the clock counter and outputting a basic timing signal of a subscriber identity module (SIM); Transmitting a data signal received from the first processor to a command controller, combining the response signal of the command controller with a start flag, parity bits, and guard bits, and outputting the data signal to the first processor in synchronization with the basic timing signal; 2 processing section; And And a command controller configured to output a response signal corresponding to the SIM command according to the received data signal to the second processor when the data signal is received from the second processor. The method of claim 5, wherein the command control unit Simulating a test case for supporting increased speed, the shim simulator, characterized in that if the cold reset condition is satisfied, and outputs a response signal accordingly.

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