JP2003015966A - Memory card test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a memory card test device capable of simultaneously inspecting a plurality of memory cards, easy in operation and capable of inspecting a number of the memory cards in a short time. SOLUTION: The memory card test device is provided with a plurality of connectors 21-0 to 21-N mounting the memory cards, a gate circuit comprising FPGA1 realizing a function generating a prescribed test signal to be commonly transmitted to the plurality of the memory cards and judging to individually take in response signals from each of the memory cards, and LEDs 22-0 to 22-N displaying quality of a judging result on each of the memory cards.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card test apparatus, and more particularly to a memory card test apparatus for testing a plurality of memory cards at the same time.

[0002]

2. Description of the Related Art Using a conventional memory card test device,
When inspecting the memory card, a dedicated controller and host CPU were required. The host CPU issues a read command to the dedicated controller, the dedicated controller performs the read process, and passes the read data to the host CPU. Even if only a simple inspection is performed, the dedicated program can be executed by the host CPU. It had to be run on and control the memory card through a dedicated controller for inspection. When inspecting a plurality of memory cards, one dedicated controller can control only one memory card in the conventional memory card test apparatus, and therefore, a plurality of the same test apparatuses must be used. Furthermore, multiple dedicated controllers can be connected to one host CP.
It was also difficult to control with U.

When reading one designated block of the memory card, the dedicated controller performs the reading process in the procedure of the following steps. Step 1: Designation of read block Step 2: Setting of read command Step 3: Confirmation of read command Step 4: Page read, data transfer ... Step N: (N-3) page read, data transfer ... Step 35: 32 pages are read, data is transferred, and in the case of a 4 Mbyte memory card, there are 512 blocks. Therefore, when reading all the memories, the above process needs to be repeated 512 times. As described above, in the conventional memory card test apparatus, one dedicated controller can control only one memory card, and there are many steps in the processing procedure. Therefore, when a large number of memory cards are inspected, it takes time and time. There was a problem of this.

[0004]

As described above, in the conventional memory card testing device, one dedicated controller is used as one controller.
Since only one memory card can be controlled and there are many steps in the processing procedure, there is a problem that it takes time and labor to inspect a large number of memory cards. The present invention solves this problem by a relatively simple method, can inspect a plurality of memory cards at the same time, is easy to operate, and can inspect a large number of memory cards in a short time. The challenge is to realize the device.

[0005]

In order to achieve the above object, the present invention provides a memory card testing apparatus for testing the function of a memory card, comprising a plurality of memory card mounting means for mounting the memory cards respectively, and a predetermined memory card mounting means. Test signal transmitting means for generating a test signal and transmitting the same to the plurality of memory cards mounted on the memory card mounting means, and the predetermined test from each of the memory cards mounted on the memory card mounting means. For each of the memory cards, a plurality of response signal receiving means for individually receiving response signals corresponding to the signals, and whether or not the response signal received by the response signal receiving means for the predetermined test signal is appropriate. A plurality of discriminating means for individually discriminating, and a plurality of displaying for each of the memory cards the quality of the discrimination result by the discriminating means. Characterized by comprising a determination result displaying means. As a result, the same test can be performed on a plurality of memory cards, the operation is easy, and it is possible to realize a memory card testing apparatus capable of testing a large number of memory cards in a short time.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION A memory card test apparatus according to the present invention will be described in detail below with reference to the accompanying drawings.

First, the hardware configuration of the memory card test apparatus of the present invention will be described. FIG. 1 shows a block diagram of a circuit of this device. In FIG. 1, reference numeral 1 is an FPGA (Fi
eld Programmable Gate Arr
ay), reference numerals 2-0 to 2-N are memory card connection blocks, reference numerals 21-0 to 21-N are connectors, and reference numeral 2
2-0 to 22-N are LEDs. Reference numeral 3 is a maximum block number signal [max block] set by a mode switch (not shown), and reference numeral 4 is a reset signal [rs].
tn], reference numeral 5 is a clock signal [clk], and VC
C is a power source. The FPGA 1 is a gate circuit device in which the connection of internal circuits can be programmed as desired. The circuit of this device is basically composed of a gate circuit FPGA 1, a connector 21, an LED 22, and a mode switch.

FIG. 2 shows an example of the terminal function of the connector 21 for interfacing between the circuit of this device and the memory card. Here, BS is a bus state signal terminal, which is an output signal from the test apparatus and an input signal when viewed from the memory card. SDIO is a serial data input / output signal terminal and is an input / output signal from the test apparatus. SCLK is a serial clock signal terminal, which is an output signal from the test apparatus. Input to the SCLK terminal [sclk]
Is a clock divider of FPGA1 and [clk] 5 is set to 1
It is a frequency divided into two frequencies. INS is a card insertion detection signal terminal, which is an input signal to the test apparatus.
Further, VCC is a power supply terminal and VSS (GND) is a ground terminal.

The operation of the memory card test apparatus of the present invention will be described below by taking the case of inspecting the reading of the flash memory of the memory card as a representative. Writing to the flash memory and format check can be performed by the same method. The FPGA 1 controls the [bs] signal input to the BS terminal and the [sdio] data signal input to the SDIO terminal by counting the clock signal [clk] 5.

VCC is switched by a signal at the INS terminal so that it is supplied only when a memory card is inserted.
[Max block] signal 3 given by MODE SW is 8-bit data indicating the size of the inspection memory. LED for displaying each memory card inspection status is FP
It is controlled by the [ok] signal from the error check circuit of GA1. By performing packet communication to the memory card, the memory card Flash memory can be read.

The memory size to be checked is Attribu.
te ROM Read UNIT packet is transmitted, and in response, the packet is identified from the packet returned from the memory card. After that, Block Set UNI
By repeating T and Page Data Read UNIT, reading from the flash memory can be repeated. The gate circuit that generates this packet is the FPGA 1 in FIG.

Next, the gate circuit configuration of the FPGA 1 will be described. FIG. 3 shows a gate circuit for controlling packet communication,
The detailed block diagram of the circuit structure of FPGA1 is shown. In FIG. 3, reference numeral 11 is an input buffer gate (IBUF).
G), reference numeral 12 is a clock frequency dividing circuit (CLKDLL),
Reference numerals 13-1 and 13-2 denote buffer gates (BUF).
G), reference numeral 14 is a step counter module (step counter circuit), and reference numeral 15 is sdio ou
t module (serial data signal output circuit), reference numeral 1
Reference numeral 6 is a step gen module (step generation circuit), reference numeral 17 is a crc16 module (CRC16 forming circuit), and reference numerals 18-1 to 18-N are error channels.
eck module (error check circuit), symbol 19-
1 to 19-N are input / output bidirectional buffers. Further, reference numeral 3 is a maximum block number signal [max block], reference numeral 4 is a reset signal [rstn], reference numeral 5 is a clock signal [clk], and reference numeral 6 is a divided clock signal [scl].
k] and symbols 7-1 to 7-N are serial data signals ([s
[dio-0] to [sdio-N]), symbols 8-1 to 8-
N is a bus state signal ([bs-0] to [bs-
N]), reference numerals 9-1 to 9-N are determination signals ([ok-0]).
~ [Ok-N]).

The clock frequency dividing circuit (CLKDLL) 12 reduces the frequency of the clock signal [clk] 5 input from the clk terminal to ½ frequency and is used for the synchronous clock inside the FPGA 1 and the external output of each memory card [sclk]. ]
6 is formed. step counter module 1
4 counts [sclk] 6, generates a 14-bit counter value [step], and supplies it to another module. For each module that has been supplied, this [step]
The output signal is switched according to the value of the counter. [Ste
The p] counter is reset to 0 when counting only the sequence of reading data for one block of the memory card, and the 16-bit [block] counter is counted up. The [block] counter is [max block
When the value specified by the ck] signal 3 is reached, the value is reset to 0 and the 8-bit [loop] counter is counted up. The [loop] counter is not cleared and returns to 0 after the full bit count.

In the sdio out module 15,
The [sdio] output signal of the fixed packet is generated at the timing of the [step] counter signal. [Sd
io] The output signal outputs a transfer protocol command conforming to the standard of the memory card according to a prescribed pattern. The block read command must specify the block to be read, and the current value of the [block] counter is used for this block specification. ste
In the p gen module 16, according to the value of the [step] counter signal, the [bs] signal 8, the [dir] signal,
The [crc calc] signal and the [crc out] signal are generated. The [bs] signal 8 is a bus state signal supplied to the memory card. The [dir] signal is [sdi
o] signal input / output is used for direction switching of the bidirectional buffer 19. [Crc calc] signal, [crc o
ut] signal is supplied to the crc16 module 17 as C
This is a timing pulse for RC calculation.

The [sdio] output signal 7 supplied to the memory card includes a CRC 16 (Cyclic) at the time of data transfer.
Redundancy Check 16, 16-bit cyclic redundancy check signal) must be added immediately after the data part. In the crc16 module 17, [sdio]
The CRC16 calculation of the output signal 7 is performed. [Crc cal
c] The C16 calculated by the [crc out] pulse signal by designating the CRC16 calculation area (data part) with the pulse signal
The RC16 signal is added to the [sdio] output signal 7 and output.

Error check module 18
Analyzes the [sdio] signal input from the memory card. The operation of the memory card is judged from the values of the [step] counter, the [block] counter, and the [loop] counter, and if it is different from the specified operation, [ok]
The signal is NG. Further, the value of the [max block] signal 3 is compared with the memory size information from the memory card to check the consistency of the memory size. Even when the memory size is different from the set value, the [ok] signal is set to NG.

[Sdio] output signal 7, [bs] signal 8
Since the output signals such as "" output the same contents to all the memory cards at the same timing, the outputs from one crc16 module 17 and the step gen module 16 are distributed to all the memory cards. On the other hand, [sdi
The [o] input signal and the [ok] signal need to correspond individually to each memory card.
The modules 18-0 to 18-N are arranged by the number of test memory cards.

Error check module 18-
The error detection conditions of 0 to 18-N are as follows: Check for interrupt occurrence, check RDY signal, Attribute
It is a comparison of the memory size detected by ROM Read UNIT and the memory size setting value by [max block] signal 3 from MODE SW. If a memory card with the wrong memory size is inserted or if the memory card does not operate normally, it will be detected as an error. In the memory card test apparatus of the present invention described above,
By performing the packet communication for reading the flash memory, it is possible to simultaneously inspect a plurality of memory cards.

In the present invention, the communication with the memory card is limited to the inspection contents and fixed, so that the memory card can be controlled and inspected only by the gate circuit. Also,
By distributing the communication packets to the memory cards, it is possible to control multiple memory cards at the same time. The gate circuit detects the difference in the data received from the memory card for inspection. Due to these characteristics, the circuit configuration is simplified only by the gate circuit, the inspection time can be shortened because a plurality of inspections are performed simultaneously, and the operation can be facilitated. In addition, by changing the gate circuit, the Flash
Not only reading of memory, but also writing and format inspection are possible. Furthermore, this device configuration can be applied not only to memory cards but also to similar memory devices. Furthermore, not only memory devices but also HO
It is also possible to control a device controlled by ST or an interface with the controller by using a communication protocol.

[0020]

As described above, according to the invention of claim 1 of the present invention, a plurality of memory card mounting means for mounting a memory card respectively, and a predetermined test signal are generated and commonly transmitted to the plurality of memory cards. A test signal transmitting means, a plurality of response signal receiving means for individually receiving response signals from each of the memory cards, and a plurality of determining means for individually determining whether or not the response signals are appropriate for each of the memory cards. Display means is provided for displaying the quality of the determination result for each of the memory cards. As a result, the same test can be performed on a plurality of memory cards at the same time, the operation is easy, and a memory card testing apparatus capable of testing a large number of memory cards in a short time can be realized with a relatively simple configuration. it can.

The invention of claim 2 of the present invention is characterized in that the test signal transmitting means, the response signal receiving means and the discriminating means are constituted by an FPGA circuit. As a result, the test apparatus can be realized with a simple configuration, and by changing the gate circuit, it is possible to realize the memory card test apparatus that can easily cope with the change of the test item.

The invention of claim 3 of the present invention is characterized in that the test signal transmitting means transmits the test signal to the memory card by a communication packet. As a result, the test signal can be transmitted to the plurality of memory cards without difficulty.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a memory card test apparatus of the present invention.

FIG. 2 is a diagram showing an example of terminal functions of a connector for interfacing a memory card test device of the present invention with a memory card.

FIG. 3 is a detailed block diagram of the configuration of a gate circuit of the memory card test apparatus of the present invention.

[Explanation of symbols]

1 ... FPGA, 2-0 to 2-N ... Memory card connection block, 3 ... Maximum block number signal [max block
k], 4 ... Reset signal [rstn], 5 ... Clock signal [clk], 6 ... Divided clock signal [sclk], 7
-1 to 7-N ... Serial data signal [sdio-0]
[Sdio-N], 8-1 to 8-N ... Bus state signals [bs-0] to [bs-N], 9-1 to 9-N ... Judgment signals [ok-0] to [ok-N] , 11 ... Input buffer gate (IBUFG), 12 ... Clock divider circuit (CLK
DLL), 13-1, 13-2 ... Buffer gate (BU
FG), 14 ... step counter module (step counter circuit), 15 ... sdio out module (serial data signal output circuit), 16 ... st
ep gen module (step generation circuit), 17 ...
crc16 module (CRC16 forming circuit), 18-
1-18-N ... error check module (error check circuit), 19-1-19-N ... I / O bidirectional buffer, 21-0-21-N ... Connector, 22-0
22-N ... LED.

Claims (3)

[Claims] 1. A memory card testing apparatus for testing the function of a memory card, wherein a plurality of memory card mounting means for mounting the memory cards respectively and a plurality of memory card mounting means for generating a predetermined test signal are mounted on the memory card mounting means. And a plurality of response signal reception means for individually transmitting response signals corresponding to the predetermined test signals from each of the memory cards mounted in the memory card mounting means, respectively. A plurality of discriminating means for discriminating whether or not the response signal received by the response signal receiving means with respect to the predetermined test signal is appropriate for each of the memory cards, and the discriminating means. A plurality of discrimination result display means for displaying the quality of the result of the determination for each of the memory cards. Memory card test equipment. 2. The test signal transmitting means, the response signal receiving means, and the discriminating means are an FPGA (Field Pr).
The memory card test apparatus according to claim 1, wherein the memory card test apparatus is configured by an programmable gate array) circuit. 3. The memory card test apparatus according to claim 1, wherein the test signal transmission means transmits the predetermined test signal to the memory card by a communication packet.