KR100984354B1 - Thin film transistor substrate, liquid crystal display including the same ,and manufacturing method thereof - Google Patents

Abstract

A gate wiring including a gate line and a gate electrode connected thereto, a gate insulating film covering the gate wiring, a semiconductor pattern formed on the gate insulating film, and formed separately from each other on the semiconductor pattern and formed of the same layer. A protective film having a source wiring and a drain electrode, a data wiring including a data line connected to the source electrode and crossing the gate line to define a pixel region, and a first contact hole for exposing the drain electrode; 1 includes a contact auxiliary member for connecting the end of the pixel electrode, the gate wiring, and the data wiring connected to the drain electrode through the contact hole with an external circuit, wherein the contact auxiliary member is a thin film composed of a double layer of an IZO layer and an ITO layer. Transistor substrate.

Thin Film Transistor Board, ITO, IZO

Description

A thin film transistor substrate, a liquid crystal display including the same, and a manufacturing method therefor {THIN FILM TRANSISTOR SUBSTRATE, LIQUID CRYSTAL DISPLAY INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF}

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view taken along line II-II 'of FIG. 1,

3A, 4A, 5A, and 6A are layout views of a thin film transistor substrate, illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, according to a process sequence thereof;

3B is a cross sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

4B is a cross sectional view taken along the line IVb-IVb ′ in FIG. 4A showing the next step of FIG. 3B;

FIG. 5B is a cross sectional view taken along the line Vb-Vb ′ in FIG. 5A and showing the next step in FIG. 4B;

FIG. 6B is a cross sectional view taken along the line VIb-VIb ′ in FIG. 6A and showing the next step in FIG. 5B;

FIG. 7 is a cross sectional view taken along the line VIb-VIb ′ of FIG. 6A, showing the next step of FIG. 6;

FIG. 8 is a cross-sectional view taken along line VIb-VIb ′ of FIG. 6A and illustrating a next step of FIG. 7.

FIG. 9 is a cross-sectional view illustrating the next step of FIG. 8 as a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A, and is a cross-sectional view showing a liquid crystal display device.

FIG. 10 is a diagram illustrating a shadow mask for manufacturing a liquid crystal display according to an exemplary embodiment of the present invention.

The present invention relates to a wiring structure, a thin film transistor substrate using the same, and a manufacturing method thereof.

The thin film transistor substrate is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic EL (electro luminescence) display device, or the like. The thin film transistor substrate includes a scan signal line or a gate line for transmitting a scan signal and an image signal line or data line for transmitting an image signal, a thin film transistor connected to the gate line and a data line, and a pixel connected to the thin film transistor. And an electrode, a gate insulating film covering and insulating the gate wiring, and a thin film transistor and a protective film covering and insulating the data wiring. The thin film transistor includes a semiconductor layer forming a gate electrode and a channel, which are part of a gate wiring, a source electrode and a drain electrode, which are part of a data wiring, a gate insulating film, a protective film, and the like. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

A representative device using such a thin film transistor substrate is a liquid crystal display device. In a liquid crystal display device that is a light receiving display device, particularly a thin film transistor substrate of a transmissive liquid crystal display device, a transparent conductive material should be used as a pixel electrode material. In general, transparent electrode materials currently used include indium tin oxide (ITO) and indium zinc oxide (IZO), each of which has disadvantages. In the case of ITO, a strong acid must be etched in the photolithography process, and the strong acid penetrates through the pinhole of the insulating layer, thereby damaging the data or the gate wiring. On the other hand, in the case of IZO, it is possible to etch a photo even without using a strong acid, so there is no problem of damaging the lower wiring, but a gross that inspects the panel for abnormality by using a probe before mounting the gate and data driver IC. In the Gross Test (GT) step, the C and Si components of the gate and the data pads are adsorbed on the surface of the probe, thereby making it difficult to inspect.

The technical problem to be solved by the present invention is to provide a thin film transistor substrate that does not damage the lower wiring in the formation process and is easy to gross test.

The thin film transistor substrate according to the present invention is formed on an insulating substrate, and includes a gate wiring including a gate line and a gate electrode connected thereto, a gate insulating film covering the gate wiring, a semiconductor pattern formed on the gate insulating film, and the semiconductor pattern. A first wire contacting the drain electrode; a data line including a source electrode and a drain electrode formed separately from each other and formed of the same layer, and a data line connected to the source electrode and crossing the gate line to define a pixel region; A protective film having a hole, a pixel electrode connected to the drain electrode through the first contact hole, and a contact auxiliary member connecting an end portion of the gate wire and the data wire to an external circuit through the first contact hole; And contact Division member preferably consisting of a double layer of the IZO layer and the ITO layer.

In addition, the contact assistant member is preferably made of an IZO layer which is a lower layer and an ITO layer which is an upper layer.

In addition, the liquid crystal display according to the present invention is formed on a first insulating substrate, a gate wiring including a gate line and a gate electrode connected thereto, a gate insulating film covering the gate wiring, a semiconductor pattern formed on the gate insulating film, A data line and a drain electrode formed on the semiconductor pattern and separated from each other and including a source electrode and a drain electrode formed of the same layer, and a data line connected to the source electrode and crossing the gate line to define a pixel region. A protective film having an exposed first contact hole, a contact formed on an upper portion of the protective film and connecting end portions of the pixel electrode, the gate wire, and the data wire connected to the drain electrode through the first contact hole to an external circuit; An auxiliary member, the abutment The auxiliary member is a thin film transistor substrate which consists of a double layer of the IZO layer and the ITO layer; A color filter substrate facing the thin film transistor substrate and including a common electrode formed on a second insulating substrate; It is preferable to include a liquid crystal layer injected between the thin film transistor substrate and the color filter substrate.

Further, a method of manufacturing a liquid crystal display according to the present invention may include forming a gate wiring including a gate line and a gate electrode connected thereto on a first insulating substrate, forming a gate insulating film covering the gate wiring, and forming the gate insulating film. Forming a semiconductor pattern on the semiconductor pattern, forming a data line including a source electrode and a drain electrode on the semiconductor pattern, and a data line connected to the source electrode and crossing the gate line to define a pixel region; Forming a passivation layer having a first contact hole for exposing the light source, and contacting an upper portion of the passivation layer to an external circuit connecting the pixel electrode connected to the drain electrode and the ends of the gate wiring and the data wiring through the first contact hole. Forming an auxiliary member, the thin film transistor Forming a color filter substrate having a common electrode opposite the plate, injecting a liquid crystal between the thin film transistor substrate and the color filter substrate and sealing with a sealing material, and forming an ITO layer over the contact assistant member. It is preferable to include.

In addition, the ITO layer is preferably formed using a shadow mask having a cutout in a portion corresponding to the contact assistant member.

Then, a person having ordinary knowledge in the technical field to which the present invention belongs can easily implement the thin film transistor substrate to which the structure of the low resistance wiring according to the embodiment of the present invention is applied and the manufacturing method thereof with reference to the accompanying drawings. It will be explained in detail.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

FIG. 1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II 'of the thin film transistor substrate shown in FIG.

Gate wirings 22, 24, and 26 formed of a double layer of first gate wiring layers 221, 241, and 261 and second gate wiring layers 222, 242, and 262 are formed on the insulating substrate 10. The first gate wiring layers 221, 241, and 261 may include molybdenum alloys such as molybdenum (Mo) and molybdenum tungsten (MoW), chromium (Cr), chromium alloys, titanium (Ti), titanium alloys, thallium (Ta), and thallium. The second gate wiring layers 222, 242, and 262 are made of any one of alloys, and the second gate wiring layers 222, 242, and 262 are made of silver (Ag) or a silver alloy, aluminum or an aluminum alloy, copper, or a copper alloy.

The gate lines 22, 24, and 26 include a gate line 22 extending in the horizontal direction and a gate electrode 26 of the thin film transistor connected to the gate line 22. One end 26 of the gate line 22 is extended in width for connection with an external circuit.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24, and n + having a high concentration of silicide or n-type impurity is formed on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as hydrogenated amorphous silicon are formed, respectively.

On the ohmic contact layers 55 and 56 and the gate insulating layer 30, a data line including double layers of first data wiring layers 621, 651, 661, and 681 and second data wiring layers 622, 652, 662, and 682. (62, 65, 66, 68) are formed. The first data wiring layers 621, 651, 661, and 681 include molybdenum alloys such as molybdenum (Mo) and molybdenum tungsten (MoW), chromium (Cr), chromium alloys, titanium (Ti), titanium alloys, and thallium (Ta). And one of thallium alloys, and the second data wiring layers 622, 652, 662, and 682 are made of silver (Ag) or a silver alloy, aluminum or an aluminum alloy, copper, or a copper alloy.

The data lines 62, 65, 66, and 68 are formed in the vertical direction and intersect with the gate line 22 to define the pixel, the branch of the data line 62, the data line 62, and the resistive contact layer 54. A drain electrode which is separated from the source electrode 65 and the source electrode 65 extending to the top and formed on the ohmic contact layer 56 opposite to the source electrode 65 with respect to the gate electrode 26 ( 66). At this time, one end 68 of the data line 62 is extended in width for connection with an external circuit.

A-Si: C: O film or a deposited on the data lines 62, 65, 66, 68 and on the semiconductor layer 40 which is not covered by silicon nitride (SiNx) or plasma enhanced chemical vapor deposition (PECVD) A protective film 70 made of a -Si: O: F film (low dielectric constant CVD film), an acrylic organic insulating film, and the like is formed. The a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a dielectric constant of 4 or less (the dielectric constant has a value between 2 and 4). The dielectric constant is very low. Therefore, even a thin thickness does not cause a parasitic capacity problem. Excellent adhesion to another film and step coverage. Moreover, since it is an inorganic CVD film, heat resistance is excellent compared with an organic insulating film. In addition, the a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by PECVD method have a 4 to 10 times faster process time than the silicon nitride film. It is also very advantageous in terms of.

In the passivation layer 70, contact holes 76 and 78 are formed to expose the drain electrode 66 and one end 68 of the data line, respectively, and the contact hole exposing one end 24 of the gate line together with the gate insulating layer 30 ( 74 is formed. In this case, the contact holes 74 and 78 exposing the ends 24 and 68 of the gate line and the data line may be formed in various shapes having an angle or a circle, and the area does not exceed 2 mm x 0 μm, and 0.5 mm x It is preferable that it is 5 micrometers or more.                     

On the passivation layer 70, a pixel electrode 82 electrically connected to the drain electrode 66 and positioned in the pixel region is formed through the contact hole 76. Further, on the passivation layer 70, contact auxiliary members 86 and 88 are formed to be connected to one end 24 of the gate line and one end 68 of the data line, respectively, through the contact holes 74 and 78. Here, the contact auxiliary members 86 and 88 are formed of a double layer of indium zinc oxide (IZO) layers 861 and 881 and indium tin oxide (ITO) layers 862 and 882.

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

In addition, the pixel electrode 82 may also be formed to overlap the data line 62 to maximize the aperture ratio. In this way, even when the pixel electrode 82 is formed to overlap the data line 62 in order to maximize the aperture ratio, the parasitic capacitance formed therebetween is kept small so as not to be a problem if the protective film 70 is formed of a low dielectric constant CVD film or the like. Can be.

Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 7B.

First, as shown in FIGS. 3A and 3B, the first gate wiring layers 221, 241, and 261 and the second gate wiring layers 222, 242, and 262 are stacked on the substrate 10, and photo-etched to form a gate line ( 22), the gate wirings 22, 24, and 26 extending in the horizontal direction including the gate electrode 26 are formed.                     

Next, as shown in FIGS. 4A and 4B, a three-layer film of a gate insulating film 30 made of silicon nitride, a semiconductor layer 40 made of amorphous silicon, and a doped amorphous silicon layer 50 is sequentially stacked, and the semiconductor The semiconductor layer 40 and the ohmic contact layer 50 are formed on the gate insulating layer 30 on the gate electrode 24 by photolithography by etching the layer 40 and the doped amorphous silicon layer 50.

Next, as shown in FIGS. 5A to 5B, the first data wiring layers 621, 651, 661, and 681 are stacked, and the second data wiring layers 622, 652, 662, and 682 are stacked, and photo-etched. A data line 62 intersecting the gate line 22 and a source electrode 65 connected to the data line 62 and extending to an upper portion of the gate electrode 26 are separated from the source electrode 64 and the gate electrode ( A data line including a drain electrode 66 facing the source electrode 65 is formed around 26.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 6A and 6B, a silicon nitride film, an a-Si: C: O film or an a-Si: O: F film is grown by chemical vapor deposition (CVD) or an organic insulating film is applied to the protective film. Form 70.

Subsequently, the passivation layer 70 is patterned together with the gate insulating layer 30 by a photolithography process to expose one end 24 of the gate line, the drain electrode 66 and one end 68 of the data line. 78). Here, the contact holes 74, 76 and 78 may be formed in an angled shape or a circular shape, and the area of the contact holes 74 and 78 exposing the ends 24 and 68 of the gate line and the data line is 2 mm. It does not exceed * 0 micrometer, and it is preferable that it is 0.5 mm * 5 micrometers or more.

Next, as illustrated in FIGS. 1 and 7, the IZO is deposited, photo-etched, and the second and third contacts with the pixel electrode 82 connected to the drain electrode 66 through the first contact hole 76. Contact auxiliary members 861 and 881 are formed through the holes 74 and 78 to be connected to one end 24 of the gate line and one end 68 of the data line, respectively. It is preferable to use nitrogen as the gas used in the pre-heating process before laminating IZO. This is to prevent the metal oxide film from being formed on the upper portions of the metal films 24, 66, and 68 exposed through the contact holes 74, 76, and 78.

As described above, when the pixel electrode 82 is formed by using IZO, an etchant such as chromium or aluminum may be used for photolithography, thereby reducing damage to the lower wiring. However, when the contact auxiliary members 861 and 881 (hereinafter referred to as bonding pads), which are connected to one end 24 of the gate line and one end 68 of the data line, are formed of IZO, a gross test (GT) In the step C), the C and Si components of the contact assistants 861 and 881 adsorb to the surface of the probe, thereby making it difficult to inspect.

In order to prevent this, in the present invention, as illustrated in FIGS. 1 and 2, the ITOs 862 and 882 are separately deposited only on the contact auxiliary members 861 and 881 formed of IZO.                     

Hereinafter, the steps of separately depositing ITO only on the contact auxiliary members 861 and 881 formed of IZO will be described in detail.

In FIG. 8, the common electrode 270 and the color filter 230 of the thin film transistor substrate 100 having the pixel electrode 82 and the contact auxiliary members 861 and 881 formed only of IZO are illustrated in FIGS. 1 and 7. And a liquid crystal display to which the color filter substrate 200 on which the black matrix 220 is formed is attached.

As illustrated in FIG. 8, an alignment layer 11 that determines alignment of liquid crystals is formed on the pixel electrode 82 and the passivation layer 180 formed of only IZO. Then, the spacer 320 for maintaining the cell gap of the liquid crystal display device is formed on the alignment layer 11. The sealing material 310 is formed on the edge of the thin film transistor substrate. Outside the sealing material 310, a short 60 for applying a potential is formed by contacting the pixel electrode 82 of the thin film transistor substrate with the common electrode 270 of the color filter substrate. The liquid crystal is injected into the sealing material 310 of the thin film transistor substrate to form the liquid crystal layer 3.

Next, as shown in FIG. 9, a separate ITO layer is formed only on the contact auxiliary members 861 and 881 respectively connected to one end 24 of the gate line and one end 68 of the data line of the manufactured liquid crystal display. (862, 882).

To this end, as shown in FIG. 10, ITO layers 862 and 882 are formed on the bonding pads 861 and 881 by evaporation using a shadow mask 5.

Evaporation is a method of evaporating a material to be deposited in a thin film and depositing it on a substrate.The method is evaporation by thermal heating or e-beam evaporation. Etc.

Unlike sputtering, which deposits on a substrate by giving a plasma ion bombardment to a material, evaporation deposition is possible even at low vacuum and does not require high energy. In addition, there is an advantage in that only the necessary portions can be deposited using the shadow mask.

Such an evaporation method is performed after attaching the thin film transistor substrate 100 and the color filter substrate 200, injecting liquid crystal therebetween to form a liquid crystal panel, and cutting a large substrate in cell units. That is, it is preferable to perform before the visual test (Visual Test) before the module process.

 The process of forming the ITO layer on the bonding pad by the evaporation method is possible to flexibly cope with the enlargement of the substrate since the large sized substrate is cut into cells and then only the bonding pad portion is selectively deposited using a shadow mask. There is this.

In the shadow mask 5, portions corresponding to the bonding pads are cut out to expose only portions where the bonding pads 861 and 862 are formed. That is, the shadow mask 5 includes a gate cutout 5a which is a portion corresponding to the contact auxiliary member 861 connected to the one end 24 of the gate line, and a contact auxiliary member 862 connected to the one end 68 of the data line. And a data cutout 5b which is a part corresponding to).

Therefore, since only the contact auxiliary members 861 and 881 (bonding pads) connected to one end 24 of the gate line and one end 68 of the data line are exposed during evaporation, ITO is deposited only on the bonding pads 861 and 862. .

 Therefore, the bonding pad is a double layer, in which the lower layer is the IZO layers 861 and 881 and the upper layer is the ITO layers 862 and 882. Therefore, the gross test is performed because the probe and the ITO layers 862 and 882, which are the upper layers of the bonding pad, are contacted during the gross test. No foreign matter is caught in the probe.

In the present invention, by forming only the contact assistant member as the IZO and ITO bilayer, it is possible to prevent foreign matter from being caught in the probe during the gross test, and to reduce the manufacturing cost by reducing the use of ITO.

Claims (7)

A gate wiring formed on an insulating substrate and including a gate line and a gate electrode connected thereto; A gate insulating film covering the gate wiring, A semiconductor pattern formed on the gate insulating film, A data line formed on the semiconductor pattern and separated from each other and including a source electrode and a drain electrode formed of the same layer, and a data line connected to the source electrode and crossing the gate line to define a pixel region; A protective film having a first contact hole exposing the drain electrode, A pixel electrode formed on the passivation layer and connected to the drain electrode through the first contact hole; A contact auxiliary member connecting ends of the gate wiring and the data wiring with an external circuit; Including, The pixel electrode is made of IZO, The contact auxiliary member is a thin film transistor substrate consisting of a double layer of the IZO layer and the ITO layer. In claim 1, The contact auxiliary member is a thin film transistor substrate consisting of an IZO layer as a lower layer and an ITO layer as an upper layer. A gate wiring formed on the first insulating substrate, the gate wiring including a gate line and a gate electrode connected thereto, a gate insulating film covering the gate wiring, a semiconductor pattern formed on the gate insulating film, and formed separately from each other on the semiconductor pattern A protective layer having a source electrode and a drain electrode formed of the same layer, a data line connected to the source electrode and intersecting the gate line to define a pixel region, and a first contact hole exposing the drain electrode; A contact auxiliary member formed on the passivation layer and connected to the drain electrode through the first contact hole and connecting the pixel electrode made of IZO, and an end portion of the gate wiring and the data wiring to an external circuit; Contact aid member I A thin film transistor substrate comprising a double layer of a ZO layer and an ITO layer, A color filter substrate facing the thin film transistor substrate, the color filter substrate including a common electrode formed on a second insulating substrate; And a liquid crystal layer injected between the thin film transistor substrate and the color filter substrate. Forming a gate wiring including a gate line and a gate electrode connected to the first insulating substrate, Forming a gate insulating film covering the gate wiring; Forming a semiconductor pattern on the gate insulating layer; Forming a data line on the semiconductor pattern, the data line including a source electrode and a drain electrode and a data line connected to the source electrode and crossing the gate line to define a pixel area; Forming a protective film having a first contact hole exposing the drain electrode; Forming a contact auxiliary member on the passivation layer to connect a pixel electrode connected to the drain electrode through the first contact hole and an end portion of the gate line and the data line to an external circuit; Forming a color filter substrate having a common electrode opposite the thin film transistor substrate; Injecting liquid crystal between the thin film transistor substrate and the color filter substrate and sealing with a sealing material; Forming an ITO layer by an evaporation deposition method using a shadow mask having a cutout in a portion corresponding to the contact assistant member on the contact assistant member; Including, The pixel electrode and the contact auxiliary member are formed of IZO. delete delete In claim 4, The evaporation deposition process is performed after the liquid crystal is injected between the thin film transistor substrate and the color filter substrate and sealed with a sealing material, and then the substrate is cut into cells to form a liquid crystal panel.

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