KR100983525B1 - Complementary Thin Film Transistor Formation Method and Complementary Thin Film Transistor - Google Patents

Abstract

The present invention relates to a method of forming a complementary thin film transistor having an nTFT region and a pTFT region on a substrate of a liquid crystal display, and a complementary thin film transistor thereby. In the method of manufacturing a complementary thin film transistor according to the present invention, forming a buffer layer on a substrate material, forming a continuous crystallization silicon layer on the buffer layer, the silicon oxide layer and nitride on the crystallization silicon layer Sequentially forming a silicon layer, forming a gate pattern on the silicon nitride layer, and removing a silicon nitride layer on the nTFT region except for the silicon nitride layer positioned below the gate pattern on the nTFT region And implanting impurity ions into the nTFT region and the pTFT region, and thermally activating the crystalline silicon layer. This makes it possible to form a complementary thin film transistor on a single continuous crystallized silicon.

Description

Complementary Thin Film Transistor Formation Method and Complementary Thin Film Transistor [Method of making CMOS TFT and CMOS TFT}

1 is a plan view showing a conventional complementary thin film transistor,

2 is a cross-sectional view of II-II of FIG.

3 is a plan view showing a complementary thin film transistor of the present invention;

4 is a cross-sectional view of the IV-IV portion of FIG.

5 is a cross-sectional view of the V-V portion of FIG.

6A through 6D are cross-sectional views sequentially illustrating a method of forming a complementary thin film transistor of the present invention.

* Description of the symbols for the main parts of the drawings *

10: nTFT gate 11: pTFT gate

20: nTFT Source 21: Contact

22: drain 23: pTFT source

30: crystallized silicon layer 40: substrate material

41: buffer layer 42: silicon oxide layer

43 silicon nitride layer 44 interlayer insulating film

The present invention relates to a method of forming a complementary thin film transistor and a complementary thin film transistor thereby, and more particularly, to a method of forming nTFT and pTFT on a continuous single crystallized silicon.

The liquid crystal display device includes a liquid crystal panel in which liquid crystal is injected between the thin film transistor substrate and the color filter substrate. Since the liquid crystal display is a non-light emitting device, a backlight unit for supplying light is located at the rear of the thin film transistor. Light transmitted from the backlight is adjusted according to the arrangement of liquid crystals.

As a method of forming a channel of a thin film transistor (TFT), there are a method using amorphous silicon (a-Si) and a method using crystallized silicon (polysilicon). Among them, the method using crystallized silicon has been used to manufacture high resolution high quality products due to the high mobility of crystallized silicon. In particular, a complementary thin film transistor (hereinafter referred to as cTFT) formed by using crystalline silicon as a channel may be formed in a liquid crystal panel and used as a driving circuit.

Forming the driving circuit in the liquid crystal panel is called a system on glass (SOG). Forming a drive circuit in the form of SOG can reduce costs and enable products with reduced panel size.

SOG requires various circuit formation such as a shift register / buffer circuit formed in the gate driving circuit portion, as well as a shift register, a DAC, and a latch circuit formed on the source driving circuit portion. In order to form such a circuit, the size reduction of the cTFT is required.

1 is a plan view of a conventional cTFT.

The nTFT source 200 and the drain 210 are positioned with the nTFT gate 100 interposed therebetween. On both sides of the pTFT gate 110 are the drain 210 and the pTFT source 230. The crystalline silicon layer 300 in the nTFT region and the crystalline silicon layer 350 in the pTFT region are separated from each other in the lower region of the drain 210. A circled portion in FIG. 1 represents a contact 210. Each source 200, 230 and drain are in contact with the crystalline silicon layers 300, 350 through the contact 210.

Hereinafter, a conventional cTFT will be described in detail with reference to FIG. 2, which shows a cross-sectional view of II-II of FIG. 1.

In the nTFT region, the buffer layer 410, the crystalline silicon layers 300 and 350, and the gate insulating layer 420 are sequentially stacked on the substrate material 400. An isolation region (part A) is formed between the crystalline silicon layer 300 of the nTFT region and the crystalline silicon layer 350 of the pTFT region.

The nTFT gate 100 is positioned on the gate insulating layer 420. Impurity ions are not implanted in the crystallized silicon region 320 under the gate insulating layer 420, and impurity ions are implanted in the other crystallized silicon regions 310 and 330. An interlayer insulating layer 440 is positioned on the nTFT gate 100 and the gate insulating layer 420.

The nTFT source 200 is in contact with the crystallized silicon 310 implanted with impurity ions through the contact 210, and the drain 220 is also in contact with the crystallized silicon layer 330 implanted with impurity ions.

The structure of the pTFT is similar to the nTFT such as the crystallized silicon layer 350, the pTFT gate 110, the pTFT source 230, and the three parts 360, 370, and 380. However, impurity ions implanted into the crystallized silicon layers 360 and 380 in contact with the pTFT source 230 and the drain 220 are different from the nTFT region.

In the conventional cTFT configuration described above, the crystallized silicon of the nTFT region and the pTFT region is separated. This is because when nTFT and pTFT are formed on the same crystallized silicon layer, high energy is generated at the interface between the nTFT region and the pTFT region during laser activation after ion implantation, and impurity ions are mixed. In addition, when ion implantation is performed in each of the nTFT region and the pTFT region using a chrome mask or a photoresist mask, the boundary region between the nTFT region and the pTFT region cannot be formed properly due to the warpage of the chrome mask and the occurrence of photoresist lifting. .

It is therefore an object of the present invention to provide a method for reducing the size of a cTFT by forming nTFT and pTFT in a single continuous crystallized silicon layer in cTFT production and a cTFT formed thereby.

The above object is a method of forming a complementary thin film transistor having an nTFT region and a pTFT region on a substrate of a liquid crystal display device, the method comprising the steps of forming a buffer layer on a substrate material; Forming a layer, sequentially forming a silicon oxide layer and a silicon nitride layer on the crystallized silicon layer, forming a gate pattern on the silicon nitride layer, and a lower portion of the gate pattern on the nTFT region Removing the silicon nitride layer on the nTFT region excluding the silicon nitride layer located at, implanting respective impurity ions into the nTFT region and the pTFT region, and thermally activating the crystalline silicon layer. Can be achieved.

The temperature of the thermal activation step is preferably in the range of 400 to 550 ℃ considering the process time and substrate deformation.

The thickness of the silicon oxide layer and the silicon nitride layer is preferably in the range of 300 to 600 kPa, considering the stability of the etching process and the stability of the ion implantation process.

In the implantation of ions into the nTFT region, the acceleration energy of the ion source is preferably in the range of 10 to 20 KeV, in order to effectively implant ions.

It is preferable to form a contact hole at the boundary between the nTFT region and the pTFT region after the thermal activation step, since the same contact can be used for both nTFT and pTFT.

In addition, the above object is a complementary thin film transistor positioned on a substrate of a liquid crystal display device having an nTFT region and a pTFT region, the buffer layer formed on the substrate material, the continuous crystallization silicon layer located on the buffer layer and An nTFT source in contact with the crystallized silicon layer in the nTFT region, a pTFT source in contact with the crystallized silicon layer in the pTFT region, a drain in contact with a boundary between the nTFT region and the pTFT region, and the crystallized silicon layer on the nTFT region An nTFT impurity ion implantation blocking film, positioned on top of the silicon oxide layer, a pTFT impurity ion implantation blocking film, sequentially placed on top of the crystallization silicon layer on the pTFT, and consisting of a silicon oxide layer and a silicon nitride layer; A gate located above each impurity ion implantation blocking film, and an upper portion of the gate It can also be achieved by including an interlayer insulating film located.

The thickness of the silicon oxide layer and the silicon nitride layer is preferably in the range of 300 to 600 kPa, in consideration of the stability of the etching process and the stability of the ion implantation process.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view showing a cTFT of the present invention.

The nTFT source 20 and the drain 22 are positioned with the nTFT gate 10 interposed therebetween. On both sides of the pTFT gate 11 are the drain 22 and the pTFT source 23. Unlike the related art, the crystallized silicon layer 30 is connected over the nTFT region and the pTFT region. The pTFT source 23 and the drain 22 are positioned with the pTFT gate 11 interposed therebetween. The circled portion in the figure represents the contact 21.

Compared with the prior art, the size of the drain 22 is smaller, and thus the distance between the nTFT gate 10 and the pTFT gate 11 is closer, and thus the size of the cTFT is smaller. In addition, the nTFT region and the pTFT region are used for the contact located in the drain.                     

Hereinafter, the present invention will be described in detail with reference to FIGS. 4 and 5, which illustrate a cross section of IV-IV of FIG. 3.

Referring to FIG. 4, a buffer layer 41, a single connected silicon crystal layer 30, a silicon oxide layer 42 serving as a gate insulating film, and a silicon nitride layer 43 are formed on the substrate material 40. The nTFT gate 10 and the pTFT gate 11 are positioned on the silicon nitride layer 43. Unlike the pTFT region, the silicon nitride layer 43 in the nTFT region exists only under the nTFT gate 10. The silicon oxide layer 42 and the silicon nitride layer 43 serve as a blocking layer when implanting impurity ions into the crystallized silicon layer 30.

The crystallized silicon layer 30 is composed of nTFT crystallized silicon 31 and 33 implanted with boron and the like, pTFT polysilicon 34 and 36 injected with phosphorus and the like and crystallized silicon 32 and 35 without implanting ions. It is.

The nTFT source 20 and the pTFT source 23 are in contact with the respective crystallized silicon layers 31 and 36 through the contact 21. The drain 22 is in contact with the boundary between the nTFT polysilicon 33 and the pTFT polysilicon 34.

An interlayer insulating layer 44 is positioned on the gates 10 and 11.

5, one contact of the drain 22 is in contact with the gate insulating film, i.e., the nTFT crystallized silicon layer 33, in which the impurity ion implantation blocking film is only the silicon oxide layer 42, and the other contact is the gate insulating film, i.e., impurity ion implantation blocking. It can be seen that the film is in contact with the pTFT crystallized silicon layer 34, which is a double layer of the silicon oxide layer 42 and the silicon nitride layer 43. This indicates that the contact is in contact with both the nTFT region and the pTFT region and the contact exists at the boundary between the nTFT region and the pTFT region.

Hereinafter, a detailed description will be given with reference to FIGS. 6A to 6D, which illustrate a process of forming a cTFT of the present invention.

6A shows that the buffer layer 41 and the crystallized silicon layer 30 are formed on the substrate material 40. The buffer layer 41 mainly consists of silicon oxide, and prevents impurities generated in the substrate from penetrating into the crystallized silicon layer 30 during the process. The crystallized silicon layer 30 is formed by depositing an amorphous silicon layer, crystallizing the laser by applying a laser to the amorphous silicon layer, and then patterning the amorphous silicon layer.

FIG. 6B shows that gate insulating layers 42 and 43 and gates 10 and 11 are formed on the crystallized silicon layer 30. After the silicon crystal layer 30 is formed, the silicon oxide layer 42 and the silicon nitride layer 43 are deposited as the gate insulating film. After the gates 10 and 11 are formed on the silicon nitride layer 43, the silicon nitride layer 43 of the nTFT region is removed. As a result, the gate insulating film of the pTFT layer becomes a double film of the silicon oxide layer 42 and the silicon nitride layer 43, and the gate insulating film of the nTFT layer becomes a single film of the silicon oxide layer 42 only. The step difference between the gate insulating films of the pTFT region and the nTFT region is to control the amount of impurity ions to be implanted in an ion implantation process to be described later, and to control the mobility of impurity ions in a thermal activation process.

The thickness of the silicon oxide layer 42 and the silicon nitride layer 43 is preferably in the range of 300 to 600 kPa. In the case of 300 mW or less, the reliability of the gate insulating film is lowered. In the case of 600 mW or more, the activation energy of the impurity ions is excessively large during the impurity ion implantation process.

6C shows that impurity ions are implanted into the nTFT region and the pTFT region using the gates 10 and 11 as masks. In the nTFT region, PH ₃ ions are mainly used to inject phosphorus (P), a group 5 element. In the pTFT region, boron (B), which is mainly a group 3 element, is implanted, and B ₂ H ₆ ions are mainly used. In the implantation of impurity ions in the nTFT region, the pTFT region is covered with a mask. In the implantation of impurity ions in the pTFT region, the nTFT region is covered with a mask.

The crystallized silicon of the nTFT region is formed with regions 31 and 33 implanted with phosphorus and regions 32 without phosphorus implantation. This is because the nTFT gate 10 serves as a mask. The region 32 in which phosphorus is not injected becomes a channel portion. Although not shown in the figure, it is preferable to form a lightly doped drain (LLD) to improve the off current characteristics of the thin film transistor at the boundary between the regions 31 and 33 where phosphorus is implanted and the region 32 where phosphorus is not implanted. . The configuration of crystallized silicon in the nTFT region is similarly applied to the pTFT region.

In the impurity ion implantation in the nTFT region, only the silicon oxide layer 42 serves as a blocking layer for impurity ion implantation. At this time, the acceleration energy of the PH ₃ ion is preferably in the range of 10 to 20 KeV. If the acceleration energy is 10KeV or less, the process time for obtaining the desired impurity ion concentration becomes very long, and if 20KeV or more, the crystallized silicon may be destroyed. Phosphorus ions are preferably implanted in the vicinity of the surface of the crystallized silicon 31, 33 in the nTFT region.

On the contrary, during the impurity ion implantation in the pTFT region, not only the silicon oxide layer 42 but also the silicon nitride layer 43 becomes an impurity ion implantation blocking layer. As a result, the concentration of impurity ions in the crystallized silicon 34 and 36 in the pTFT region is lower than that of the implanted impurity ions in the nTFT region compared to the crystallized silicon 31 and 33.

The crystallized silicon layer crystallized by a laser or the like is partially amorphous by deposition of a gate insulating film and implantation of impurity ions. It is crystallized again through activation, which not only activates the implanted impurity ions to function properly.

The activation method includes a method using a laser and a method using heat. Since the dual laser method does not distinguish between the nTFT region and the pTFT region, a problem arises in that boron having a high mobility moves to the nTFT region. The same problem occurs because thermal activation does not adjust the temperature of the nTFT region and the pTFT region separately. However, in the pTFT region of the present invention, since the gate insulating film is thicker than that of the nTFT region, even though thermal activation is performed at the same temperature, the boron of the pTFT region is less affected by heat than the phosphorus of the nTFT. In addition, the implantation amount of boron in the impurity ion implantation process is relatively small compared to that of phosphorus. Therefore, even after the activation process, the phenomenon of mixing ions between the nTFT region and the pTFT region does not occur.

The temperature in the thermal activation process is preferably between 400 and 550 ° C. If it is below 400 ℃, the activation time becomes very long. If it is above 550 ℃, the glass used as the substrate is deformed.                     

FIG. 6D shows that the source / drains 20, 22, and 23 are formed after the interlayer insulating film 44 is formed and the contact holes are formed. As the interlayer insulating film 44, silicon oxide, silicon nitride, or the like is used.

As described above, in the present invention, after forming a step in the impurity ion implantation blocking layer of the nTFT region and the pTFT region, impurity ions are implanted and thermally activated to form both the nTFT region and the pTFT region in the single crystallized silicon region.

As described above, according to the present invention, the size of the cTFT can be reduced by forming the cTFT on a single continuous crystallized silicon film. This facilitates the manufacture of the SOG type liquid crystal display device using the cTFT.

Claims (7)

In the method of forming a complementary thin film transistor having an nTFT region and a pTFT region on a substrate, Forming a buffer layer on the substrate material; Forming a continuous silicon crystal layer on top of the buffer layer; Sequentially forming a silicon oxide layer and a silicon nitride layer on the crystallized silicon layer; Forming a gate pattern on the silicon nitride layer; Removing the silicon nitride layer on the nTFT region except for the silicon nitride layer under the gate pattern; Implanting impurity ions into the nTFT region and the pTFT region; And thermally activating the crystallized silicon layer. The method of claim 1, Complementary thin film transistor forming method, characterized in that the temperature of the thermal activation step is in the range of 400 to 550 ℃. The method of claim 1, The thickness of the silicon oxide layer and the silicon nitride layer is a complementary thin film transistor forming method, characterized in that each of the range of 300 to 600Å. The method of claim 1, Complementary thin film transistor forming method, characterized in that the acceleration energy of the impurity ion source in the step of implanting impurity ions into the nTFT region is in the range of 10 to 20 KeV. The method of claim 1, And forming a contact hole at a boundary between the nTFT region and the pTFT region after the thermal activation step. In a complementary thin film transistor positioned on a substrate and having an nTFT region and a pTFT region, A buffer layer formed on the substrate material; A continuous crystallized silicon layer located on top of the buffer layer; An nTFT source in contact with the crystallized silicon layer of the nTFT region; A pTFT source in contact with said crystallized silicon layer in said pTFT region; A drain in contact with a boundary between the nTFT region and the pTFT region; An nTFT impurity ion implantation blocking film positioned on the nTFT layer and formed of a silicon oxide layer; A pTFT impurity ion implantation blocking film composed of a silicon oxide layer and a silicon nitride layer sequentially positioned on the crystallized silicon layer on the pTFT; A gate positioned on each of the impurity ion implantation blocking films; Complementary thin film transistor, characterized in that it comprises an interlayer insulating film located on top of the gate. The method of claim 6, Complementary thin film transistors, characterized in that the thickness of the silicon oxide layer and the silicon nitride layer is in the range of 300 to 600Å.

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