KR100980012B1 - Thin film transistor array panel - Google Patents

Abstract

The thin film transistor array panel according to the present invention includes a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors connected to the gate lines and the data lines, a plurality of pixel electrodes connected to the thin film transistors, the gate lines or the data. And a repair bar crossing the line, a shorting bar connected to the gate line and the data line, and an electrostatic discharge protection circuit connected between the shorting bar and the repair line and including at least one diode. In this way, the static electricity flowing into the repair line by the electrostatic discharge protection circuit flows into the shorting bar, and thus, even if the static electricity flows into the repair line of the thin film transistor array panel, the static electricity can be prevented from being transmitted to the display area.

Static electricity, diodes, shorting bars, repair lines, discharge protection circuit

Description

Thin film transistor array panel

1 is a schematic layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

2 is a layout view of one pixel of a thin film transistor array panel according to an exemplary embodiment of the present invention.

3 is a cross-sectional view of the thin film transistor array panel of FIG. 2 taken along a line III-III '.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to liquid crystal displays, and more particularly, to thin film transistor array panels for liquid crystal displays.

In general, a liquid crystal display device includes a liquid crystal layer having a field generating electrode for generating an electric field and having an anisotropic dielectric constant injected into two display panels spaced apart from each other with a predetermined gap and a gap between the two display panels. Such a liquid crystal display generates an electric field in the liquid crystal layer by applying a voltage to the field generating electrode, and displays an image by controlling the transmittance of light passing through the liquid crystal layer by adjusting the intensity of the electric field depending on the magnitude of the voltage.

In general, a liquid crystal display (LCD) has a field generating electrode for generating an electric field and has a dielectric anisotropy in the gap between the two display panels separated from each other with a predetermined gap. It includes. Such a liquid crystal display generates an electric field in the liquid crystal layer by applying a voltage to the field generating electrode, and displays an image by controlling the transmittance of light passing through the liquid crystal layer by adjusting the intensity of the electric field depending on the magnitude of the voltage.

Among the liquid crystal display devices, the liquid crystal display device includes a plurality of thin film transistors each having a plurality of pixel electrodes formed on one of the two display panels and switching voltages applied to the pixel electrodes. A display panel including a pixel electrode and a thin film transistor (hereinafter, referred to as a thin film transistor display panel) includes a plurality of gate lines and a plurality of data lines that transmit signals to the thin film transistors. The thin film transistor selectively transfers the data voltage transmitted through the data line to the pixel electrode according to the gate signal transmitted through the gate line.

Therefore, when the gate line or the data line is disconnected, the signal may not be properly transmitted to the thin film transistor, and further, the data voltage may not be transmitted to the pixel electrode, and thus the image may not be properly displayed.

There are various methods for repairing such disconnection defects in the gate line or data line. However, if the data line or gate line that crosses the display line has a repair line intersecting the data line and the gate line outside the display area. There is a method of transmitting a signal by detouring to the outside of the display area using a repair line.

However, since the repair line is located at the edge of the display panel, static electricity generated in the manufacturing process flows through the data line and the gate line intersecting the repair line on the repair line, and it is easy to destroy the thin film transistor.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array panel including an electrostatic discharge protection circuit capable of protecting elements of the display panel from electrostatic discharge.

In order to achieve the above object, the present invention provides the following thin film transistor array panel.

More specifically, a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors connected to the gate lines and the data lines, a plurality of pixel electrodes connected to the thin film transistors, and repairs intersecting the gate lines or the data lines. A shorting bar connected to a line, the gate line, and the data line, and a thin film transistor array panel connected between the shorting bar and the repair line and including at least one diode is provided.

The electrostatic discharge protection circuit may further include a conductive line formed along an edge of the peripheral area and connected to the repair line and the shorting bar through the diode.                     

In addition, the diode may be connected in a forward direction from the repair line toward the conductive wire and in the forward direction from the conductive wire toward the shorting bar.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Next, a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

As illustrated in FIG. 1, the thin film transistor array panel 100 according to an exemplary embodiment of the present invention has a plurality of gate lines G1 -Gn extending in a horizontal direction and a plurality of data lines D1 extending in a vertical direction. A plurality of pixel regions defined by the intersection of Dm) are divided into a display region A for displaying an image and a peripheral region B except for the display region A. FIG.

Each pixel area of the display area A includes a thin film transistor (not shown) connected to the gate lines G1 -Gn and the data lines D1 -Dm, the gate lines G1 -Gn through the thin film transistor, and A pixel electrode (not shown) is electrically connected to the data lines D1 -Dm. In addition, a storage electrode line (not shown) may be formed between the gate lines G1 -Gn that are adjacent to each other. This is to form a storage capacitor by overlapping the pixel electrode, and the gate lines G1 of the neighboring pixel rows. It is omitted when the storage capacitor is formed by overlapping Gn) with the pixel electrode.

In the peripheral area B, when the gate lines G1 -Gn and the data lines D1 -Dm are disconnected or short-circuited, the signals transmitted through them are detoured to the outside of the display area A to transmit signals. A pair of repair lines 61 and 62 are formed to intersect D1-Dm and the gate lines G1-Gn.

The shorting bar 40 is formed near the edge of the display panel 100, and the gate lines G1 -Gn and the data lines D1 -Dm extend to the peripheral area B outside the display area A and are shortened. It is connected to the bar 40. When static electricity flows into the gate lines G1 -Gn and the data lines D1 -Dm, the static electricity is spread and discharged over the entire display panel 100 through the shorting bar 40.

On the other hand, external static electricity may be easily introduced into the display area A through the repair lines 61 and 62. In order to effectively discharge such static electricity, an electrostatic discharge protection circuit 50 electrically connecting the repair lines 61 and 62 and the shorting bar 40 is provided.                     

The electrostatic discharge protection circuit 50 is disposed in the peripheral area B, and is provided with a guard ring disposed adjacent to the repair lines 61 and 62 at the edge of the display panel 100 without the shorting bar 40. The conductive dummy wiring 55 includes a plurality of electrostatic protection diodes D connected between the repair lines 61 and 62 and the conductive wiring 55 and between the conductive wiring 55 and the shorting bar 40. The diodes D between the repair lines 61 and 62 and the conductive lines 55 are alternately connected to the repair lines 61 and 62. The diode D between the repair lines 61 and 62 and the conductive line 55 has a forward direction from the repair lines 61 and 62 to the conductive line 55, and the conductive line 55 and the shorting bar 40 are in a forward direction. Since the direction of the diode (D) between the conductive wire 55 toward the shorting bar 40 is forward, the static electricity introduced to the repair lines 61 and 62 is shorted through the diode D and the conductive wire 55. Flow is discharged to the bar 40.

The electrostatic discharge protection circuit 50 according to another embodiment of the present invention includes a plurality of electrostatic protection diodes (not shown) connected between the repair lines 61 and 62 and the shorting bar 40. Static electricity generated in 62 may be directly flown to the shorting bar 40.

Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3.

2 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view of the thin film transistor array panel of FIG. 2 taken along line III-III ′.

A plurality of gate lines 121 are formed on the insulating substrate 110 to transfer gate signals. The gate line 121 mainly extends in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes 124. In addition, another portion of each gate line protrudes downward to form a plurality of expansions 127.

The gate line 121 includes two layers having different physical properties, that is, a lower layer 121p and an upper layer 121q thereon. The upper layer 212 is formed of a metal having a low resistivity, for example, aluminum-based metal such as aluminum (Al) or an aluminum alloy, so as to reduce delay or voltage drop of the gate signal. In contrast, the lower layer 211 is a material having excellent physical, chemical and electrical contact properties with other materials, particularly indium zinc oxide (IZO) or indium tin oxide (ITO), such as molybdenum (Mo) and molybdenum alloys (eg, molybdenum alloys). -Tungsten (MoW) alloy], chromium (Cr) and the like. An example of the combination of the lower layer 121p and the upper layer 121q may be a chromium / aluminum-neodymium (Nd) alloy. In FIG. 1, lower and upper layers of the gate electrode 124 are denoted by reference numerals 124p and 124q, and lower and upper layers of the expansion unit 127 are denoted by reference numerals 127p and 127q, respectively.

Side surfaces of the lower layer 121p and the upper layer 121q are inclined, respectively, and the inclination angle thereof is about 30 to 80 ° with respect to the surface of the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction, from which a plurality of extensions 154 extend toward the gate electrode 124. In addition, the linear semiconductor 151 increases in width near the point where the linear semiconductor 151 meets the gate line 121 to cover a large area of the gate line 121.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor 151. have. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined, and the inclination angle is 30 to 80 degrees.

The plurality of data lines 171, the plurality of drain electrodes 175, and the plurality of storage capacitors are disposed on the ohmic contacts 161 and 165 and the gate insulating layer 140, respectively. conductor 177 is formed.

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 124. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. A protrusion 154 is formed between the electrode 173 and the drain electrode 175.

The storage capacitor conductor 177 overlaps the extension portion 127 of the gate line 121.

The data line 171, the drain electrode 175, and the conductor 177 for the storage capacitor are also inclined at an angle of about 30 to 80 °, similarly to the gate line 121.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 above and serve to lower the contact resistance. The linear semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175 and is not covered by the data line 171 and the drain electrode 175, and in most places, the linear semiconductor 151 is provided. Although the width of is smaller than the width of the data line 171, as described above, the width becomes larger at the portion that meets the gate line 121 to strengthen the insulation between the gate line 121 and the data line 171.

On the data line 171, the drain electrode 175, the conductive capacitor 177 for the storage capacitor, and the exposed portion of the semiconductor 151, an organic material having excellent planarization characteristics and photosensitivity, plasma chemical vapor deposition (plasma) A passivation layer 180 made of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F formed by enhanced chemical vapor deposition (PECVD), or silicon nitride, which is an inorganic material, is formed. It is.

The passivation layer 180 includes a plurality of contact holes 182, 185, and 187 exposing the end portion 179 of the data line 171, the drain electrode 175, and the conductive capacitor conductor 177, respectively. A plurality of contact holes 181 are formed along with the gate insulating layer 140 to expose the ends of the gate lines 121.

A plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 made of IZO or ITO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 and the storage capacitor conductor 177 through the contact holes 185 and 187, respectively, to receive a data voltage from the drain electrode 175, and to connect the conductor. Transfer data voltage to 177.

The pixel electrode 190 to which the data voltage is applied generates an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied, thereby generating an electric field between the two electrodes 190 and 270. Rearrange the liquid crystal molecules of the liquid crystal layer.

In addition, the pixel electrode 190 and the common electrode form a capacitor (hereinafter referred to as a liquid crystal capacitor) to maintain an applied voltage even after the thin film transistor is turned off, and in parallel with the liquid crystal capacitor to enhance the voltage holding capability. Other capacitors are connected to each other and are called storage electrodes. The storage capacitor is formed by overlapping the pixel electrode 190 and the neighboring gate line 121 (which is called a prior gate line), and the like to increase the capacitance of the storage capacitor, that is, the storage capacitance. An extension part 127 extending the line 121 is provided to increase the overlapped area, while the conductive capacitor conductor 177 is connected to the pixel electrode 190 and overlaps the extension part 127. Place it underneath to bring the distance between the two closer.

The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap.

The contact auxiliary members 81 and 82 are connected to the end portion of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 complement the adhesion between the gate line 121 and the data line 171 and the external device and protect them, and their application is optional.

According to another embodiment of the present invention, a transparent conductive polymer may be used as the material of the pixel electrode 190, and in the case of a reflective liquid crystal display, an opaque reflective metal may be used. In this case, the contact assistants 81 and 82 may be made of a material different from the pixel electrode 190, in particular, IZO or ITO.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, an electrostatic discharge protection circuit connecting the repair line and the shorting bar is added to the peripheral area of the thin film transistor array panel to prevent the static electricity from being transmitted to the display area even if static electricity flows into the repair line of the thin film transistor array panel. can do.

Accordingly, a high quality thin film transistor array panel can be provided by minimizing defects caused by static electricity.

Claims (3)

A plurality of gate lines and a plurality of data lines, A plurality of thin film transistors connected to the gate line and the data line, A plurality of pixel electrodes connected to the thin film transistor, A repair line crossing the gate line or the data line, A shorting bar connected to the gate line and the data line, and An electrostatic discharge protection circuit connected between the shorting bar and the repair wire and including at least one diode Thin film transistor array panel comprising a. In claim 1, The electrostatic discharge protection circuit further comprises a conductive line connected to the repair line and the shorting bar through the diode. In claim 2, And the diode is connected in a forward direction from the repair line toward the conductive wiring and in a forward direction from the conductive wiring toward the shorting bar.

Images