KR100976411B1

KR100976411B1 - Electrostatic discharge circuit

Info

Publication number: KR100976411B1
Application number: KR20080049871A
Authority: KR
Inventors: 최낙헌
Original assignee: 주식회사 하이닉스반도체
Priority date: 2008-05-28
Filing date: 2008-05-28
Publication date: 2010-08-17
Also published as: KR20090123676A

Abstract

The electrostatic discharge circuit of the present invention includes a first diffusion region formed in a first type well and a second type well adjacent to each other and the first type well, to which an input / output pad connected to an internal circuit is connected, and the first type well and the second well. A second diffusion region formed across the interface of the wells and connected to a power supply voltage pad and a third diffusion region formed in the second type well and connected to a ground voltage pad and a third diffusion region in the second type well; And a capacitor having one end connected to the fourth diffusion region and the second diffusion region formed to be isolated from the second diffusion region, and a third diffusion region connected to the other end.

Description

Electrostatic Discharge Circuit {ELECTROSTATIC DISCHARGE CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an electrostatic discharge circuit used to prevent a phenomenon in which a defect occurs in a semiconductor device due to an electrostatic discharge phenomenon caused by static electricity.

In general, semiconductor chips may be subject to static electricity stored in themselves or in devices to be mounted. Accordingly, mass-produced semiconductor chips include electrostatic discharge circuits on data input / output pads and power pads of the semiconductor element to protect the semiconductor element from static electricity.

As such an electrostatic discharge circuit, a diode, a metal oxide scilicon (MOS) device, a bipolar junction transistor device (BJT), a silicon voltage controlled rectifier (Low Voltage Scilicon Controlled Rectifier (LVTSCR)) is widely used.

The dual diode has advantages of large extinguishing ESD current and small junction capacitance per unit area, but has a problem in that the operation resistance is large and its use is limited.

Morse devices have lower triggering voltage and lower operating resistance, but the ESD current that can be extinguished per unit area is smaller than 1/3 or 1/5 of diode or LVTSCR. As a result, there is a problem in that the junction capacitor becomes large using a large area.

On the other hand, LVTSCR has many advantages of extinguishing ESD current, small junction capacitance and small operating resistance per unit area.However, it is difficult to cope with high-speed and low-voltage circuits because of high and unstable operation trigger voltage when ESD transistor occurs. there is a problem.

1 is a diagram showing an electrostatic discharge circuit of a semiconductor device according to the prior art. Referring to FIG. 1, the LVTSCR circuit 100 includes a PNP bipolar transistor 150, an NPN bipolar transistor 130, and resistors 110 and 170.

The two MOS transistors 101, 103 and resistor 105 are for supplying a triggering voltage for operating the LVTSCR circuit 100.

When external static electricity is generated and input to an input / output pin (not shown), a voltage generated from the resistor 105 is supplied to the LVTSCR circuit 100 as a triggering voltage, and the bipolar transistors 130 and 150 are driven by the triggering voltage Vtr. Is turned on to discharge the input static signal.

The LVTSCR circuit 100 operates at a relatively low voltage once it is triggered when an electrostatic signal is generated and input, and thermal damage occurs because the local area concentration of the electrostatic current generated by the electrostatic signal is significantly low. It has a relatively small advantage.

On the other hand, LVTSCR circuit 100 has a disadvantage that the triggering voltage is higher than the general static protection circuit. Accordingly, techniques for lowering the triggering voltage of the LVTSCR circuit 100 have been developed. An example of this is a technique for lowering the triggering voltage by a voltage applied to the resistor 105 by including a circuit for supplying a triggering voltage as shown in FIG. to be.

However, in order to lower the triggering voltage, NMOS transistors 101 and 103 and resistor 105 must be separately provided, and these devices have a disadvantage in that the chip size is increased.

The present invention provides an electrostatic discharge circuit for efficiently discharging static electricity introduced into input / output pads and power pads from the outside.

In addition, the present invention provides an electrostatic discharge circuit capable of protecting the internal circuit connected to the input / output pad by quickly discharging the static electricity flowing into the input / output pad and the power pads.

In addition, the present invention provides an electrostatic discharge circuit for improving the area efficiency while implementing a fast operation in the electrostatic discharge circuit using the LVTSCR circuit.

The electrostatic discharge circuit of the present invention comprises a first type well and a second type well adjacent to each other; A first diffusion region formed in the first type well and connected to an input / output pad connected to an internal circuit; A second diffusion region formed at an interface between the first type well and the second type well and connected to a power supply voltage pad; A third diffusion region formed in the second type well and connected to a ground voltage pad; A fourth diffusion region formed in the second type well so as to be isolated from a third diffusion region; And a capacitor having one end connected to the second diffusion region and the third diffusion region connected to the other end.

It is preferable that the first type well is an N well region and the second type well is a P well region.

The first and fourth diffusion regions are P-type impurities, and the second and third diffusion regions are N-type impurities.

In addition, it is preferable to configure an NMOS transistor having the second and third diffusion regions as a drain and a source and a gate additionally provided between the second and third diffusion regions, and a gate connected to the ground voltage terminal.

The display device may further include a diode connected between the input / output pad and the ground voltage pad.

The electrostatic discharge circuit of the present invention is configured between a power supply voltage terminal and a ground voltage terminal, and discharges static electricity by an inflow of static electricity from an input terminal connected to an input / output pad connected to an internal circuit, and induces an amount of static electricity flowing into the input terminal. And controlling the connection between the power supply voltage terminal and the ground voltage terminal to control the discharge, the LVTSCR circuit and a capacitor connected between the power supply voltage terminal and the ground voltage terminal and stabilizing the potential of the power supply voltage terminal. do.

The LVTSCR circuit may include a PNP bipolar transistor and a resistor connected in series between the input terminal and the ground voltage terminal; And an NPN bipolar transistor configured between the ground voltage terminal and the power supply voltage terminal, wherein the PNP bipolar transistor and the NPN bipolar transistor are coupled to each other by a base and a collector.

In the NPN bipolar transistor, a parasitic NMOS transistor in which a source and a drain are covalently coupled is preferably formed in parallel.

In addition, the capacitor unit is preferably composed of a capacitor using a capacitor or a MOS transistor in which the source and the drain are connected in bulk.

Further, by further connecting a diode between the input / output pad and the ground voltage terminal, a negative electrostatic current flowing into the input / output pad may be discharged.

The electrostatic discharge circuit according to the present invention can stably protect the internal circuit of the semiconductor device from static electricity by lowering the operation start voltage of the LVTSCR circuit for discharging static electricity.

In addition, the electrostatic discharge circuit according to the present invention can increase the area efficiency by using an internal circuit to lower the operation start voltage of the transistor element.

The present invention proposes an electrostatic discharge circuit for quickly operating an LVTSCR circuit and increasing the area efficiency of the LVTSCR circuit to protect internal circuits connected to the input / output pad and the power pad from static electricity.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a cross-sectional view showing the LVTSCR structure of the present invention, Figure 3 is an equivalent circuit diagram corresponding to FIG.

Referring to FIG. 2, the LVTSCR circuit 200 of the present invention is configured between a power supply voltage terminal VDD and a ground voltage terminal VSS, and is connected to an input / output pad (I / O) connected to an internal circuit 250. The static electricity is discharged in response to the inflow of static electricity from the input terminal. In the discharge operation, the connection between the power supply voltage terminal VDD and the ground voltage terminal VSS is controlled according to the amount of static electricity flowing into the input / output pad I / O.

In detail, when a positive electrostatic current flows into the input / output pad I / O, the electrostatic current flows from the emitter of the PNP transistor 210 to the base and flows to the capacitor 201 connected to the base side.

Here, the capacitor 201 is connected to the base of the PNP transistor 210 and the ground voltage terminal VSS, thereby inducing the flow of an electrostatic alternating current, thereby rapidly driving the LVTSCR circuit 200.

In addition, the capacitor 201 may use, for example, a reservoir capacitor connected between the power supply voltage terminal VDD and the ground voltage terminal VSS to reduce noise of the power supply.

The electrostatic current, which is the base current of the PNP transistor 210, causes the collector operation of the PNP transistor 210, and flows through the resistor 230 through the collector to the ground voltage terminal VSS. The NPN transistor 222 is turned on by increasing the potential, that is, the base voltage of the NPN transistor 222.

Accordingly, the LVTSCR circuit 200 is turned on, and the electrostatic current flowing into the input / output pads I / O flows from the emitter of the PNP transistor 210 to the emitter of the NPN transistor 222, thereby causing the ground voltage terminal VSS. Will be discharged.

The diode 202 serves to discharge the negative electrostatic current to the ground voltage terminal VSS when a negative electrostatic current flows into the input / output pad I / O.

Conventionally, since two transistor elements and a resistance element are provided to supply a triggering current to an LVTSCR circuit, the area consumed in terms of layout in a chip has a large disadvantage.

In order to compensate for this, the electrostatic discharge circuit of the present invention can drive the LVTSCR circuit 200 by using a conventional capacitor used in a semiconductor device, thereby not only driving the LVTSCR circuit 200 quickly but also in terms of layout area. It has the advantage of increasing efficiency.

Referring to the cross-sectional view of the LVTSCR circuit 200 according to the present invention with reference to Figures 2 and 3, the substrate is sequentially divided into adjacent P well 310, N well 320, P well 330.

P-type impurity diffusion region 340 is formed inside N well 320, and N-type impurity diffusion region 342 is formed at the boundary between N well 320 and P well 330. An diffusion region 344 of N-type impurities and a diffusion region 346 of P-type impurities are formed in 330.

In the P type well 310, a diffusion region 350 of P type impurities and a diffusion region 352 of N type impurities are formed, and the diffusion region 352 and the P type well 310 form a diode 202. .

The diffusion region 344 and the diffusion region 350 are connected to the ground voltage pad VSS, and the diffusion region 340 and the diffusion region 352 are connected to the input / output pad I / O and the internal circuit 250. .

The diffusion region 342, the diffusion region 344, and the gate 348 constitute the NMOS transistor 220, and the diffusion region 342 is connected to the power supply voltage pad VDD and the capacitor 201.

The LVTSCR circuit 200 has a PNPN structure including a diffusion region 340 of P type impurities, an N well 320, and a diffusion region 346 of P type impurities.

The LVTSCR circuit 200 according to the present invention uses a diffusion region in order not to depend on the avalanche breakdown voltage of the NP junction formed of the diffusion region 342 of the N-type impurity and the P-type well 330. The 342 and the diffusion region 344 are connected through the capacitor 201. That is, the diffusion region 342 and the diffusion region 344 are electrically connected to each other through the external capacitor 201.

Next, the operation of the LVTSCR of the present invention will be described.

When an electrostatic current flows into the I / O pad, the electrostatic current initially in an AC state has a fast signal rising time of 10 ns. Flow through the base of the PNP bipolar transistor 210 to the capacitor 201.

In addition, the AC current rapidly triggers the operation of the PNP bipolar transistor 210 by supplying a current to the base of the PNP bipolar transistor 210. The alternating current of the collector of the PNP bipolar transistor 210 is transferred to the ground voltage pad VSS through the resistor 230 to be discharged.

In addition, the AC current is a voltage corresponding to the AC current * resistance 230 between the diffusion region 344 which is the emitter of the NPN bipolar transistor 222 and the diffusion region 346 which is the base due to the resistance element 230. The drop causes a rapid operation of the NPN bipolar transistor 222. That is, the NPN bipolar transistor 222 is turned on by supplying a bias corresponding to the alternating current * resistance 230 between the base and the emitter of the NPN bipolar transistor 222.

Afterwards, the NPN bipolar transistor 222 and the PNP bipolar transistor 210 in which the collectors and the bases are coupled to each other have a low operating resistance and a large electrostatic current even with a small area because one operation mutually promotes the other. High efficiency electrostatic discharge operation to extinguish.

Thus, unlike the conventional LVTSCR circuit of FIG. 2 operating when the conventional LVTSCR circuit of FIG. 1 reaches the avalanche breakdown voltage of the NP junction, the electrostatic alternating current induced by the capacitor 201 is based on the PNP bipolar transistor. By supplying current, the PNP bipolar transistor 210 and the NPN bipolar transistor 222 are quickly turned on.

Thus, the LVTSCR circuit of the present invention operates at a much lower voltage than conventional LVTSCR circuits.

Meanwhile, the capacitor 201 may use, for example, a reservoir capacitor connected between the power supply voltage pad VDD and the ground voltage pad VSS to reduce noise of the power supply. Thus, by utilizing the capacitor used in the past, the area efficiency can be increased.

The diode 202 is composed of a sixth diffusion region 352 and a P-type well 310, and when the negative static current flows into the input / output pad I / O, the diode 202 receives the negative static current from the ground voltage pad VSS. It serves to discharge.

In the related art, since two transistor elements and resistance elements are provided to supply a triggering current to an LVTSCR circuit, a large area is occupied in terms of layout in a chip.

Electrostatic discharge circuit 200 of the present invention to compensate for this to drive the LVTSCR circuit 200 by using a capacitor used in the internal circuit not only to drive the LVTSCR circuit 200 quickly, but also in terms of layout area efficiency Height has an advantage.

4 is a circuit diagram of the electrostatic discharge circuit 400 according to the present invention connected to a semiconductor device employing multiple power supply voltages.

The electrostatic discharge circuit 400 according to the present invention may be employed in a semiconductor device circuit employing multiple power supply voltages.

The diode 402 is employed between the first power voltage pad VDD1 and the ground voltage pad VSS, and the LVTSCR circuit 400 is connected between the first power voltage pad VDD1 and the internal circuit 450. The second power supply voltage pad VDD2 is connected to the collector of the NPN bipolar transistor 422, which is a parasitic transistor of the NMOS transistor 420.

Since the configuration and operation of the electrostatic discharge circuit including the LVTSCR circuit 400 and the capacitor 401 are the same as those of the electrostatic discharge circuit described with reference to FIGS. 2 and 3, a detailed description thereof will be omitted.

5 is a result of simulating the effect of lowering the driving voltage of the LVTSCR circuit in the capacitor configured as the electrostatic discharge circuit of the present invention to drive the LVTSCR circuit.

Increasing the capacitance of the capacitor from 0.01pF to 1nF, it can be seen that the initial operating voltage decreases from 5.3V to 1.7V.

The present invention configured as described above has the advantage that it is possible to secure the chip area more than the existing technology without the need for additional devices while operating the LVTSCR circuit, ESD protection device fast.

1 is a conventional electrostatic discharge circuit diagram.

2 is an electrostatic discharge circuit diagram of the present invention.

3 is a cross-sectional view of an electrostatic discharge circuit of the present invention.

4 is an electrostatic discharge circuit diagram of another embodiment of the present invention.

5 is a simulation diagram of the electrostatic discharge circuit of the present invention.

Claims

Type 1 and type 2 wells adjacent to each other;

A first diffusion region formed in the first type well and connected to an input / output pad connected to an internal circuit;

A second diffusion region formed over an interface between the first type well and the second type well and connected to a power supply voltage pad;

A third diffusion region formed in the second type well and connected to a ground voltage pad;

A fourth diffusion region formed in the second type well so as to be isolated from a third diffusion region; And

A capacitor having one end connected to the second diffusion region and the third and fourth diffusion regions connected to the other end;

Electrostatic discharge circuit, characterized in that comprises a.

The method of claim 1,

And the first type well is an N well region, and the second type well is a P well region.

The method of claim 1,

The first and fourth diffusion regions are

An electrostatic discharge circuit comprising p-type impurities, and wherein the second and third diffusion regions are N-type impurities.

The method of claim 1,

And an NMOS transistor, wherein the second and third diffusion regions constitute a drain and a source, and the NMOS gate is connected to the ground voltage pad.

The method of claim 1,

And a diode connected between the input / output pad and the ground voltage pad.

It is configured between a power supply voltage terminal and a ground voltage terminal, and discharges static electricity by the inflow of static electricity from an input terminal connected to an input / output pad connected to an internal circuit, and the power voltage terminal and the ground voltage according to the inflow amount of the static electricity flowing into the input terminal. An LVTSCR circuit in which the discharge is controlled by controlling the connection between the stages; And

A capacitor connected between the power supply voltage terminal and the ground voltage terminal to stabilize the potential of the power supply voltage terminal;

Electrostatic discharge circuit comprising a.

The method of claim 6,

The LVTSCR circuit is

A PNP bipolar transistor and a resistor connected in series between the input terminal and the ground voltage terminal; And

And an NPN bipolar transistor configured between the ground voltage terminal and the power supply voltage terminal, wherein the PNP bipolar transistor and the NPN bipolar transistor are coupled so that a base and a collector are cross coupled.

The method of claim 7, wherein

The NPN bipolar transistor

An electrostatic discharge circuit in which parasitic NMOS transistors in which a source and a drain are covalently coupled are formed in parallel.

The method of claim 6,

The capacitor is

An electrostatic discharge circuit implemented with a capacitor element or a MOS transistor in which a source and a drain are connected in bulk.

The method of claim 6,

And a diode further connected between the input / output pad and the ground voltage terminal to discharge a negative electrostatic current flowing into the input / output pad.