KR100973803B1 - Liquid crystal display - Google Patents

Abstract

A gate line, a data line intersecting the gate line, a switching element connected to the gate line and the data line, respectively, a pixel electrode connected to the switching element, a gate line and a data line, spaced apart from the switching element and the pixel electrode, A driving circuit connecting line for connecting between driving circuits for supplying a driving signal, a data line contact auxiliary member for assisting the connection of the driving circuit and the data line, and a connecting line contact auxiliary member for assisting the connection of the driving circuit connecting line and the driving circuit; The connecting line contact auxiliary member includes a first portion covering an exposed portion of the driving circuit connecting line and a second portion extending along the driving circuit connecting line by a predetermined length and used as a pad to which the prop tip contacts during the gross test. .

LCD, Gross Test, Driver Circuit Connection

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a conceptual diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 4 is a layout view illustrating a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, in which the gate line, the data line, and an intersection region thereof of FIG. 3 are enlarged.

FIG. 5 is a cross-sectional view of the thin film transistor array panel of FIG. 4 taken along the line VV ′.

FIG. 6 is an enlarged layout view of portion A of FIG. 3 according to an exemplary embodiment of the present invention.

7 is an enlarged layout view of a vicinity of a connection portion between a data line and an inspection line according to an exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view taken along the line VII-VII 'of FIG. 7.

9 is an enlarged layout view of a portion B of FIG. 3 according to an exemplary embodiment of the present invention.

FIG. 10 is a cross-sectional view taken along line X-X 'of FIG. 9.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to liquid crystal displays, and more particularly, to thin film transistor array panels for liquid crystal displays.

A general liquid crystal display (LCD) includes a liquid crystal layer having dielectric anisotropy interposed between two display panels. The desired image is obtained by applying an electric field to the liquid crystal layer and adjusting the intensity of the electric field to adjust the transmittance of light passing through the liquid crystal layer. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

In the display panel on which the thin film transistor is formed, a plurality of gate lines and data lines are formed in row and column directions, respectively, and pixel electrodes connected to the gate lines and data lines are formed through the thin film transistors. The thin film transistor controls the data signal transmitted through the data line according to the gate signal transmitted through the gate line and transmits the data signal to the pixel electrode. The gate signal is generated by combining a plurality of gate driving integrated circuits (ICs) supplied with the gate on voltage V _on and the gate off voltage V _off generated by the driving voltage generator according to control from the signal controller. The data signal is obtained by converting the gradation signal from the signal controller into a plurality of data driving ICs into analog voltages. The signal control unit and the driving voltage generator are usually provided on a printed circuit board (PCB) located outside the display panel, and the driving IC is a flexible printed circuit (FPC) board located between the PCB and the display panel. It is mounted on the top. Two PCBs are usually placed in this case, one above and one left of the display panel. The left one is called a gate PCB and the top one is called a data PCB. A gate driver IC is positioned between the gate PCB and the display panel, and a data driver IC is positioned between the data PCB and the display panel, and receives signals from the corresponding PCB.

The gate and data driving ICs may be attached by a tape carrier package (TCP) mounting method and a chip on glass (COG) method. The TCP method is a method of attaching a tape attached with a driving chip to a thin film transistor array panel separately, and the COG method is a method of attaching a drive IC directly on an insulating substrate of a thin film transistor array panel. Conventionally, the TCP method is mainly used, but the COG method is mainly used due to the reduction of the area occupied by the chip and the cost reduction.

After the driving circuit is attached to the thin film transistor array panel, a visual inspection or a gross test is performed to inspect the defect of the thin film transistor array panel.

Visual inspection forms an inspection line connecting each data line or gate line to one, and performs inspection through the inspection line, and then disconnects the inspection line from the wiring using a laser.

The gross test is performed by touching the probe tip directly to each signal line.

However, unlike visual inspection in the COG method, the gross test requires an inspection pad for gross testing because the probe tips that are arranged at regular intervals must be in direct contact with each signal line. As a result, in order to provide a separate test pad for gross testing on the substrate, not only the process margin of the substrate is insufficient but also the process time is long.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor display panel that can be easily gross-tested by using a signal line inspection pad positioned between a bumper and a signal line of a COG driving chip.

A liquid crystal display according to an exemplary embodiment of the present invention includes a gate line, a data line intersecting the gate line, a switching element connected to one of the gate lines and one of the data lines, and a switching element connected to the switching element. A driving circuit connection line spaced apart from the pixel electrode, the gate line and the data line, the switching element, and the pixel electrode, for connecting a driving circuit for supplying a driving signal to the data line, the driving circuit and the A data line contact assistant member for assisting the connection of a data line, and a connection line contact assistant member for assisting the connection of the driving circuit connection line and the drive circuit, wherein at least one of the data line contact assistant member and the connection line contact assistant member is provided. The first portion and the data line covering the exposed portion of the data line or the driving circuit connection line, or It is extended by the same circuit in accordance with a predetermined connection line length and a second portion for use as a pad for the gloss test when prop tip contact.

At this time, to assist the connection between the driving circuit and the gate line, the first portion covering the exposed portion of the gate line and extending along the gate line by a predetermined length to use as a pad contact the probe tip during the gross test And a gate line contact assistant member having a second portion, wherein the gate line contact assistant member, the data line contact assistant member, and the driving circuit connection line contact assistant member are made of ITO or IZO.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

1 is a conceptual diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display according to the present invention includes a liquid crystal panel assembly 300, a gate driver 400 and a data driver 500 connected thereto. The driving voltage generator 700 connected to the gate driver 400, the gray voltage generator 800 connected to the data driver 500, and a signal controller for controlling the driving voltage generator 700 are connected to the gate driver 400. It contains 600.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected thereto in an equivalent circuit, and each pixel includes a display signal line G _1. A switching element Q connected to -G _n , D ₁ -D _m ), and a liquid crystal capacitor C _lc and a storage capacitor C _st connected thereto. The display signal lines G ₁ -G _n and D ₁ -D _m transmit a scanning signal or a gate signal, and the plurality of scanning signal lines or gate lines G ₁ -G _n extending in the row direction. ) And a data signal line or data line D ₁ -D _m which transmits an image signal or a data signal and extends in the column direction. The switching element Q is a three-terminal element, the control terminal of which is connected to the gate line G ₁ -G _n , the input terminal of which is connected to the data line D ₁ -D _m , and the output terminal of the liquid crystal capacitor ( C _lc ) and one terminal of the holding capacitor C _st .

The liquid crystal capacitor C _lc is connected to the output terminal of the switching element Q and a common voltage V _com or a reference voltage. The other terminal of the holding capacitor C _st is connected to another voltage, for example a reference voltage. However, the other terminal of the holding capacitor C _st may be connected to the gate line directly above (hereinafter referred to as "previous gate line"). The former is called a separate wire type and the latter is called a prior gate type.

Meanwhile, the liquid crystal panel assembly 300 may be schematically illustrated as shown in FIG. 2. For convenience, only one pixel is shown in FIG. 2.

As shown in FIG. 2, the liquid crystal panel assembly 300 includes a lower panel 100 and an upper panel 200 facing each other and a liquid crystal layer 3 therebetween. The lower panel 100 includes gate lines G _i-1 , G _i , a data line D _j , a switching element Q, and a storage capacitor C _st . The liquid crystal capacitor C _lc has two terminals as the pixel electrode 190 of the lower panel 100 and the reference electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270 is It functions as a dielectric.

The pixel electrode 190 is connected to the switching element Q, and the reference electrode 270 is formed on the entire surface of the upper panel 200 and is connected to the common voltage V _com .

Herein, the liquid crystal molecules change their arrangement according to the change of the electric field generated by the pixel electrode 190 and the reference electrode 270, and thus the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

In the pixel electrode 190, a separate signal line to which a reference voltage is applied is provided on the lower panel 100 to overlap the pixel electrode 190 to form the storage capacitor C _st . For the previous gate way form the two terminals of the pixel electrode 190 is maintained with a previous gate line (G _i-1) by being overlapped with the previous gate line (G _i-1), an insulator as a medium capacitor (C _st).

FIG. 2 shows a MOS transistor as an example of the switching element Q, which is implemented as a thin film transistor having amorphous silicon or polysilicon as a channel layer in an actual process.

Unlike in FIG. 2, the reference electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be formed in a linear or bar shape.

On the other hand, in order to implement color display, each pixel should be able to display color, which is provided with a color filter 230 of red, green, or blue in a region corresponding to the pixel electrode 190. It is possible by doing. The color filter 230 is mainly formed in the corresponding region of the upper panel 200 as shown in FIG. 2, but may be formed above or below the pixel electrode 190 of the lower panel 100.

Referring back to FIG. 1, the driving voltage generator 700 generates a gate on voltage V _on for turning _{on the} switching element Q, a gate off voltage V _off for turning off the switching element Q, and the like. do.

The gray voltage generator 800 generates a plurality of gray voltages related to the luminance of the liquid crystal display.

The gate driver 400 may also be referred to as a scan driver. The gate driver 400 may be connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to provide a gate-on voltage V _on from the driving voltage generator 700. And a gate signal composed of a combination of the gate off voltage V _off are applied to the gate lines G ₁ -G _n .

In addition, the data driver 500 may also be referred to as a source driver. The data driver 500 may be connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 to select a gray voltage from the gray voltage generator 800 to select data. It is applied to the data lines D ₁ -D _m as signals.

The signal controller 600 generates a control signal for controlling operations of the gate driver 400, the data driver 500, and the driving voltage generator 700, and outputs corresponding control signals to the gate driver 400 and the data. The driving unit 500 and the driving voltage generator 700 are supplied.

Next, the structure of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIG. 3.

3 is a layout view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 3, a signal controller 600 for driving a liquid crystal display device is disposed above the liquid crystal panel assembly 300 including the gate lines G ₁ -G _n and the data lines D ₁ -D _m . ), A printed circuit board (PCB) 550 including circuit elements such as the driving voltage generator 700 and the gray voltage generator 800 is located. The liquid crystal panel assembly 300 and the PCB 550 are electrically and physically connected to each other through the flexible printed circuit (FPC) substrates 511 and 512.

The leftmost FPC board 511 A plurality of data transfer lines 521 and a plurality of drive signal lines 522 and 523 are formed. The data transmission line 521 is connected to an input terminal of the data driving IC 540 through a lead wire 321 formed in the assembly 300 to transmit a gray level signal. The driving signal lines 522 and 523 respectively supply power voltages and control signals required for the operation of the driving ICs 540 and 440 through the lead wires 321 and the driving signal lines 323 formed in the assembly 300. , 440).

The other FPC board 512 is provided with a plurality of driving signal lines 522 for transmitting driving and control signals to the data driving IC 540 connected thereto.

These signal lines 521-523 are connected to and receive signals from circuit elements of the PCB 550.

The driving signal line 523 may be formed on a separate FPC substrate.

As shown in FIG. 3, a plurality of pixel regions defined by the intersection of the horizontal gate lines G ₁ -G _n and the vertical data lines D ₁ -D _m provided in the liquid crystal panel assembly 300 are formed. The display area D which collects and displays an image is comprised. A black matrix 220 is provided outside the display area D to block light leaking out of the display area D. FIG. The gate lines G ₁ -G _n and the data lines D ₁ -D _m remain substantially parallel in the display area D, respectively. Gathered together, the gap between them narrows and becomes substantially parallel again. This area is called the fan out area.

A plurality of data driver ICs 540 are sequentially mounted in the horizontal direction at an upper edge of the liquid crystal panel assembly 300 outside the display area D. FIG. Inter-IC connection lines 541 are formed between the data driver ICs 540, and the gray level signal supplied to the leftmost data driver IC 540 through the FPC board 511 is transferred to the next data driver IC 540. Pass in turn.

In addition, one or more VI test lines 125 may be formed under each data driver IC 540. Each inspection line 125 extends mainly in the horizontal direction, one side of which extends upward, and an inspection pad 126 is connected to an end thereof. Data lines D ₁ -D _m are connected to each test line 125, and when the number of test lines 125 is two or more, the connection between the test line 125 and the data lines D ₁ -D _m is alternately performed. Is done. For example, in FIG. 3, there are two inspection lines 125, the upper inspection line 125 has odd-numbered data lines D ₁ , D ₃ , ..., and the lower inspection line 125 has even-numbered data. The lines (D ₂ , D ₄ , ...) are connected.

The test pad 126 may be a portion at which the FPC boards 511 and 512 and the assembly 300 are electrically connected, or a point where a signal is applied to the data line D ₁ -D _m above the data driver IC 540. It is arranged at the top. As such, since the test pad 126 and the test line 125 are not disposed between the data driver ICs 540 and are disposed on the data driver ICs 540, the test pads 126 and the test line 125 are not disposed between the data driver ICs 540. It can be formed almost in a straight line to reduce wiring resistance, signal delay, and the like.

In addition, four gate driving ICs 440 are mounted side by side in the vertical direction at the left edge of the liquid crystal panel assembly 300. The plurality of driving signal lines 323 described above are formed near the gate driving IC 440. These driving signal lines 323 electrically connect the driving signal lines 523 of the FPC board 511 and the gate driving IC 440 or the gate driving IC 440.

In addition, two signal lines 323 adjacent to the display area D of the driving signal lines 323 are alternately connected to the gate lines G _{1 to} G _n . One end of these signal lines 323 is provided with gate lines G ₁ -G _n and inspection pads 323p for inspecting the state of the pixels, respectively.

As described above, the liquid crystal panel assembly 300 includes two display panels 100 and 200, and the lower panel 100 having the double thin film transistor is referred to as a "thin film transistor display panel". In FIG. 3, since the driving signal line 323, the lead wire 321, the connection line 541, the VI test line 125, and the test pad 126 are provided in the thin film transistor array panel 100, the thin film transistor array panel 100 is provided. The structure of) will be described in detail with reference to FIGS. 4 to 10.

FIG. 4 is a layout view illustrating a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, in which the gate line, the data line, and an intersection region of FIG. 3 are enlarged, and FIG. 5 is a thin film transistor array panel of FIG. 4. Is a cross-sectional view taken along the line VV '. FIG. 6 is an enlarged layout view of portion A of FIG. 3 according to an exemplary embodiment of the present invention. FIG. 7 is an enlarged layout view showing a vicinity of a connection portion between a data line and an inspection line according to an exemplary embodiment of the present invention, and FIG. 8 is a cross-sectional view taken along the line VII-VII 'of FIG. 7. FIG. 9 is an enlarged layout view illustrating a portion B of FIG. 3 according to an exemplary embodiment of the present invention, and FIG. 10 is a cross-sectional view taken along line X-X 'of FIG. 9.

A plurality of gates made of a metal or a conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten alloy (MoW), chromium (Cr), tantalum (Ta) and the like on the insulating substrate 110 A line 121, a pair of inspection lines 125, and a plurality of lead lines 321 are formed.

The gate line 121 mainly extends in the horizontal direction, and part of the gate line 121 becomes the gate electrode 124.

Each inspection line 125 mainly extends in the horizontal direction, and its end portion extends upward to become the inspection pad 126. As shown in FIG. 6, the lower inspection line 125 is connected to an odd data line and the upper inspection line 125 is connected to an even data line. The test pad 126 is disposed between the lead wires 321.

The gate line 121, the inspection line 125, and the lead line 321 may be formed in a single layer, or may be formed in two or more layers. In this case, it is preferable that one layer is formed of a material having a low specific resistance and the other layer is formed of a material having good contact properties with other materials, for example, a double film of chromium and an aluminum alloy or a double film of molybdenum or molybdenum alloy and aluminum. Can be.

The driving signal line 323 shown in FIG. 3 is also formed of the same layer as the gate line 121.

The gate insulating layer 140 made of silicon nitride (SiN _X ) is formed on the gate line 121, the inspection line 125, and the lead line 321.

A plurality of island type semiconductors 154 made of hydrogenated amorphous silicon are formed on the gate insulating layer 140 on the gate electrode 124, and a high concentration of n-type impurities such as phosphorus (P) is formed on the semiconductor 154. A plurality of pairs of ohmic contacts 163 and 165 formed of semiconductors, such as hydrogenated amorphous silicon, are doped with each other, and each pair of contact members 163 and 165 are separated on both sides of the gate electrode 124. have.

On the ohmic contacts 163 and 165 and the gate insulating layer 140, a plurality of data lines 171 and drain electrodes 175 made of a metal or a conductor such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, chromium, tantalum, or the like. And an IC connection line 541 is formed.

Each data line 171 mainly extends in the vertical direction, and its branches extend to form a plurality of source electrodes 173. The drain electrode 175 faces the source electrode 173 around the gate electrode 124 and is separated from the data line 171.

The connection line 541 between the ICs extends and extends in the horizontal direction, and both ends 549 extend in width for connection with the IC.

The data line 171, the drain electrode 175, and the connection line 541 between the ICs may be formed of a single layer like the gate line 121, but may be formed of a double layer or more. In the case where there are more than two layers, it is preferable that one layer is formed of a material having a low specific resistance, and the other layer is a material having good contact characteristics with other materials.

The inspection line 125 and the connection line 541 may be formed on the same layer as the data line 171, and the lead line 321 may be formed on the same layer as the gate line 121.

Here, the gate electrode 124, the semiconductor 154, the source electrode 173, and the drain electrode 175 form a thin film transistor TFT.                     

A passivation layer 180 made of silicon nitride or an organic insulating layer is formed on the data line 171, the drain electrode 175, and the semiconductor 154 and the gate insulating layer 140 which are not covered by these. The passivation layer 180 has a plurality of contact holes 182, 183, 186, and 189 exposing a part of the data line 171, a part of the drain electrode 175, and a part of the IC connection line 541.

The passivation layer 180 also has a plurality of contact holes 181 and 187 exposing a part of the gate line 121 and a part of the inspection line 125 together with the gate insulating layer 140. Although not shown in the drawing, the protective film 180 also includes a contact hole that exposes a part of the test pad 126, the lead wire 321, and the driving signal line 323.

On the passivation layer 180, a pixel electrode 190 made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), contact auxiliary members 91, 92, and 82, and a connection member 97 are formed. have.

The pixel electrode 190 is connected to the drain electrode 175 through the contact hole 183 to receive a data signal.

The gate contact auxiliary member 91 and the data contact auxiliary member 92 are connected to the gate line 121 and a part of the data line 171 through contact holes 181 and 182, respectively, which are the gate line 121. And the adhesion between the end of the data line 171 and the external circuit device and protects the gate line 121 and the data line 171. In addition, the connecting line contact auxiliary member 82 is connected to both ends 549 of the inter-IC connecting line 541 through the contact hole 189, and complements the adhesion between the inter-IC connecting line 541 and the IC, and the inter-IC connecting line. (541) serves to protect.

In addition, the contact auxiliary members 91, 92, and 82 extend along the first portions 91a, 92a, 82a and the lines 121, 171, and 541 covering the contact holes 181, 182, and 189. Second portions 91b, 92b, 82b. The second portions 91b, 92b, and 82b are used as pads to which the probe tip contacts during a gross test (G / T). The second portions 91b, 92b and 82b have a space margin for contacting the probe tip during the gross test.

The connecting member 97 is connected to the data line 171 through the contact hole 186 and connected to the test line 125 through the contact hole 187, and transmitted through the test pad 126. Supply the signal to the connected data line.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 included in the PCB 550 is a control input signal for controlling the RGB data signals R, G, and B and their display from an external graphic controller (not shown). signals, for example, a vertical synchronizing signal (V _sync ), a horizontal synchronizing signal (H _sync ), a main clock (CLK), and a data enable signal (DE). Get a back. The signal controller 600 generates a gate control signal and a data control signal based on the control input signal, appropriately processes the gray level signals R, G, and B according to the operating conditions of the liquid crystal panel assembly 300, and then controls the gate. The signal is sent to the gate driver 400 and the driving voltage generator 700, and the data control signal and the processed gray level signals R ′, G ′, and B ′ are sent to the data driver 500.

The gate control signal includes a vertical synchronization start signal (STV) for indicating the start of output of the gate on pulse (high period of the gate signal), and a gate clock signal for controlling the output timing of the gate on pulse. CPV) and a gate on enable signal (OE) for limiting the width of the gate on pulse. The gate on enable signal OE and the gate clock signal CPV are also supplied to the driving voltage generator 700. The data control signal includes a horizontal synchronization start signal (STH) indicating the start of input of the gray scale signal, a load signal (load signal, LOAD or TP) for applying a corresponding data voltage to the data line, and a polarity of the data voltage. An inversion control signal RVS and a data clock signal HCLK to invert.

In this case, the gate control signal supplied to the gate driver 400 is transmitted through the driving signal lines 523 and 323, and the data control signal and the gray level signal are transmitted to the data driver 500 through the lead line 321.

On the other hand, the driving voltage generator 700 according to the control signal from the signal controller 550, the gate on voltage (V _on ), the gate off voltage (V _off ) and the common voltage (V _com ) applied to the reference electrode 270 ) And supply the gate on voltage V _on and the gate off voltage V _off to the gate driver 400 through the driving signal lines 523 and 323. The gray voltage generator 800 generates a plurality of gray voltages related to the luminance of the liquid crystal display and applies them to the data driver 500 through the lead line 321.

The gate driver 400 sequentially applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal from the signal controller 600, thereby applying the gate-on voltage V _on to the gate lines G ₁ -G _n . Turn on the connected switching element (Q). At the same time, the data driver 500 corresponds to the grayscale signals R ', G', and B 'for the pixels including the turned-on switching element Q according to the data control signal from the signal controller 600. The analog gray voltage from the voltage generator 800 is supplied as a data signal to the data lines D ₁ -D _m . The data signal supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q. In this way, the gate-on voltage V _on is sequentially applied to all the gate lines G ₁ -G _n during one frame to apply the data signal to all the pixels. At this time, when the inversion control signal RVS is supplied to the driving voltage generator 700 and the data driver 500 after one frame is finished, the polarity of all data signals of the next frame is changed.

This process is explained in more detail.

The first gate driver IC 440 receiving the vertical synchronization start signal STV selects the gate-on voltage V _on among the two voltages V _on and V _off from the driving voltage generator 700 to select the first gate. Output as line (G ₁ ). At this time, the gate-off voltage V _off is applied to the other gate lines G ₂ -G _n .

Meanwhile, the leftmost data driver IC 540 stores all of its own grayscale signals, receives the grayscale signal for the other data driver IC 540, and passes the grayscale signal to the adjacent data driver IC 540 through the connection line 541. In this manner, each data driver IC 540 stores its gray level signal and transmits the gray level signal for the other data driver IC 540 to the adjacent data driver IC 540 through the connection line 541.

The switching element Q connected to the first gate line G ₁ is turned on by the gate-on voltage V _on , and the liquid crystal of the pixels in the first row through the switching element Q through which the data signal of the first row is conducted. Is applied to capacitor C _lc and holding capacitor C _st . After a certain period of time, when the charging of the capacitors C _lc and C _st of the pixels in the first row is completed, the first gate driving IC 440 applies the gate off voltage V _off to the first gate line G ₁ . The connected switching element Q is turned off and the gate-on voltage V _on is applied to the second gate line G ₂ .

The first gate driving IC 440 that applies the gate-on voltage V _on at least once to all the gate lines connected in this manner transmits a carry signal to the second gate driving IC through the signal line 323 indicating that scanning is completed. Provided at 440.

In the same manner, the second gate driver IC 440 receiving the carry signal scans all the gate lines connected thereto and supplies the carry signal to the next gate driver IC 440 through the signal line 323. In this manner, one frame is completed when the scan operation of the last gate driver IC 440 is completed.

In the liquid crystal display device which performs the display operation through the above process, the gross test is performed by applying the same conditions as the finished product to the liquid crystal display device without the interface circuit or the backlight.

In the gross test, the probe tip of the tester contacts the second portions 91b, 92b, 82b of the contact aid and transmits a signal.

In the present invention, it is possible to secure a sufficient margin of the test pad by expanding the contact assistant member and using the pad as a gross test pad.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (3)

Gate Line, A data line intersecting the gate line, A switching element connected to one of the gate lines and one of the data lines, A pixel electrode connected to the switching element, A driving circuit connecting line spaced apart from the gate line and the data line, the switching element, and the pixel electrode, for connecting between driving circuits supplying a driving signal to the data line; A data line contact auxiliary member for assisting the connection of the driving circuit and the data line; A connecting line contact auxiliary member for assisting the connection of the driving circuit connecting line and the driving circuit. Including, At least one of the data line contact assisting member and the connection line contact assisting member extends by a predetermined length along the data line or the driving circuit connecting line and the first portion covering the exposed portion of the data line or the driving circuit connecting line and is protruded during the gross test. A second portion for use as a pad in contact with the tip, A second portion for assisting the connection between the driving circuit and the gate line, the first portion covering the exposed portion of the gate line and a pad extending along the gate line by a predetermined length and contacting the probe tip during a gross test; A liquid crystal display device comprising a gate line contact auxiliary member having a portion. delete In claim 1, And the gate line contact assistant member, the data line contact assistant member, and the driving circuit connection line contact assistant member are made of ITO or IZO.

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