KR100968157B1 - Power supply circuit and semiconductor memory device using the same - Google Patents

Abstract

PURPOSE: A power supply circuit and a semiconductor memory device using the same are provided to stably perform an over-driving operation even if an external voltage is varied by supplying an internal voltage, higher than a core voltage, as an overdriving voltage. CONSTITUTION: A voltage comparison unit(10) compares an external voltage with a first internal voltage. The voltage comparison unit generates a comparison signal. An internal voltage generating unit(12) generates a second internal voltage. The second internal voltage is higher than the first internal voltage. A voltage selection unit(14) selects one of the external voltage and the second internal voltage. The voltage selection unit outputs the selected voltage as an overdriving voltage. A first switch supplies the overdriving voltage to a first power line of a sense amplifier.

Description

Voltage supply circuit and semiconductor memory device using same {POWER SUPPLY CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME}

The present invention relates to a semiconductor memory device, and more particularly, to a voltage supply circuit and a semiconductor memory device using the same so that the overdriving operation of the sense amplifier can be stably performed even when the level of the external voltage is changed.

With the advancement of technology in computer systems and electronic communication fields, semiconductor memory devices used for storing information are becoming increasingly lower in cost, smaller in size, and larger in capacity, and the demand for energy efficiency is also increasing. In the direction of the development of technology for semiconductor devices is being made.

In general, a cell array that stores data of a DRAM device has a structure in which many cells each consisting of one NMOS transistor and a capacitor are connected to word lines and bit lines connected in a mesh shape.

The operation of a typical DRAM device will be briefly described.

First, the Ras (/ RAS) signal, which is the main signal for operating the DRAM element, changes to an active state (low), receives an address signal input to a row address buffer, and receives the row address signals received at this time. A row decoding operation of decoding and selecting one of the word lines of the cell array is performed.

At this time, if the data of cells connected to the selected word line is loaded on the bit line pair BL, / BL consisting of the bit line and the complementary bit line, the sense amplifier enable signal indicating the operation time of the sense amplifier is enabled. As a result, the sense amplifier driving circuit of the cell block selected by the row address is driven. The sense amplifier bias potential is shifted to the core potential VCORE and the ground potential VSS by the sense amplifier driving circuit, respectively, to drive the sense amplifier. When the sense amplifier starts to operate, the bit line pairs BL and / BL, which have maintained a small potential difference, are shifted to a large potential difference. Then, the column decoder selected by the column address converts the data of the bit line into the data bus line. By turning on the transferred column transfer transistor, the data transferred to the bit line pair BL and / BL is transferred to the data bus lines DB and / DB and output to the outside of the device.

That is, in such an operation, the bit line pairs BL and / BL are precharged to 1/2 VCORE in the standby mode before the semiconductor memory device starts to operate. Is changed to another potential having When the sense amplifier starts to operate in this state, the potentials of the bit line pairs BL and / BL, which have maintained a small potential difference, change to the core potential VCORE and the ground potential VSS, respectively. The amplified bit line data is transferred to the data bus lines DB and / DB by the column decoder output signal yi.

However, when the sense amplifier receives the internal voltage VCORE, which is the core voltage, and starts the operation, a large amount of current is suddenly consumed, which causes the internal voltage VCORE to drop rapidly. Therefore, in order to solve this problem, a method of supplying an external voltage to the core voltage terminal by shorting the external voltage terminal and the core voltage terminal at the time when the sense amplifier starts operation has been widely applied. This is called sense amplifier overdriving.

On the other hand, in recent years, there is a tendency to lower the external power level for low power implementation of the semiconductor memory device, thereby narrowing the difference between the external voltage level and the core voltage level. Therefore, when a level reversal phenomenon occurs in which the external voltage level is changed by internal and external factors and becomes lower than the core voltage level, the driving force of the overdriving section driven by the external voltage is lower than that of the normal driving section driven by the core voltage. Occurs.

Therefore, when the external voltage is lower than the core voltage, the present invention supplies the internal voltage generated at the level higher than the core voltage as the overdriving voltage, thereby stably performing the overdriving operation even when the external voltage level is changed. A voltage supply circuit and a semiconductor memory device using the same are provided.

To this end, the present invention is a voltage comparison unit for generating a comparison signal by comparing the external voltage and the first internal voltage, an internal voltage generation unit for generating a second internal voltage higher than the first internal voltage, the response to the comparison signal A voltage selector configured to select one of the external voltage and the second internal voltage to output the overdriving voltage, and to supply the overdriving voltage to the first power line of the sense amplifier in response to an overdriving control signal. It provides a power supply circuit including a switch.

In the present invention, the first internal voltage is preferably a core voltage.

In the present invention, the comparison signal is preferably enabled when the external voltage level is lower than the first internal voltage level.

In the present invention, it is preferable that the voltage selector transfers the second internal voltage to the overdriving voltage when the comparison signal is enabled.

The voltage comparator includes a comparator configured to generate an output signal by comparing the external voltage level with the first internal voltage level, and a buffer to buffer the output signal of the comparator to generate the comparison signal.

In an embodiment of the present invention, the internal voltage generator may include a control signal generator configured to generate a control signal enabled when the second internal voltage level is lower than a reference voltage level, an oscillator configured to output a periodic signal in response to the control signal; And a voltage pumping part configured to pump the internal voltage in response to the periodic signal.

In the present invention, the reference voltage is preferably set above the first internal voltage level.

In an embodiment, the voltage selector is configured to output the external voltage as the overdriving voltage in response to the comparison signal, and the second internal voltage as the overdriving voltage in response to the comparison signal. And a second switch element for outputting.

In the present invention, it is preferable that the first switch element and the second switch element are selectively turned on in response to the comparison signal.

The present invention also provides a voltage supply circuit for outputting a second internal voltage higher than the first internal voltage when the external voltage level is lower than the first internal voltage level, the second internal voltage in response to an overdriving control signal. Is a first switch outputting an overdriving voltage, a second switch outputting the first internal voltage as a normal operating voltage in response to a normal operation control signal, and the overdriving voltage is received, and performs an overdriving operation. Provided is a semiconductor memory device including a sense amplifier configured to receive an operating voltage and perform a normal operation.

In the present invention, the first internal voltage is preferably a core voltage.

In an embodiment of the present invention, the voltage supply circuit may include a voltage comparator configured to compare the external voltage and the first internal voltage to generate a comparison signal, and generate an internal voltage to generate a second internal voltage having a level higher than the first internal voltage. And a voltage selector configured to selectively supply the external voltage or the second internal voltage as an overdriving voltage of a sense amplifier in response to the comparison signal.

In the present invention, the comparison signal is preferably enabled when the external voltage level is lower than the first internal voltage level.

In the present invention, it is preferable that the voltage selector transfers the second internal voltage to the overdriving voltage when the comparison signal is enabled.

In the present invention, the voltage comparison unit includes a comparison unit for generating an output signal by comparing the external voltage level and the first internal voltage level, and a buffer unit for buffering the output signal of the comparison unit to generate the comparison signal. desirable.

In an embodiment of the present invention, the internal voltage generation unit may include a control signal generation unit generating a control signal enabled when the second internal voltage level is lower than a reference voltage level, an oscillator outputting a periodic signal in response to the control signal; And a voltage pumping part configured to pump the internal voltage in response to the periodic signal.

In the present invention, the reference voltage is preferably set above the first internal voltage level.

In an embodiment, the voltage selector is configured to output the external voltage as the overdriving voltage in response to the comparison signal, and the second internal voltage as the overdriving voltage in response to the comparison signal. And a second switch element for outputting.

In the present invention, it is preferable that the first switch element and the second switch element are selectively turned on in response to the comparison signal.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 1, the semiconductor memory device according to the present embodiment includes a voltage supply circuit 1 and a sense amplifier circuit 2.

The voltage supply circuit 1 includes a voltage comparator 10, an internal voltage generator 12, and a voltage selector 14.

As shown in FIG. 2, the voltage comparator 10 includes a general differential amplifier circuit and compares the external voltage VDD and the core voltage VCORE to drive the node nd1. And a first buffer unit 102 for buffering the signal of the node nd1 to generate the comparison signal / COM. Here, the comparison signal / COM is enabled at a low level when the external voltage VDD level is lower than the core voltage VCORE level.

As illustrated in FIG. 3, the internal voltage generator 12 includes a control signal generator 120, an oscillator 125, and a voltage pumping unit 130.

As shown in FIG. 4, the control signal generator 120 includes a general differential amplifier circuit and compares the internal voltage VIN and the reference voltage VREF to drive the node nd2. ) And an inverter IV3 for inverting the signal of the node nd2 to generate the control signal CS. The control signal CS is output at a high level when the internal voltage VIN level is lower than the reference voltage VREF level. Here, the reference voltage VREF is set higher than the minimum core voltage VCORE level.

The oscillator 125 generates a periodic signal OSC that is toggled in response to the control signal CS. As shown in FIG. 5, the oscillator 125 inverts and buffers the periodic signal OSC in response to the control signal CS. A second buffer unit 126 for outputting, a third buffer unit 127 for inverting and outputting an output signal of the second buffer unit 126 in response to an inverted signal of the control signal CS, and a third buffer And a fourth buffer unit 128 for inverting and buffering the output signal of the unit 127 to output the periodic signal OSC. Here, the NMOS transistor N5 and the PMOS transistor P5 are turned on in the period in which the internal voltage VIN level is lower than the reference voltage VREF level, that is, in the high enable period of the control signal CS, so that the periodic signal is turned on. (OSC) is toggled.

The second buffer unit 126 includes an NMOS transistor N5 turned on in response to the control signal CS, an NMOS transistor N6 and a PMOS transistor selectively turned on in response to the periodic signal OSC. P6).

The third buffer unit 127 is a PMOS transistor P5 turned on in response to an inversion signal of the control signal CS, and an NMOS transistor selectively turned on in response to an output signal of the second buffer unit 126. N7 and a PMOS transistor P7.

The fourth buffer unit 128 is composed of a chain of inverters IV5, IV6, and IV7.

The voltage pumping unit 130 pumps the internal voltage VIN while the periodic signal OSC is toggled, and as shown in FIG. 6, the driver driving the node nd5 in response to the periodic signal OSC. A capacitor C1 coupling the node nd5 and the node nd6, an NMOS transistor N10 and an NMOS transistor N11 that are turned on in response to the periodic signal OSC, and an NMOS. And a capacitor C2 that stores the charge of the node nd6 through the transistor N11.

More specifically, when the node nd5 is pulled up and becomes the external voltage VDD level when the periodic signal OSC is toggled to the low level, the node nd6 is connected to the node nd5 through the capacitor C1. Is coupled to twice the external voltage (VDD) level. After a predetermined period, when the periodic signal OSC is toggled to the high level, the NMOS transistor N10 and the NMOS transistor N11 are turned on so that the capacitor C2 has a charge twice the level of the external voltage VDD. Since it is stored, the internal voltage VIN is pumped by the charge of the capacitor C2. This operation is repeated while the periodic signal OSC is toggled. As such, the internal voltage generator 12 performs pumping until the internal voltage VIN level reaches the reference voltage VREF level.

Meanwhile, the voltage selector 14 converts any one of the external voltage VDD and the internal voltage VIN into the source voltage VS for the overdriving operation of the sense amplifier circuit 2 according to the comparison signal / COM. 7, an NMOS transistor N12 that outputs an external voltage VDD as a source voltage VS in response to a comparison signal / COM of the voltage comparator 10, and a comparison signal. The NMOS transistor N13 outputs the internal voltage VIN as the source voltage VS in response to an inversion signal of (/ COM). Here, the source voltage VS is a voltage transferred to the overdriving voltage of the sense amplifier circuit 2, and when the external voltage VDD level is lower than the core voltage VCORE level, the comparison signal / COM is enabled low. Therefore, the internal voltage VIN having a level higher than the core voltage VCORE is transmitted to the sense amplifier circuit 2 as the source voltage VS.

On the other hand, the sense amplifier circuit 2 is composed of a drive control unit 21 and a sensing unit 22, as shown in FIG.

The driving controller 21 is an NMOS transistor N20 that operates as a first switch for connecting the external voltage terminal and the RTO line RTO of the sensing unit 22 in response to the overdriving control signal OVD, and normal operation control. The NMOS transistor N21 acting as a second switch for connecting the core voltage terminal and the RTO line RTO of the sensing unit 22 in response to the signal NV, and the ground voltage in response to the ground voltage control signal SAEN. And an NMOS transistor N22 connecting the stage and the SB line SB of the sensing unit 22 to each other. In addition, when the sense amplifier enable signal SAEB is disabled, the driving controller 21 converts the RTO line RTO and the SB line SB into the precharge voltage VBLP in response to the bit line equalizer signal BLEQ. NMOS transistors N23, N24 and N25 for precharging are provided. The bit line equalizer signal BLEQ maintains the same level of the RTO line RTO and the SB line SB while the sense amplifier enable signal SAEB is disabled to prevent the sensing unit 22 from being driven. It is a signal for.

The sensing unit 22 is composed of a general cross coupled latch circuit, and the sensing operation is not performed while the RTO line RTO and the SB line SB are precharged, but the SB line SB is not performed. The ground voltage VSS is supplied through the circuit, and the source voltage VS or the core voltage VCORE is supplied through the RTO line RTO to generate a potential difference between both ends, thereby sensing the pair of bit lines BL and / BL. do.

The operation of the semiconductor memory device according to the present exemplary embodiment configured as described above is divided into a case where the external voltage VDD level is greater than the core voltage VCORE level and a case where the external voltage VDD level is lower than the core voltage VVCORE level. The description is as follows.

First, when the external voltage VDD level is higher than the core voltage VCORE level, the node nd1 of the voltage comparator 10 becomes a high level, and the comparison signal / COM is generated at a high level. Accordingly, as the NMOS transistor N12 of the voltage selector 14 is turned on in response to the high level comparison signal / COM, the external voltage VDD is output as the source voltage VS. Subsequently, when the overdriving control signal OVD is enabled at a high level and the overdriving operation of the sense amplifier circuit 2 is started, the NMOS transistor N20 of the drive control unit 21 generates a high-level overdriving control signal ( Since it is turned on in response to OVD, the RTO line RTO is driven to the external voltage VDD level. That is, the sense amplifier circuit 2 performs an overdriving operation at the external voltage VDD level.

Next, when the external voltage VDD level is lower than the core voltage VCORE level, the node nd1 of the voltage comparator 10 is driven at the low level, and the comparison signal / COM is enabled at the low level. At this time, the internal voltage generator 12 transmits the internal voltage VIN pumped to the reference voltage VREF level to the voltage selector 14, and the NMOS transistor N13 of the voltage selector 14 is a comparison signal. As turned on in response to an inversion signal of (/ COM), the internal voltage VIN is output as the source voltage VS. Subsequently, when the overdriving control signal OVD is enabled at a high level and the overdriving operation of the sense amplifier circuit 2 is started, the NMOS transistor N20 of the drive control unit 21 generates a high-level overdriving control signal ( Since it is turned on in response to OVD, the RTO line RTO is driven to the internal voltage VIN level. That is, the sense amplifier circuit 2 performs an overdriving operation at the internal voltage VIN level. Here, since the internal voltage VIN is pumped above the core voltage VCORE level, the sense amplifier circuit 2 performs overdriving to a level higher than the core voltage VCORE.

In summary, when the external voltage VDD level is higher than the core voltage VCORE level, the power supply circuit 1 according to the present embodiment has the external voltage as the overdriving voltage of the sense amplifier circuit 2 as before. While supplying (VDD), when the external voltage (VDD) level is lower than the core voltage (VCORE) level, the internal voltage (VIN) generated higher than the core voltage (VCORE) level by the overdriving voltage of the sense amplifier circuit (2) ), The overdriving operation can be stably performed regardless of the variation of the external voltage (VDD) level.

1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating the voltage comparison unit of FIG. 1.

FIG. 3 is a block diagram showing the configuration of the internal voltage generator of FIG.

4 is a circuit diagram illustrating a control signal generator of FIG. 3.

FIG. 5 is a circuit diagram illustrating the oscillator of FIG. 3.

FIG. 6 is a circuit diagram illustrating the voltage pumping unit of FIG. 3.

FIG. 7 is a circuit diagram illustrating the voltage selector of FIG. 1.

FIG. 8 is a circuit diagram illustrating the sense amplifier circuit of FIG. 1.

<Description of the symbols for the main parts of the drawings>

1: voltage supply circuit 2: sense amplifier circuit

10: voltage comparator 12: internal voltage generator

14: voltage selector 120: control signal generator

125: oscillator 130: voltage pumping unit

VDD: External Voltage VCORE: Core Voltage

VIN: Internal voltage

Claims (19)

A voltage comparison unit comparing the external voltage with the first internal voltage to generate a comparison signal; An internal voltage generator configured to generate a second internal voltage having a level higher than the first internal voltage; A voltage selector which selects one of the external voltage and the second internal voltage and outputs the overdriving voltage in response to the comparison signal; And And a first switch for supplying the overdriving voltage to a first power line of a sense amplifier in response to an overdriving control signal. The voltage supply circuit as claimed in claim 1, wherein the first internal voltage is a core voltage. The voltage supply circuit of claim 1, wherein the comparison signal is enabled when the external voltage level is lower than the first internal voltage level. The voltage supply circuit of claim 3, wherein the voltage selector transfers the second internal voltage to the overdriving voltage when the comparison signal is enabled. The method of claim 1, wherein the voltage comparison unit A comparator configured to generate an output signal by comparing the external voltage level with the first internal voltage level; And And a buffer unit configured to generate the comparison signal by buffering the output signal of the comparison unit. The method of claim 1, wherein the internal voltage generation unit A control signal generator configured to generate a control signal enabled when the second internal voltage level is lower than a reference voltage level; An oscillator outputting a periodic signal in response to the control signal; And And a voltage pumping unit configured to pump the internal voltage in response to the periodic signal. 7. The voltage supply circuit as claimed in claim 6, wherein the reference voltage is set above the first internal voltage level. The method of claim 1, wherein the voltage selector A first switch element outputting the external voltage as the overdriving voltage in response to the comparison signal; And And a second switch element outputting the second internal voltage as the overdriving voltage in response to the comparison signal. 9. The voltage supply circuit as claimed in claim 8, wherein the first switch element and the second switch element are selectively turned on in response to the comparison signal. A voltage supply circuit configured to output a second internal voltage higher than the first internal voltage when the external voltage level is lower than the first internal voltage level; A first switch configured to output the second internal voltage as an overdriving voltage in response to an overdriving control signal; A second switch outputting the first internal voltage to a normal operation voltage in response to a normal operation control signal; And And a sense amplifier configured to receive the overdriving voltage to perform an overdriving operation and to receive the normal operating voltage to perform a normal operation. The semiconductor memory device of claim 10, wherein the first internal voltage is a core voltage. The circuit of claim 10, wherein the voltage supply circuit is A voltage comparator configured to generate a comparison signal by comparing the external voltage and the first internal voltage; An internal voltage generator configured to generate a second internal voltage having a level higher than the first internal voltage; And And a voltage selector configured to selectively supply the external voltage or the second internal voltage as an overdriving voltage of a sense amplifier in response to the comparison signal. The semiconductor memory device of claim 12, wherein the comparison signal is enabled when the external voltage level is lower than the first internal voltage level. The semiconductor memory device of claim 13, wherein the voltage selector transfers the second internal voltage to the overdriving voltage when the comparison signal is enabled. The method of claim 12, wherein the voltage comparison unit A comparator configured to generate an output signal by comparing the external voltage level with the first internal voltage level; And And a buffer unit configured to generate the comparison signal by buffering an output signal of the comparison unit. The method of claim 12, wherein the internal voltage generation unit A control signal generator configured to generate a control signal enabled when the second internal voltage level is lower than a reference voltage level; An oscillator outputting a periodic signal in response to the control signal; And And a voltage pumping part configured to pump the internal voltage in response to the periodic signal. The semiconductor memory device of claim 16, wherein the reference voltage is set to be equal to or greater than the first internal voltage level. The method of claim 12, wherein the voltage selector A first switch element outputting the external voltage as the overdriving voltage in response to the comparison signal; And And a second switch element configured to output the second internal voltage as the overdriving voltage in response to the comparison signal. The semiconductor memory device of claim 18, wherein the first switch element and the second switch element are selectively turned on in response to the comparison signal.

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