KR100948479B1 - Driver which includes skew control circuit and method for settting control signal of the same - Google Patents

Abstract

The present invention relates to a driver having a skew control circuit. The present invention has been created to suppress the occurrence of short circuit current which is a problem of the conventional driver.

The driver according to the present invention is a driver having a first preceding driver, a second preceding driver and an output driver, wherein the first and second preceding drivers are each further provided with a skew control circuit operating in resistance or short circuit according to a control signal. It is characterized by.

The present invention also provides a method for setting a control signal of a skew control circuit of the driver.

According to the present invention, not only can the time and cost be reduced as compared with the method of adjusting the skew by the metal selection process, but the control signal of the skew control circuit can be set in a simple manner.

Driver, skew control circuit, CMOS transistor.

Description

A driver having a skew control circuit and a method for setting the control signal thereof {DRIVER WHICH INCLUDES SKEW CONTROL CIRCUIT AND METHOD FOR SETTTING CONTROL SIGNAL OF THE SAME}             

1 is a circuit diagram of a driver according to the prior art.

2 is a view for explaining the principle that the short-circuit current is generated in the driver according to the prior art.

3 is a view for explaining a method for removing a short circuit current according to the prior art.

4 is a circuit diagram of a driver according to a first embodiment of the present invention.

5 is a view for explaining the operation of the driver according to the first embodiment of the present invention.

6 is a circuit diagram of the skew control circuit according to the first embodiment of the present invention.

7 to 13 are flowcharts showing a method for setting a control signal of a driver according to the first embodiment of the present invention.

The present invention relates to a driver. In particular, the present invention relates to a driver having a skew control circuit.

Hereinafter, a driver according to the prior art will be described with reference to FIGS. 1 and 2.

1 is a circuit diagram of a driver according to the prior art. In FIG. 1, the driver is composed of a first pre-driver 1100, a second pre-driver 1200, and an output driver 1300. The first and second preceding drivers 1100, 1200 and the output driver 1300 each comprise a complementary metal oxide semiconductor (CMOS) inverter including PMOS transistors 1110, 1210, 1310 and NMOS transistors 1120, 1220, 1320. inverter). The first and second inputs IN1 and IN2 are driven by the preceding drivers 1100 and 1200 to become the first and second outputs OUT1 and OUT2, which in turn are driven by the output driver 1300 to drive outputs. Becomes (OUT). As such, the first and second inputs IN1 and IN2 pass through a two-stage driver composed of the preceding drivers 1100 and 1200 and the output driver 1300, thereby having a stronger driving capability.

2 is a view for explaining the principle that a short circuit current (short circuit current) occurs in the driver according to the prior art. In FIG. 2, a first input voltage V _IN1 , a second input voltage V _IN2 , a first output voltage V _OUT1 , a second output voltage V _OUT2 , and a driving output voltage V _OUT are represented. have.

When the first and second output voltages V _OUT1 and V _OUT2 are low, the PMOS transistor 1310 of the output driver 1300 is on, and the NMOS transistor 1320 is off. ) And the first and second output voltages V _OUT1 and V _OUT2 are high, the PMOS transistor 1310 of the output driver 1300 is turned off, and the NMOS transistor 1320 is turned on. It becomes a state. In either case, since one of the PMOS transistor 1310 and the NMOS transistor 1320 is in an off state, no current flows from the voltage power supply terminal Vs to the ground power supply terminal.

In the period 2100 in which the first and second output voltages V _OUT1 and V _OUT2 change from low to high and in the period 2200 from high to low, the PMOS transistor 1310 and the NMOS transistor (of the output driver 1300) In 1320, there is a time for current to flow, and in this period, a relatively large amount of current flows from the voltage power supply terminal Vs to the ground power supply terminal. Also, If the first output voltage skew (skew) is delayed as shown in the dotted line 2300 in (V _OUT1) has occurred, the first output voltage (V _OUT1) is low and the second output voltages (V _OUT2) is deceased In the period 2400, both the PMOS transistor 1310 and the NMOS transistor 1320 of the output driver 1300 are turned on so that a huge current flows from the voltage power supply terminal Vs to the ground power supply terminal. In the same way, the second output voltage, even if a skew is delayed as shown in the dotted line (2500) to (V _OUT2) has occurred, the first output voltage (V _OUT1) is low and the second output voltages (V _OUT2) is deceased period In 2600, a huge current flows from the voltage power supply terminal Vs to the ground power supply terminal. The skew may be caused by a time difference between the first and second inputs IN1 and IN2 or asymmetry of the first and second preceding drivers 1100 and 1200.

As described above, when both the PMOS transistor 1310 and the NMOS transistor 1320 of the output driver 1300 are turned on, a large power loss occurs due to a large current flowing from the voltage power supply terminal Vs to the ground power supply terminal. There is this. In particular, when skew occurs between the first and second outputs OUT1 and OUT2, the problem is more serious.

There is a metal option method in the prior art to solve the above problems. Hereinafter, a metal selection method will be described with reference to FIG. 3.

In FIG. 3, the driver is manufactured by the same method as the driver represented in FIG. The skew characteristics are then measured using measuring equipment. If the first output OUT1 is delayed compared to the second output OUT2, an additional metal process is performed to disconnect the f terminal and the d terminal of the second preceding driver 3200, and the f terminal and the e terminal. By forming a connection therebetween, a resistor 3230 is formed between the drain of the second PMOS transistor 3210 and the second output terminal OUT2. As a result, the rise of the second output voltage V _OUT2 is delayed, and as a result, generation of a short circuit current due to skew is suppressed. In the same way, if the second output OUT2 is delayed compared to the first output OUT1, the connection between the c terminal and the a terminal of the first preceding driver 3100 is disconnected and the c terminal and the b terminal are disconnected. By forming a connection to the circuit, generation of a short circuit current due to skew is suppressed.

However, this conventional method of metal selection for skew removal requires a measuring step to determine whether skew has occurred, and after the measuring step, an additional metal process is required. The measurement step is performed on a wafer basis, and there is a problem in that it is expensive to use the measurement equipment. Further metal processes include an oxide film forming process, a lithography process, and an etching process. There is a problem.

The present invention has been made to solve the above-described problem, the technical problem to be achieved by the present invention is to provide a method for controlling the skew to prevent the generation of short-circuit current.

In addition, an object of the present invention is to provide a way to control the skew without additional metal processing, without using a metal selection method that is time-consuming and expensive.

As a technical means for achieving the above technical problem, the first aspect of the present invention is a first preceding driver for receiving a first input and outputting a first output, the second receiving a second input and outputting a second output A preceding driver, an output driver for receiving the first and second outputs and outputting a drive output, wherein the first and second preceding drivers each comprise a skew control circuit operating in resistance or short circuit in accordance with a control signal; Provide a driver.

A second aspect of the invention provides a first preceding driver having a first skew control circuit controlled by a first control signal, a second preceding driver having a second skew control circuit controlled by a second control signal and an output. A method of setting a control signal of a driver having a driver, wherein the first control signal is set such that the first skew control circuit operates in a short circuit when the output of the first preceding driver is delayed compared to the output of the second preceding driver. And set the second control signal to cause the second skew control circuit to operate as a resistor, and if the output of the second preceding driver is delayed relative to the output of the first preceding driver, the first skew control circuit to operate as a resistor. Set the control signal and set the second control signal so that the second skew control circuit operates in a short circuit, and the outputs of the first and second preceding drivers move. In the case of vaporization, a control signal setting method of a driver including a skew control circuit having a step of setting the first and second control signals such that the first and second skew control circuits operate in a short circuit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention may be modified in various forms, and the scope of the present invention should not be interpreted as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art.

Hereinafter, the structure and function of the driver according to the first embodiment of the present invention will be described with reference to FIG. 4.

In FIG. 4, the output driver includes a first pre-driver 4100, a second pre-driver 4200, and an output driver 4300.

The first preceding driver 4100 includes a first PMOS transistor 4110, a first NMOS transistor 4120, and a first skew control circuit 4130. A gate, a source, and a drain of the first PMOS transistor 4110 are connected to the first input terminal IN1, the voltage power supply terminal Vs, and the first output terminal OUT1, respectively. The gate, source, and drain of the first NMOS transistor 4120 are connected to a first input terminal IN1, a ground power supply terminal, and one terminal of the first skew control circuit 4130, respectively. The first skew control circuit 4130 is connected to the drain of the first control signal terminal CTRL1, the first output terminal OUT1, and the first NMOS transistor 4120.

The second preceding driver 4200 includes a second PMOS transistor 4210, a second NMOS transistor 4220, and a second skew control circuit 4230. The gate, source, and drain of the second PMOS transistor 4210 are connected to one terminal of the second input terminal IN2, the voltage power supply terminal Vs, and the second skew control circuit 4230, respectively. The gate, source, and drain of the second NMOS transistor 4220 are connected to the second input terminal IN2, the ground power supply terminal, and the second output terminal OUT2, respectively. The second skew control circuit 4230 is connected to the second control signal terminal CTRL2, the drain of the second PMOS transistor 4210, and the second output terminal OUT2.

The output driver 4300 includes a third PMOS transistor 4310 and a third NMOS transistor 4320. The gate, source, and drain of the third PMOS transistor 4310 are connected to the first output terminal OUT1, the voltage power supply terminal Vs, and the driving output terminal OUT, respectively. The gate, source, and drain of the second NMOS transistor 4320 are connected to the second output terminal OUT2, the ground power supply terminal, and the driving output terminal OUT, respectively.

The skew control circuits 4130 and 4230 may control the skew of the first and second outputs OUT1 and OUT2 so as to control the skew of the first and second outputs OUT1 and OUT2, the first NMOS transistor 4120 and the second PMOS transistor 4210 according to the control signals CTR1 and CTRL2. A short circuit or a resistance is formed between the drain of the C1) and the first and second output terminals OUT1 and OUT2. If the control signals CTRL1 and CTRL2 are provided such that a short circuit is formed between the drain and the output terminals OUT1 and OUT2, the same function as the conventional driver shown in FIG. 1 performs a function of driving without skew control. . If the control signal CTRL1 is provided such that the first skew control circuit 4130 has a resistance, a delay occurs in the falling of the first output voltage V _OUT1 , and if the second skew control circuit 4230 is When the control signal CTRL2 is provided to have a resistance, a delay occurs in the rise of the second output voltage V _OUT2 .

The first skew control circuit 4130 is positioned between the source of the first NMOS transistor 4120 and the ground power supply terminal, and the second skew control circuit 4230 is positioned between the second PMOS transistor 4210 and the voltage power supply terminal Vs. It can be easily seen that the driver positioned between the) will operate as described above.

Hereinafter, the operation of the driver according to the first embodiment of the present invention will be described with reference to FIGS. 4 and 5.

FIG. 5 illustrates a case where a skew in which the first input IN1 is delayed compared to the second input IN2 occurs. In this case, the first output voltage V _OUT1 is low and the third PMOS transistor 4310 is turned on. At the same time, the second output voltage V _OUT2 is turned high and the third NMOS transistor 4320 is turned on. A period 5100 is generated. In this period, a huge short circuit current flows from the voltage power supply terminal Vs to the ground power supply terminal. To prevent this, the second control signal CTRL2 is selected to cause the first skew control circuit 4230 to operate as a resistor, thereby increasing the RC time constant. As a result, the rising time of the second output voltage V _OUT2 is delayed as in the dotted line 5200, thereby preventing the third PMOS transistor 4310 and the third NMOS transistor 4320 from being turned on at the same time.

Since the operation in the case where a skew in which the second input IN2 is delayed compared to the first input IN1 occurs can be easily understood from the above description, it is omitted for convenience of description.

Hereinafter, a skew control circuit according to a first embodiment of the present invention will be described with reference to FIG. 6. The skew control circuit includes a resistor 6100 and a switch 6200. The switch 6200 performs a function of connecting one terminal of the resistor 6100, one of the first terminals T1, and the second terminal T2 according to the control signal CTRL. The switch 6200 includes, for example, a first pass transistor 6210, a second pass transistor 6220, and an inverter 6230. The inverter 6230 reverses the control signal CTRL. The PMOS gate of the first pass transistor 6210 is connected to the control signal CTRL, the NMOS gate to the output of the inverter 6230, and the other two terminals are connected to the first terminal T1 and the second terminal T2. The PMOS gate of the second pass transistor 6220 is connected to the output of the inverter 6230, the NMOS gate is connected to the control signal CTRL, and the other two terminals are connected to the resistor 6100 and the second terminal T2. When the switch 6200 is configured in this manner, when the CTRL is low, a short circuit is formed between the first terminal T1 and the second terminal T2, and when the switch 6200 is high, a resistance is formed. That is, the skew control circuit operates as a short circuit when CTRL is low and as a resistor when high.

Hereinafter, a method of selecting control signals CTRL1 and CTRL2 of a skew control circuit of a driver according to an embodiment of the present invention will be described with reference to FIGS. 4 and 7 to 13.

7 is a method for setting the control signals CTRL1 and CTRL2 of a single step skew control circuit. In this step, when the first output OUT1 is delayed compared to the second output OUT2, the second skew control causes the first control signal CTRL1 to operate in a short circuit. When the second control signal CTRL2 is set to cause the circuit 4230 to operate as a resistor, and the second output OUT2 is delayed relative to the first output OUT1, the first skew control circuit 4130 is a resistor. The second control signal CTRL2 is set to operate the first control signal CTRL1 so that the second skew control circuit 4230 operates in a short circuit, and the first and second skews are not used in any of the above cases. The first and second control signals CTRL1 and CTRL2 are set to cause the control circuits 4130 and 4230 to operate in a short circuit.

The above step may have a substep as shown in FIGS. 8 to 13. FIG. 8 illustrates a first substep of setting the first and second control signals CTRL1 and CTRL2 such that the first and second skew control circuits 4130 and 4230 operate in a short circuit. If the short circuit current does not occur, the setting is terminated. If the short circuit current occurs, the second substep, the first skew control circuit 4130, which proceeds to the next substep, operates in a short circuit. The third sub-step of setting the second control signal CTRL2 to cause the first control signal CTRL1 to operate the second skew control circuit 4230 as a resistor, and whether or not a short circuit current occurs in the output driver 4300. If the short-circuit current does not occur by judging, the setting is terminated, and if the short-circuit current occurs, the fourth sub-step, which proceeds to the next sub-step, and the first control such that the first skew control circuit 4130 operates as a resistor. Second skew control of signal CTRL1 And in (4230) it is provided with a fifth sub-step that the short-circuit operation hagekkeum set the second control signal (CTRL2). With this substep, the advantage of being able to simply set the control signals CTRL1 and CTRL2 without measuring the first output OUT1 and the second output OUT2 separately with a measuring instrument is advantageous. have.

Since the sub-steps shown in FIGS. 9 to 13 only change the settings of the first to second control signals CTRL1 and CTRL2 in FIG. 8, it can be easily understood from the above description, and thus will be omitted for convenience of description.

According to a modification of the present invention, it is possible to apply the idea of the present invention to a driver implemented as an NMOS transistor and a driver implemented as a bipolar junction transistor (BJT).

In order to control the skew, the driver according to the present invention does not use a metal selection method that requires a measuring step and an additional metal process, and uses a skew control circuit, thereby saving a lot of time and money spent in the measuring step and the additional metal process. There is an effect that can be saved.

In addition, according to the method of setting the skew control circuit according to the present invention, not only the skew control signal of the driver can be set, but also the skew control signal can be easily set without measuring the first and second output signals with a measuring instrument. There is an effect.

Claims (13)

A first preceding driver to receive a first input and output a first output; A second preceding driver to receive a second input and output a second output; An output driver configured to receive the first and second outputs and output a driving output; And said first and second preceding drivers each comprise a skew control circuit operating in resistance or short circuit in accordance with a control signal. The method of claim 1, The skew control circuit comprises a switch and a resistor, The switch connects one of the terminals connected to the outside and one terminal of the resistor in accordance with the control signal to the other terminal connected to the outside, And the resistor is connected to one terminal connected to the outside and to one terminal of the switch. The method of claim 1, Wherein the first preceding driver, the second preceding driver and the output driver are implemented using CMOS transistors. The method of claim 3, wherein The first preceding driver, A first PMOS transistor having a gate, a source, and a drain connected to a first input terminal, a voltage power supply terminal, and a first output terminal, respectively; A first NMOS transistor having a gate, a source, and a drain connected to one terminal of a first input terminal, a ground power supply terminal, and a first skew control circuit, respectively; And And a first skew control circuit operated by a first control signal and connected to the first output terminal and the drain of the first NMOS transistor. The method of claim 3, wherein The first preceding driver, A first PMOS transistor having a gate, a source, and a drain connected to a first input terminal, a voltage power supply terminal, and a first output terminal, respectively; A first NMOS transistor having a gate, a source, and a drain connected to a first input terminal, one terminal of the first skew control circuit, and a first output terminal, respectively; And And a first skew control circuit operated by the first control signal and connected to the source and ground power supply terminals of the first NMOS transistor. The method of claim 3, wherein The second preceding driver, A second PMOS transistor having a gate, a source, and a drain connected to one terminal of a second input terminal, a voltage power supply terminal, and a second skew control circuit, respectively; A second NMOS transistor having a gate, a source, and a drain connected to a second input terminal, a ground power supply terminal, and a second output terminal, respectively; And And a second skew control circuit operated by a second control signal and connected to the second output terminal and the drain of the second PMOS transistor. The method of claim 3, wherein The second preceding driver, A second PMOS transistor having a gate, a source, and a drain connected to a second input terminal, one terminal of the second skew control circuit, and a second output terminal, respectively; A second NMOS transistor having a gate, a source, and a drain connected to a second input terminal, a ground power supply terminal, and a second output terminal, respectively; And And a second skew control circuit operated by a second control signal and connected to a source and a voltage power supply terminal of the second PMOS transistor. The method of claim 3, wherein The output driver, A third PMOS transistor having a gate, a source, and a drain connected to the first output terminal, the voltage power supply terminal, and the driving output terminal, respectively; And And a third NMOS transistor having a gate, a source, and a drain connected to a second output terminal, a ground power supply terminal, and a driving output terminal, respectively. The method of claim 3, wherein The skew control circuit, An inverter for reversing a control signal; A first pass transistor connected to the PMOS gate at the control signal, the NMOS gate at the output of the inverter, and the other two terminals connected to two terminals connected to the outside; A second pass transistor connected to a PMOS gate at an output of the inverter, an NMOS gate to a control signal, and the other two terminals to one terminal of a resistor and one terminal connected to the outside; And And a resistor connected to one terminal of the second pass transistor and the other terminal connected to the outside. delete The method of claim 1, Wherein the first preceding driver, the second preceding driver and the output driver are implemented using BJT. Control of a first preceding driver having a first skew control circuit controlled by a first control signal, a second preceding driver having a second skew control circuit controlled by a second control signal and a driver having an output driver In the method for setting the signal, If the output of the first preceding driver is delayed relative to the output of the second preceding driver, the first control signal is set so that the first skew control circuit operates in a short circuit and the second control signal causes the second skew control circuit to operate as a resistor. Set the first control signal so that the first skew control circuit operates as a resistor and the second skew control circuit operates in a short circuit when the output of the second preceding driver is delayed compared to the output of the first preceding driver. Setting a second control signal, and setting the first and second control signals such that the first and second skew control circuits operate in a short circuit when the outputs of the first and second preceding drivers are synchronized. Control signal setting method of a driver including a skew control circuit The method of claim 12, Setting the first and second control signals A first step of setting the first and second control signals to cause the first and second skew control circuits to operate in a short circuit; A second step of judging whether or not a short circuit current occurs in the output driver, terminating the setting if a short circuit current does not occur, and proceeding to the next step if a short circuit current occurs; A third step of setting a first control signal to cause the first skew control circuit to operate in a short circuit and a second control signal to cause the second skew control circuit to operate as a resistor; A fourth step of judging whether or not a short circuit current occurs in the output driver, terminating the setting if a short circuit current does not occur, and proceeding to the next step if a short circuit current occurs; And A fifth step of setting a first control signal to cause the first skew control circuit to operate as a resistor and a second control signal to cause the second skew control circuit to operate in a short circuit; The first, the third and the fifth step may be different in the order of the control signal setting method of the driver comprising a skew control circuit.

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