KR100947532B1 - Flat panel display device - Google Patents

Abstract

Disclosed is a flat panel display device capable of improving display quality. The pixel array is formed on the display region of the substrate, the data integrated circuit portion is mounted in the non-display region of the substrate, and generates a signal on the data line extended in the first direction to operate the pixel array, and the gate integrated circuit portion is formed. The gate signal line transfers a signal including on and off to a gate line extending in a direction different from one direction. The plurality of gate pads are formed in the non-display area of the substrate and are integrally provided to correspond to two or more adjacent gate signal lines and connected to the ends of the gate signal lines so that the same kind of signal is transmitted.

Description

Flat panel display device

FIG. 1 is a diagram illustrating a thin film transistor that is employed in a gate pad to explain a problem in a conventional liquid crystal display.

2 is a diagram illustrating a structure of a gate input pad part of a gate driving integrated circuit employed in a general liquid crystal display device.

FIG. 3 is an enlarged schematic view of portion A of FIG. 2.

4 is a schematic view of a liquid crystal panel of the liquid crystal display according to the present invention.

5 is a plan view schematically illustrating the connection of an integrated circuit capable of driving a liquid crystal panel employed in the present invention.

6 is a schematic diagram showing the structure of a gate pad portion of a gate driving integrated circuit employed in the first embodiment of the present invention.

Fig. 7 is a schematic diagram showing the structure of a gate pad portion of a gate driving integrated circuit employed in the second embodiment of the present invention.

8 is a schematic diagram showing the structure of a gate pad portion of a gate driving integrated circuit employed in the third embodiment of the present invention.

9 is a schematic diagram showing the structure of a gate pad portion of a gate driving integrated circuit employed in the fourth embodiment of the present invention.                 

<Explanation of symbols for main parts of drawing>

100: first substrate 102: second substrate

106: data line 114: liquid crystal

130: liquid crystal panel 133: first pad

134: second pad 137: first integrated circuit

138: second integrated circuit 200: gate signal lines

400: gate pads 450: insulating film

The present invention relates to a flat panel display, and more particularly, to a flat panel display for improving display quality.

The liquid crystal display uses a transmissive liquid crystal display for displaying an image using a light source such as a backlight, a reflective liquid crystal display using natural light, and a built-in light source of the display device itself in a dark place where an indoor or external light source does not exist. The display device may be classified into a reflection-transmissive liquid crystal display device which operates in a transmissive display mode for displaying and operates in a reflective display mode for reflecting and displaying external incident light in an outdoor high illumination environment.

The liquid crystal display device includes a liquid crystal panel for displaying an image and a driving integrated circuit for generating an image signal.                         

The liquid crystal panel is composed of a thin film transistor (TFT) substrate (hereinafter referred to as a TFT substrate), a color filter substrate, and a liquid crystal injected between the TFT substrate and the color filter substrate.

A plurality of gate lines and a plurality of data lines are formed in a matrix form on the TFT substrate, and pixel electrodes and TFTs are formed at intersections thereof. The color filter substrate is provided with a color filter and a transparent common electrode layer including an RGB pixel in which a predetermined color is expressed while light passes. In addition, a polarizing plate is provided on the outer surface of the TFT substrate and the color filter substrate in accordance with the alignment direction of the liquid crystal to make the transmission direction of external light constant.

The TFT includes a gate electrode formed on the TFT substrate, a gate insulating film formed on the gate electrode and the substrate, an active pattern and an ohmic contact layer pattern formed on the gate insulating film on the gate electrode, and a source / drain electrode formed on the active pattern. It consists of. A protective film made of an inorganic material or an organic material is formed on the TFT substrate on which the TFT is formed. A contact hole is formed through the passivation layer to expose the drain electrode. In addition, contact holes exposing the gate terminal and the drain terminal of the pad region are also formed through the passivation layer.

The gate electrode is connected to a gate line, the source electrode is connected to a data line, and the drain electrode is connected to a pixel electrode. Therefore, when a scan voltage is applied to the gate electrode through the gate line, a signal voltage flowing through the data line is applied through the active pattern from the source electrode to the drain electrode. The signal voltage is applied to the drain electrode through the active pattern. When a signal voltage is applied to the drain electrode, a voltage difference is generated between the pixel electrode connected to the drain electrode and the common electrode of the color filter substrate. Then, the molecular arrangement of the liquid crystal injected between the pixel electrode and the common electrode is changed, thereby changing the light transmittance of the liquid crystal so that the thin film transistor serves as a switching element for operating the pixel of the liquid crystal panel.

In addition, the liquid crystal panel includes a gate pad extending from a gate line and a data pad extending from a data line. The gate pad is connected to a gate integrated circuit generating a scan voltage, and the data pad is connected to a data integrated circuit generating a signal voltage. Accordingly, the scan voltage generated in the gate integrated circuit is applied to the gate line through the gate pad, and the signal voltage generated in the data integrated circuit is applied to the data line through the data pad. In this case, there are various methods of connecting the gate pad or data pad to a gate integrated circuit or a data integrated circuit. First, a bump is formed in an integrated circuit to connect the pad to an electrode of the integrated circuit. The bumps are used to connect the pads and the integrated circuit.

A commonly used method for connecting the pad and the integrated circuit is TAB (tape automated bonding). According to the TAB method, the metal-bonded film and the electrodes of the integrated circuit are connected by bumps, and then the leads of the TAB package bonded to the electrodes are bonded to the liquid crystal panel. That is, the TAB method is a method of installing an integrated circuit outside the liquid crystal panel and electrically shorting an electrode of the integrated circuit and an electrode of the liquid crystal panel with a film to which a metal wire is bonded.                         

In addition to the TAB method, a chip on glass (COG) method may be used to attach the driving integrated circuit to the liquid crystal panel. In the COG method, an integrated circuit is directly mounted on a substrate of a liquid crystal panel. Instead of using a film used in the TAB method, only a bump and an anisotropic conductive film (hereinafter referred to as "ACF") are used for the substrate of the liquid crystal panel. It is a method of adhering the integrated circuit to the.

1 is a diagram illustrating a thin film transistor employed in a conventional gate pad.

Referring to FIG. 1, the contact between the gate metal 20 and the ITO conductive layer 23 is a pad for mounting an integrated circuit in a COG method or a pad for attaching a flexible printed circuit (FPC) in a transflective liquid crystal display. It is used a lot.

As the gate metal 20, a double film 20 of Cr film 16 and AlNd 15 is used. During the process of contacting the gate metal 20 with the ITO conductive film 23, the insulating film 25 is patterned in consideration of galvanic corrosion of the AlNd film 15 and the ITO film 23, and then AlNd The entire etch process is performed to form pads by contact between Cr and ITO.

When the AlNd entire surface is etched after the insulating film 25 is patterned, an AlNd undercut occurs in the open portion 30 of the insulating film 25, and thus the insulating film 25 is slightly collapsed.

FIG. 2 is a diagram illustrating a structure of a gate input pad part of a gate driving integrated circuit employed in a general liquid crystal display, and FIG. 3 is a schematic diagram illustrating an enlarged portion A of FIG. 2.

2 and 3, the gate pad part 50 includes a gate signal line 52 and a gate pad 54. The gate signal line 52 is composed of a Vcom gate signal line 52a, a Voff gate signal line 52b, and a gate signal line 52c for applying other signals, and the gate pad 54 is a Vcom gate pad for receiving a gate Vcom signal. 54a, the Voff gate pad 54b receives the Voff signal, and the gate pad 54c receives the remaining signal.

3, the open portion 30 of the insulating layer 25 should be larger than the connection portion 35 of the pad. However, even in this case, a fan out for distributing the output of the gate electrode is provided. out) the undercut in the part 35 is unavoidable.

In addition, an ITO etchant penetrates between the ITO 108 and the insulating film 25, thereby causing the wirings to electrochemically react with contaminants, causing metal corrosion and disconnection.

Accordingly, an object of the present invention is to provide a flat panel display device capable of preventing corrosion from occurring in a wiring connected to the pad when the pad of the panel and the driving integrated circuit are connected.

In order to achieve the above object of the present invention, a flat panel display device according to the present invention, the substrate; A pixel array formed on the display area of the substrate; A data integrated circuit unit mounted on a non-display area of the substrate and generating a signal on a data line extended in a first direction to operate the pixel array; A gate integrated circuit unit having a gate signal line transferring a signal including on and off to a gate line extending in a direction different from the first direction; And a plurality of gate pads formed in the non-display area of the substrate and integrally provided corresponding to two or more adjacent gate signal lines and connected to ends of the gate signal lines to transmit the same kind of signal.

According to the flat panel display, when the pad of the panel is connected to the driving integrated circuit, corrosion of the wiring connected to the pad can be prevented, thereby preventing deterioration of display quality of the flat panel display.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a schematic view of a liquid crystal panel of a liquid crystal display according to the present invention, and FIG. 5 is a plan view schematically illustrating a connection of an integrated circuit capable of driving a liquid crystal panel employed in the present invention.

4 and 5, the liquid crystal display includes a liquid crystal panel 130 displaying an image and driving integrated circuits 138 and 137 generating an image signal.

The liquid crystal panel 130 is injected between the first substrate 100, the second substrate 102 attached to face the first substrate 100, and the first substrate 100 and the second substrate 102. The liquid crystal 114.

A plurality of gate lines 104 and a plurality of data lines 106 are formed in a matrix form on the first substrate 100, and pixel electrodes 108 and thin film transistors (TFTs) are formed at intersections thereof. have. The second substrate 102 is formed with a color filter 112 and a transparent common electrode layer 110 formed of RGB pixels through which light is expressed. In addition, polarizers (not shown) may be attached to outer surfaces of the first substrate 100 and the second substrate 102 in accordance with the alignment direction of the liquid crystal 114 to make the transmission direction of external light constant.

5, the first pad 133 extending from the gate line 104 and the second pad 134 extending from the data line 106 are formed in the liquid crystal panel 130.

The first pad 133 is connected to the first integrated circuit 137 generating the scan voltage, and the second pad 134 is connected to the second integrated circuit 138 generating the signal voltage. Therefore, the scan voltage generated in the first integrated circuit 137 is applied to the gate line 104 through the first pad 133, and the signal voltage generated in the second integrated circuit 138 is the second pad. Is applied to data line 106 via 134. In this case, there are various methods of connecting the first pad 133 or the second pad 134 to the first integrated circuit 137 or the second integrated circuit 138. After forming a bump (bump) that can be connected to the integrated circuit to connect the pad and the integrated circuit using the bump.

The method used in the present invention for connecting the pad and the integrated circuit is a chip on glass (COG) method. In the COG method, an integrated circuit is directly mounted on a substrate of a liquid crystal panel, and the bump and anisotropic conductive film (hereinafter referred to as "ACF") of the liquid crystal panel are used without using a film used in the TAB method. A method of bonding an integrated circuit to a substrate.

As will be described in detail with reference to FIGS. 6 to 9, in the present invention, in order to prevent the display quality of the liquid crystal display device from deteriorating due to corrosion of the first integrated circuit 137, signal lines applying the same kind of signals are integrally formed. Or a first pad 133 to which a signal of the same type is applied.

6 is a schematic diagram showing the structure of a gate pad portion of a gate driving integrated circuit employed in the first embodiment of the present invention.

Referring to FIG. 6, a plurality of gate signal lines 200 are formed on a substrate on which a thin film transistor is formed. The gate signal lines 200 include a Vcom gate signal line 200a for applying a Vcom signal, a Voff gate signal line 200b for applying a Voff signal, and signal lines for applying other signals.

The gate pads 400 apply the same kind of signal and correspond to two or more adjacent gate signal lines 200 and are integrally connected to an end thereof.

That is, as shown in FIG. 6, the gate pads 400 are integrally connected to the ends of the Vcom gate pad 400a and the Voff gate signal line 200b, which are integrally connected to the ends of the Vcom gate signal line 200a. Gate pads 400b and gate pads 400 are integrally connected to the ends of signal lines to which other signals are applied.

Here, the insulating layer 450 and the common electrode layer 180 are provided on the gate pads 400. In this case, in order to electrically connect the gate electrode 150 on the gate pads 400 and the common electrode layer 180, pad contact holes 152 are integrally formed corresponding to the gate pads 400. .

In addition, the insulating layer 450 has a V shape that becomes narrower toward the gate signal lines 200.

According to the first embodiment of the present invention, by providing a gate pad that is applied to the signal applied from the same kind of signal lines integrally to reduce the resistance of the electrically or physically vulnerable parts to prevent corrosion by static electricity, etc. The display quality of the liquid crystal display device can be improved.

Fig. 7 is a schematic diagram showing the structure of a gate pad portion of a gate driving integrated circuit employed in the second embodiment of the present invention.

Referring to FIG. 7, a plurality of gate signal lines 300 are formed on a substrate on which a thin film transistor is formed. The gate signal lines 300 include a Vcom gate signal line 300a for applying a Vcom signal, a Voff gate signal line 300b for applying a Voff signal, and signal lines for applying other signals.

The gate signal lines 300 are integrally formed based on the application of the same kind of signal, and the gate pads 500 correspond to the integrally formed gate signal lines 300. It is integrally connected to the end of the.

That is, as shown in FIG. 7, the gate pads 500 are integrally connected to the ends of the Vcom gate pad 500a and the Voff gate signal line 300b integrally connected to the ends of the Vcom gate signal line 300a. Gate pads 500b and gate pads 500 are integrally connected to the ends of the signal lines to which other signals are applied.                     

Here, the insulating layer 550 and the common electrode layer 190 are provided on the gate pads 500. In this case, a pad contact hole 162 is formed to electrically connect the gate electrode 160 and the common electrode layer 190 on the gate pads 500.

In addition, the insulating layer 450 has a V shape that becomes narrower toward the gate signal lines 300.

According to the second embodiment of the present invention, the gate signal lines for applying the same kind of signal are integrally formed, and correspondingly, the gate pads connected to the ends of the gate signal lines are integrally provided to electrically or physically. Accordingly, the display quality of the liquid crystal display may be improved by reducing the resistance of the vulnerable portion to prevent corrosion by static electricity.

8 is a schematic diagram showing the structure of a gate pad portion of a gate driving integrated circuit employed in the third embodiment of the present invention.

Referring to FIG. 8, a plurality of gate signal lines 210 are formed on a substrate on which a thin film transistor is formed. The gate signal lines 210 include a Vcom gate signal line 210a for applying a Vcom signal, a Voff gate signal line 210b for applying a Voff signal, and signal lines for applying other signals.

Since the third embodiment can similarly apply the contents described in the first embodiment shown in FIG. 6, the descriptions of the same matters are omitted. However, the insulating layer 455 is a polygon formed of a plurality of sides and has a characteristic in which gate gate lines 210 are diagonally formed.                     

According to the third embodiment of the present invention, the gate pads that receive signals applied from the same type of signal lines are integrally provided to reduce the resistance of electrically or physically vulnerable portions to prevent corrosion by static electricity. The display quality of the liquid crystal display device can be improved.

9 is a schematic diagram showing the structure of a gate pad portion of a gate driving integrated circuit employed in the fourth embodiment of the present invention.

Referring to FIG. 9, a plurality of gate signal lines 310 are formed on a substrate on which a thin film transistor is formed. The gate signal lines 310 include a Vcom gate signal line 310a for applying a Vcom signal, a Voff gate signal line 310b for applying a Voff signal, and signal lines for applying other signals.

Since the fourth embodiment can similarly apply the contents described in the second embodiment shown in FIG. 7, the descriptions of the same matters are omitted. However, the insulating film 555 is a polygon consisting of a plurality of sides and has a characteristic in which gate signal lines 310 are diagonally formed.

According to the fourth embodiment of the present invention, the gate signal lines for applying the same kind of signal are integrally formed, and correspondingly, the gate pads connected to the ends of the gate signal lines are integrally provided to electrically or physically. Accordingly, the display quality of the liquid crystal display may be improved by reducing the resistance of the vulnerable portion to prevent corrosion by static electricity.

 As described above, according to the present invention, by providing the gate pads receiving signals applied from the same type of signal lines integrally, the resistance of the electrically or physically vulnerable portions can be reduced to prevent corrosion by static electricity.

In addition, by integrally forming the gate signal lines for applying the same type of signal, and correspondingly integrated with the gate pads connected to the ends of the gate signal lines to reduce the resistance of the electrically or physically vulnerable areas to reduce the static electricity Corrosion can be prevented.

Although the above has been described with reference to the preferred embodiments of the present invention, those skilled in the art may vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that modifications and variations can be made.

Claims (9)

Board; A pixel array formed on the display area of the substrate; A data integrated circuit unit mounted on a non-display area of the substrate and generating a signal on a data line extended in a first direction to operate the pixel array; A gate integrated circuit unit having a gate signal line transferring a signal including on and off to a gate line extending in a direction different from the first direction; And And a plurality of gate pads formed in the non-display area of the substrate and integrally provided in correspondence to two or more adjacent gate signal lines and connected to ends of the gate signal lines to transmit signals of the same type. . The flat panel display of claim 1, wherein the plurality of gate pads are integrally provided with two or more adjacent gate signal lines to transmit a signal of the same type. The flat panel display of claim 1, wherein the gate integrated circuit is bonded to the gate pad in a COG manner. The flat panel display of claim 1, further comprising an insulating layer on the gate pad. The flat panel display of claim 4, wherein the insulating layer has a shape that becomes narrower toward the gate signal line. The flat panel display according to claim 4, wherein the insulating film is a polygon consisting of a plurality of sides, and a side of the gate signal line has an oblique shape. The flat panel display of claim 4, further comprising a common electrode layer on the insulating layer. The flat panel display of claim 7, wherein a contact hole is formed in the gate pad to electrically connect the gate electrode connected to the gate line and the common electrode layer. The flat panel display of claim 8, wherein the contact hole is integrally formed to correspond to the gate pad.

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