KR100939116B1 - Semiconductor memory device for reducing current consumption during precharge operation - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a semiconductor memory device capable of reducing current consumption during precharging. The present invention provides a semiconductor memory device including a plurality of banks including a plurality of unit blocks having respective address decoders. The semiconductor memory device can generate a low precharge signal for each unit block in response to a precharge signal, a bank information signal, and an active block information signal.

Precharge, Current Consumption, Half Bank, Page Mode, Partial

Description

Semiconductor memory device to reduce current consumption during precharging {SEMICONDUCTOR MEMORY DEVICE FOR REDUCING CURRENT CONSUMPTION DURING PRECHARGE OPERATION}             

1 is a bank layout diagram of a semiconductor memory device having a 1K page mode.

2 is a circuit diagram of a bank precharge signal generation circuit of a semiconductor memory device according to the prior art.

3 is a circuit diagram of a bank precharge signal generation circuit of a semiconductor memory device according to an embodiment of the present invention.

* Description of the main parts of the drawing

30: logical combination

The present invention relates to a semiconductor design technology, and more particularly to a semiconductor memory device that can reduce the current consumption during precharging.                         

In general, an active signal and a row address are applied to activate a corresponding word line, and then a column address and a read or write signal are applied to output or input data. As described above, after one command signal is applied to perform a corresponding operation, preparation is required to receive a new active signal, and this preparation process is called precharge.

1 is a layout view of a bank of a semiconductor memory device having a 1K page mode.

Referring to FIG. 1, the illustrated semiconductor memory device includes a total of four banks Bank0, Bank1, Bank2, and Bank3, and each bank includes a half bank, that is, an upper half bank 11 and a lower half. The bank 10 is comprised. In the upper half bank 11 and the lower half bank 10, specific bit values of a row address are divided into '0' and '1', respectively.

The semiconductor memory devices can be driven in units of half banks, and are driven as if they have substantially eight banks. Therefore, an address decoder is provided for each half bank unit.

When performing the active command, the row address is decoded to activate only one word line in the corresponding bank. However, when precharging, the word line and the lower half of the upper half bank having the same row address as the row address of the word line that executed the active command. The precharge signal is equally activated for the word line of the bank. This is due to the generation circuit of the precharge signal, which will be described in detail.

2 is a circuit diagram of a bank precharge signal generation circuit of a semiconductor memory device according to the prior art.                         

Referring to FIG. 2, the bank precharge signal generation circuit uses a precharge signal pcgp generated by receiving a precharge command as a gate input, and has a PMOS transistor PM1 connected between a supply power supply Vdd and an output terminal, An NMOS transistor having a precharge signal (pcgp) as a gate input and connected in series between an output terminal and a ground power supply, and having a precharge signal (pcgp) and a bank information signal (bank_inf_i: i = 0 to 3) as a gate input, respectively. NM1 and NM2).

For reference, the bank precharge signal generation circuit is arranged for each half bank, and the bank information signal bank_inf_i is generated by decoding the bank addresses BA0 and BA1.

When the precharge command is applied to activate the precharge signal pcgp to a logic level high, and the bank information signal bank_inf_i corresponding to the bank is activated to a logic level high, the bank precharge signal pcgp_baz_i is a logic level low. Is activated.

Thereafter, the bank precharge signal pcgp_baz_i and the row address are input to precharge the word lines in the upper half bank and the lower half bank.

On the other hand, in the case of using the conventional technology, since the bank precharge signal pcgp_baz_i is generated using only the precharge signal pcgp and the bank information signal ba_inf_i, the same row addresses in the upper half bank and the lower half bank of the corresponding bank are generated. The word line has a precharge. This is because although the bank precharge signal generation circuit is provided in half bank units, the bank precharge signal generation circuit in the same bank has the same signal and configuration. Therefore, the word lines in the half banks that are not active are precharged to generate unnecessary current consumption.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a semiconductor memory device capable of reducing current consumption during precharging.

In accordance with an aspect of the present invention, a semiconductor memory device includes a plurality of banks including a plurality of unit blocks having respective address decoders, the precharge signal and the bank information. The low precharge signal is generated for each unit block in response to the signal and the active block information signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a circuit diagram of a bank precharge signal generation circuit of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, a bank precharge signal generation circuit according to an embodiment of the present invention uses a precharge signal pcgp as a gate input, and a PMOS transistor PM1 connected between a supply power supply Vdd and an output terminal. A logic combination unit 30 for logically combining the bank information signal bank_inf_i: i = 0 to 3 and the active bank information signal half_inf_j: j = 0 to 1, and the precharge signal pcgp as a gate input It is connected in series between the output terminal and the ground power supply, and the NMOS transistors NM1 and NM2 having the logic combination unit 30 as the gate input are provided.

In addition, the logic combination unit 30 includes a two-input NAND gate ND1 for inputting the bank information signal bank_inf_i and the active bank information signal half_inf_j, and an inverter for inverting the output signal of the NAND gate ND1. I1).

For reference, the bank information signal bank_inf_i is generated through decoding of the bank addresses BA0 and BA1, and the active bank information signal half_inf_j is information about the upper half bank or the lower half bank that performed the active command in the bank. This signal is generated with a specific bit among row addresses.

Next, an operation of the bank precharge signal generation circuit according to an embodiment of the present invention will be described.

First, when the precharge signal pcgp is activated at a logic level high, and the logical combination signal of the bank information signal ba_inf_i and the active bank information signal half_inf_j is activated at a logic level high, the bank precharge signal pcgp_halfz_i is activated. Is activated to logic level low. That is, the bank precharge signal pcgp_halfz_i is activated in a half bank unit including a word line that has performed an active command.

As described above, according to the present invention, the precharge signal can be activated in a half bank unit including a word line that has performed an active command. This is possible because the bank precharge signal pcgp_halfz_i additionally uses the active bank information signal half_inf_j, which is a signal having information on the half bank including the word line that has executed the active command. In addition, current consumption is reduced because only the active word line in the half bank is precharged.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The semiconductor memory device having a half bank structure having a 1K page mode has been described above, but the present invention is not limited to the page mode or the structure of a bank.

According to the present invention described above, the precharge signal can be generated only for the bank of the portion including the word line on which the active command is performed, and the current consumption can be reduced without performing the precharge for the entire bank.

Claims (3)

delete In a semiconductor memory device comprising a plurality of banks consisting of a plurality of unit blocks having each address decoder, A pull-up transistor using the precharge signal as a gate input; A first pull-down transistor using the precharge signal as a gate input; A logic combiner for logically combining the bank information signal and the active block information signal; And A second pull-down transistor having a gate input as an output signal of the logic combination section; And selectively performing low precharge on a unit block including an active word line. The method of claim 2, The logical combination portion, A NAND gate inputting the bank information signal and the active block information signal; And an inverter for inverting the output of the NAND gate.

Images