JPH031395A - Static type random access-memory - Google Patents

Abstract

PURPOSE: To provide a new and improved static random access memory strengthened in resistance to radiational environment by selecting a segment selected with respective segment selection lines. CONSTITUTION: Columns of a memory are divided into plural pieces of segments, and respective segments are provided with n (n is an integer) pieces of memory cells. Each segment SG has a pair of bit lines, and a precharge and equalization circuit is attached to it. A latch or a sense amplifier is provided on each segment, and e.g. when the latch is provided on each segment, a column bit line CBL is connected to an inverter, and its output is compared with a certain threshold value voltage for recognizing the data. Then, the segment is selected by an n channel pass transistor 20 through the column bit line CBL and a segment decoder so as to act for it. Thus, an allowable amount to a device having a leak occurring in the radiational environment is improved, and the device becomes operable.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to the field of integrated circuits, and more particularly to static random access memories.

Prior Art and Problems In RAMs, it is generally advantageous from a capacitance standpoint to have a very small number of cells associated with any given bit line or pair of bit lines. The need to limit the number of cells per bit line is especially important in radiation environments. This is because errors can occur if the cumulative leakage current for photocurrent from unaccessed cells is greater than the current from accessed cells. The challenge was to develop a scheme (layout and circuitry) that would make the data bus connections to the array reasonable, while also shortening the bit lines. For example, Figure 1 shows 0 connection lines (
The word line driver (indicated by the diagonal lines on the connection line) also connects the word line driver (
1 shows a conventional scheme of an array of n×m (n and m are integers) memory cells connected to a W/driver) and to a sense amplifier and an input/output I10 bus. In this memory method, as the value of n increases,
Due to the previously mentioned problem of having a large number of cells connected to a bit line, it is particularly susceptible to environments with radiation. m
A similar problem can occur when the number of pixels increases, such as increased leakage or photocurrent from unselected columns.

Another scheme would reduce the number of cells per column by placing the sense amplifiers and I10 bus between each half of the array shown in FIG. 1, as shown schematically in FIG. It was intended to be. Yet another scheme attempts to reduce the number of cells in a basic nxw array by dividing the memory cell array shown in FIG. 1 into four parts as shown schematically in FIG. A sense amplifier SA is attached to each array, and input/output I10 buses are arranged around each part of the array as shown in FIG. Additionally, word line drivers (W/L drivers) are placed between paired portions of the array. The conventional method mentioned above is
The problem is that it requires extra area, power, delay, or the I10 bus is unacceptably long.

Therefore, improved S when operating in environments with radiation
There is a demand for RAM architecture.

It is an object of this invention to provide a new and improved static random access memory.

Another object of the invention is to provide a new and improved static random access memory that is more resistant to radiation environments.

Another object of the invention is to provide a new and improved approach to segmented bitline static random access memory architecture.

Means and Operation for Solving the Problems The above-mentioned object of the present invention is to provide a static random 7-access memory (S) that divides the SRAM bit line into segments.
RAM). Each segment has its own precharge/equalization circuit and latch. This architecture operates with low power, high speed, and good tolerance for leaky devices that occur in environments with radiation, including transient transients and cumulative totals. This architecture has the advantage of low bit line capacitance for large, high-speed memories;
It has module capability for SIC.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a relatively small number of cells per bit line while maintaining a reasonable I10 bus structure.
Allows you to configure arrays. This invention is
By reducing the number of rows connected to a bit line, the ratio of current from accessed cells to leakage current from unaccessed cells is improved. FIG. 4 shows a preferred embodiment of the invention. In this figure, a column of memory is divided into multiple segments, each segment having n
(n is an integer) memory cells. The number n may be 4.8 or 16, for example. The smaller the number n, the greater the gamma large dot tolerance of the segment, but the lower the placement efficiency (the smaller the value of n, the more space is required for memory placement). Each segment SG has a pair of bit lines and has an associated precharge and equalization circuit. A latch or sense amplifier is associated with each segment. For example, with a latch in each segment, the column pit line CBL can be connected to an inverter and its output compared to a threshold voltage for recognizing data.

A segment can be selected by an n-channel pass transistor 20 to act on it through the column bit line CBL and the segment decoder. The gate of transistor 20 is a line of 2mg14 (m is an integer)
connected to one of the When a segment is selected, a signal from the segment decoder causes the gate voltage of transistor 20 to rise. This is transistor 2
0 is sufficient to turn on. The drain of transistor 20 connected to the associated column bit 1ICBL/
Through the source, memory cells receive data or data is communicated to a multiplexer. The multiplexer receives its input from a column decoder which receives column addresses. Additionally, a multiplexer is connected to the input/output I10 bus for receiving data from or transmitting data to the bus. Additionally, FIG. 4 shows an optional sense amplifier for column bit line CBL. Using dual column bit line scheme, optionally select dummy column bit 1it (
DCBL) is an optional sense amplifier and column pit line C.
It can be used in conjunction with the BL to latch information onto the column bit lines. During segment selection, the voltage on the optional column pit line DCBL is pulled down via one of the n-channel transistors 21.

The bit line DCBL may act as a control signal line for the optional sense amplifier, precharge of the I10 path, and precharge of the multiplexer. This is similar to the use of dummy bit lines in Schuster et al., where the dummy bit lines have inputs from each W/L. This invention has the advantage that the DCBL has input only from each segment select line, reducing fan-in. In fact, Schuster et al.'s scheme reduces fan-in by making the input to the dummy bit line a partially decoded row address signal rather than a fully decoded W/L, thereby reducing fan-in compared to the standard (i.e. segment An improvement can be made to the (split bit line) architecture. The segment latch can act as a sense amplifier when used with an optional sense amplifier. In terms of operation, segment latches are
When driving a bit line, a full voltage change may not necessarily occur. An optional sense amplifier ensures that the bit line undergoes a full voltage change.

FIG. 5 is a circuit diagram of a memory cell segment. Memory cell 24 is an n-channel pass transistor 2
6 to segment bit lines BL and BL. Word line WL is connected to the gate of transistor 26. The source of the bit line p-channel pull-up transistor 40.42 is connected to the power supply voltage Vdd. The drains of transistors 40 and 42 are connected to bit lines BL and BL, respectively. The input line n-channel pull-down transistor is transistor 28.
Consists of 30. The drain of the n-channel segment latch transistor 32 is connected to the transistor 28.
Connected to 30 sources. The source of transistor 32 is connected to a voltage V SS (V SS may be, for example, ground potential). The transistors for precharging the bit lines BL and BL- are composed of n-channel transistors 36 and 38. The drain and source of the n-channel transistor 34 are connected to the bit lines BL and BL.
- and its gate is connected between transistor 36°3
It is connected to the gate PCE of No. 8 and performs bit line equalization. N-channel transistors 44, 46 and inverter 50 perform segment selection.

In operation, prior to a read or write operation to a selected memory cell 24, transistors 34 .
36.38, segment bit lines BL and B
is precharged and equalized. Bit line BL
and BL, information is transferred to and from memory cell 24 via pass transistor 26.

Information from memory cell 24 is latched in conjunction with a segment latch pulse at the gate of transistor 32. The reading operation can be performed as follows. Precharge and equalize the bit lines. Energize the word line (eg, during equalization). Latch the segment. Connect the segment to column bit line CBL. and retrieve the output from the column.

The write operation order can be configured as follows, for example. Precharge and equalize the bit lines.

Force the column pit line to the level according to the input data. Connect the segment to column bit line CBL. Latch the segment. Then, the word line WL is energized (the word line goes to a high voltage level). Segment selection is
This is done by the segment connection signal on the gate of transistor 44.

During a read operation, column bit line CBL (transistor 44
is connected to the segment bit line BL via transistor 44 (when the gate of the bit line BL receives a segment connect signal). During a write operation, a segment connect signal is sent to the gate of transistor 44 of the appropriate segment and a write signal W is sent to the gate of transistor 46 of the segment. Column bit line CBL applies a voltage state to segment bit line BL. Opposite voltage states are applied to segment bit line BL- via inverter 50 and transistors 44 and 46.

Another embodiment of the invention is shown in the circuit diagram of FIG. FIG. 6 shows a p-channel latch that acts as a latch for p-channel pull-up transistors 40 and 42.
A portion of a segment with a transistor 52 is shown. n
A channel pulldown transistor is latched primarily through an n-channel latch transistor 32. The segment latch signal is passed through inverter 54 to enable transistors 42 and 32 simultaneously.

By latching both the pull-up and pull-down transistors by transistors 52 and 32, respectively, both segment bit lines can be floated prior to latching, thus minimizing differential voltage amplification due to noise. It can be suppressed.

Segmented bit line architectures can be configured in various arrangements. - format, where the column bit lines run parallel to the segment bit lines at the same interconnect level, resulting in an interconnect pitch width of three cells. This fits into the arrangement of at least one radiation hardened Sol memory cell. Another possibility is to make the column bit lines parallel to the segment bit lines but taper to another interconnect level.

This is highly desirable if the peripheral circuitry also uses another interconnect level. Another interconnect can be used as a power bus to the memory array.

When using alternate interconnect levels, it is feasible in terms of area to provide a differential pair of bit lines per column, as in the case of segments. Segmented bit lines (compared to memory of the same dimensions in a non-segmented structure)
Because it is short, it allows the use of one layer less device per segment than would be possible with an equivalently functional memory structure having simple columns of memory cells. Segmented bit line structures allow bit lines to be shortened while maintaining a reasonable chip aspect ratio, and eliminate the excess area, power requirements, and increased delay associated with the prior art techniques discussed previously. In that it does not require an I10 bus,
Are better. This superiority is especially enhanced in memory structures with multi-bit input/output I10 schemes.

As the number of segments increases significantly in a segmented bitline architecture, the degree of immunity to leakage or photocurrent due to extra pass transistors attached to the bus may decrease. This problem can be alleviated by equalizing the unselected segments at the intermediate rail (rail refers to the power supply voltage).

Alternatively, selected segments on the intermediate rail can be equalized. FIG. 7 is a circuit diagram of such a circuit. In FIG. 7, p-channel transistor 6
0 is a common drain connected to an n-channel transistor 62. The gate and source of each of transistors 60, 62 are coupled together. The drain/source regions of n-channel pass transistors 64.66 are connected to the common drain of transistors 60.62. Column bit line CBL is connected to segment bit line B1- via transistors 64,66. In operation, column pit line CBL and segment bit 15IRL are equalized at the intermediate rail by transistor 60.62 during the time that the gate of transistor 64.66 receives a high segment select signal.

Utilizing pre-decoding of word line addresses, a group of pre-decoded signals can be used to select segments. This group controls the precharging of the selected segment and the latching of the sense amplifiers, as well as enabling word line selection in the selected segment. This scheme has the advantage of tightly controlling the relative timing of word line selection, precharge and latch operations. Figure 8a has four segments and
2 is a circuit diagram of a circuit that may implement Moe's preliminary decoding scheme with 16 word lines per segment; FIG.

FIG. 8a shows the previously described segment architecture shown in FIG. In addition, series-connected Nando
A word line driver W composed of a gate 70 and an inverter 72 (subscripts indicate word line numbers, i.e., 1-16)
/L is shown.

The lower pit, upper bit and segment select lines are NANDed by NAND gate 70 to select one word line from the desired segment. For example, to select word line 15 from segment #3, lower bit 3,
A logic high signal must be received from the upper pit 3 and segment select 1i13.

An optional delay circuit (Optional Delay 1) delays turn-off of the precharge until after the word line is energized. FIG. 8b shows the change in the address of address A with respect to time, and the detection pulse AT of the address change with respect to time.
D. Selection of word line WL over time (on/off);
FIG. 4 is a time diagram showing the relative timing of the precharge and equalization enablement PEQ (for turning on the precharge and equalization circuit) versus time, and the voltages of the human lines BL and BL over time; Optional delay 1 makes it gamma dot resistant. This is because without the delay, noise (such as gamma dots) can cause one or both bit lines to drop to a low voltage state before receiving information from the cell. This can lead to latching the wrong memory state. Returning to Figure 8a, another optional delay circuit of Figure 8a (
Optional delay 2) allows time to set the differential voltages on the bit lines before latching.

FIG. 8C shows an optional delay of 2 for the precharge and equalization enable versus time and the sense amplifier latch signal (used to latch the sense amplifier) versus time. Optional Delay 2 may not be needed if Optional Delay 1 turns on the word line before precharge is turned off.

Figure 8d shows the circuitry used to implement optional delay 1. A chain of inverters 74 (only two inverters are shown, but more or fewer inverters may be used) provides one input to a NAND gate 76.

Another input to NAND gate 76 is an input to inverter chain 74 or a control signal for segment selection. An inverter 78 receives the output of NAND gate 76 and creates a sense amplifier latch signal. A signal is taken from the output of a selected inverter in inverter chain 74 to create a control signal for bit line precharging.

FIG. 8e is a circuit diagram of another embodiment in which optional delays 1 and 2 are implemented by an inverter chain 74. A precharge control signal is taken from selected outputs of the inverters in the chain. A sense amplifier latch control signal is taken from the output of the inverter chain. Although only four inverters are shown in this chain, it is possible to use more.

If there is no time left in the cycle for precharging, the eighth
In place of the circuits shown in FIGS. d and 8e, it is possible to use a circuit that has a slow response to a control signal for turning on segment selection and a fast response to a control signal for turning off segment selection. Other circuits are also possible. An important objective is to utilize the segment select lines of the predecode circuit to control the timing for word line selection.

An alternative to the preliminary decoding scheme of FIG. 8a is shown in the circuit diagram of FIG. 9. FIG. 9 shows a circuit that does not include a segment selection signal in word line selection. That is, instead of NANDing the segment selection signal and the word line address, the segment selection line signal goes directly to the segment control circuit. With this alternative, W of the unselected segment
/L can be turned on.

The line carrying the segment select signal can be used to generate a bit line delay signal on an optional dummy column bit line that controls the timing of the sensing action of the column bit line.

FIG. 10a shows a segment select line connected to n-channel transistor 21 via delay circuit 88. FIG.

A series of p-channel transistors for precharging an optional dummy column bit line DCBL are connected between voltage Vdd and column bit line DCBL. When one segment select line switches to high voltage, the column bit line DCB
Precharge is removed from L. Thereafter, the gate of one n-channel transistor 21 is energized by one segment selection line, thereby lowering the bit line DCBL to a low voltage after a period determined by delay circuit 88. The operation described above initiates the bit line ready r signal from dummy column bit 1iiDCBL.

Note that the segment select lines can be controlled by address change detection pulses.

For example, as shown in the circuit diagram of FIG.
It can be constructed by a CMOS inverter including a channel type transistor 90. The inverter can be gated by address transition detection signal ATD.

The invention described above can be constructed using various methods well known in semiconductor manufacturing technology.

Although the invention has been described in detail with reference to preferred embodiments and alternatives, it is to be understood that this description is by way of example only and is not to be construed as limiting the invention. Furthermore,
From the foregoing description, those skilled in the art will appreciate that various changes in the details of the embodiments of the invention, as well as other embodiments of the invention, will be readily apparent to those skilled in the art. For example, an n-type transistor may be replaced with a p-type transistor, or vice versa. Furthermore, bipolar transistors may be used instead of field effect transistors, or vice versa.

All such modifications and other embodiments are within the scope of the invention as defined by the claims.

This invention further has the following embodiments in relation to the above description.

(1) having a plurality of rows and rows of memory cell segments, each segment having a precharge circuit, an equalization circuit, a sense amplifier, and at least one memory cell uniquely and operably; In a related static random access memory, an SRAM includes a column bit line that can be selectively connected to a certain column of a segment, and a plurality of segment select lines, each segment select line. A static random access memory that allows lines to select selected segments.

(2) In the static random access memory described in item (1), the static random access memory has a dummy column bit line having an input from each segment line to generate the timing 1iI111Il signal.

(3) In the static random access memory described in item (1), the static random access memory is composed of an inverter in which at least one memory cell is cross-coupled.

(4) In the static random access memory described in item (3), each cross-coupled inverter is
A static random access memory consisting of an n-channel transistor and a p-channel transistor that shares a gate and drain.

(5) In the static random access memory described in (1), one row of memory in a segment
A static random access memory having circuitry capable of logically ANDing word addresses and segment selections to access cells.

(6) The static random access memory described in item 11) includes a p-channel transistor whose source is connected to the gate and an n-channel transistor whose source is connected to the gate, and the n-channel transistor A static random access memory having a segment selection circuit in which p-channel transistors and p-channel transistors share a drain.

(7) In the static random access memory described in mIJa, a static random access memory in which the latch includes a pull-up transistor.

(8) Stationary random access 4 described in (1)
A static random access memory whose latches include pull-down transistors.

(9) A memory that has a dummy bit line, and the dummy bit line has an input from a signal that traces a small group of W/L.

(10) A memory according to item (9) in which the signal is obtained from a partially decoded row address.

(11) Static random access memory (S RAM) in which the bit line of SRAM is divided into segments.
RAM) was explained. Each segment has its own precharge/equalization and latch circuits and relatively few memory cells, thus requiring less power, higher speed,
Operates with good tolerance to leaky equipment.

[Brief explanation of the drawing]

1-3 are circuit diagrams illustrating a conventional arrangement of an array of memory cells connected to a word line driver; FIG. 4 is a circuit diagram of a preferred embodiment of the present invention; and FIG. 6 is a schematic diagram of an alternative embodiment of the present invention; FIG. 7 is a schematic diagram of a circuit used to preserve gamma dot tolerance in highly segmented memory; Figure 8a is a schematic diagram of the circuitry used to construct the pre-decoding segment, Figure 8b is a time diagram associated with the circuitry of Figure 8a, and Figure 8C is associated with optional delay 2 of Figure 8a. FIG. 8d is a circuit diagram of the circuit constituting optional delay 1; FIG. 8e is a circuit diagram of another embodiment of the invention for constituting delays 1 and 2; FIG. FIGS. 10a and 10b are circuit diagrams of alternative circuits to the circuit shown in FIG. 8a, and FIGS. 10a and 10b are circuit diagrams of segment selection circuits for configuring the preliminary decoding system. Explanation of main symbols SG: Segment CBL: Column bit line 20: Pass transistor

Claims (1)

[Claims] (1) having a plurality of rows and columns of memory cell segments, each segment having a precharge circuit, an equalization circuit, a sense amplifier, and at least one memory cell uniquely and operatively associated therewith; In a static random access memory such as the one shown in FIG. A static random access memory in which a selected segment can be selected.