KR0184638B1 - Static random access memory - Google Patents

Abstract

None.

Description

Segmented Bit Line Static Random Access Memory (SRAM) Structure

1 through 3 are schematic diagrams of prior art configurations of a memory cell array connected to a withline driver.

4 shows a preferred embodiment of the present invention.

5 is a schematic diagram of a memory cell segment.

6 is a schematic diagram of an alternative embodiment of the present invention.

7 is a schematic diagram of a circuit used to maintain gamma dot hardness for highly segmented memory.

8A is a schematic diagram of a circuit used to implement a predecoded segment.

FIG. 8B is a timing diagram used with respect to the circuit of FIG. 8A. FIG.

FIG. 8C is a timing diagram used with respect to the optional delay 2 of FIG. 8A.

8d is a diagram of a circuit used to achieve a selective delay (1).

8E is a schematic diagram of an alternative embodiment of the present invention for implementing delays (1 and 2).

9 is a schematic diagram of a circuit alternative to the circuit shown in FIG. 8A for implementing a predecode configuration.

10A and 10B are schematic diagrams of segment selection circuits.

* Explanation of symbols for main parts of the drawings

20, 26, 64, 66: n-channel pass transistor

21, 34, 36, 38, 44, 46, 62, 92: n-channel transistor

24: memory cell 28, 30: pull-down transistor

32: n-channel segment latch transistor

40, 42: pull-up transistors 50, 72, 78: inverter

52: p-channel latch transistor 60, 90: p-channel transistor

70, 76: NAND gate

88: delay circuit

TECHNICAL FIELD The present invention relates to integrated circuits, and more particularly, to static random access memory.

The invention has been done with the support of the government under contract number DNA 001 # 86 # C # 0090 awarded by the Defense Nuclear Agency.

In RAM, it is generally advantageous for the RAM to have only a few cells associated with a given bit line or bit line pair because of consideration of capacitance. The need for a limitation of the number of cells per bitline is because radiation can occur if the cumulative leakage current of photocurrent from non-accessed cells is greater than the current from the accessed cell, thus causing radiation. This is especially important in a radiation environment. This problem led to the development of configurations (layouts and circuits) with short bit lines coupled with proper bussing of data in and out of the array.

For example, FIG. 1 is connected to a word line driver (W / L driver) by an n connection line (indicated by a slash connection line) and connected to the sense attenuator and input / output (I / O) buses. The configuration according to the prior art of the connected nxm (n and m are integer) memory cell arrays. In particular, this memory configuration is particularly sensitive to radiation ambient radiation because of the above-mentioned problems for many cells connected to bit lines as the value of n increases. Problems similar to leakage current or photocurrent from unselected columns can occur as m increases. In another configuration, as shown in the schematic diagram of FIG. 2, it has been attempted to reduce the number of cells per column by placing a sense amplifier and an I / O bus between each half of the array shown in FIG. In another configuration, as shown in the schematic diagram of FIG. 3, attempts have been made to reduce the number of cells in the basic nxm array by dividing the memory cell array shown in FIG. 1 into four sections. As shown, each array has an sense amplifier SA, and has an input / output bus I / O disposed around the array sections. In addition, a wordline driver (W / L driver) is disposed between the array section pairs. The prior art arrangement described above has the problem of having extra area, power, delay, or unacceptably long I / O buses as needed.

Therefore, there is a need for an improved SRAM structure that includes functionality that is effective in a radiation environment.

It is an object of the present invention to provide a new and improved static random access memory.

It is another object of the present invention to provide a new and improved static random access memory having increased hardness for the radiation atmosphere.

Another object of the present invention is to provide a new and improved circuit for a static random access memory structure having segmented bit lines.

The above objects of the present invention are achieved by an SRAM in which the bit lines of the static random access memory (SRAM) are divided into segments. Each segment has its own precharge / equalization circuit and latch. This structure provides operation at low power and high speed, and provides good tolerance to leakage devices that occur under a radiation atmosphere, including transient transient doses and cumulative total doses. This structure also has the advantages of small bit line capacitance for large high speed memories, and modular capability for ASIC applications.

The present invention allows a large memory array structure to have a relatively small number of cells per bit line while maintaining proper I / O bus structure. The present invention improves the ratio of the current from the accessed cell to the leakage current from unaccessed cells by reducing the number of rows connected to the bit line. 4 illustrates a preferred embodiment of the present invention in which columns of memory are divided into a plurality of segments, each segment having n (n is an integer) memory cells. n can be 4,8 or 16, for example. The smaller n, the larger the gamma dot hardness of the segment, but the smaller the effective layout (the smaller the value of n, the more space is required to lay out the memory). And a pair of bit lines with charge and equalization circuits attached thereto. A latch or sense amplifier is associated with each segment. For example, as in each segment, the column bit line CBL can be connected to an inverter and its output can be compared to a predetermined threshold voltage for data recognition. The segment may be selected to operate via the column bit line CBL and the segment decoder by the n-channel pass transistor 20. The gate of the transistor 20 is connected to one of 2 ^m lines (m is an integer). It is connected to one of 2 ^m lines from the segment decoder of the transistor 20. Once one segment is selected, the gate voltage of transistor 20 rises high enough to turn on transistor 20 by a signal from the segment decoder. Data is received by the memory cell or transmitted to the multiplexer through the drain / source of transistor 20 connected to the associated column bit line CBL. The multiplexer receives input from a column decoder that receives a column addresser. The multiplexer is also connected to an input / output bus (I / O) for receiving data from or transferring data to the bus. 4 also shows an optional sense amplifier for the column bit line (CBL). Dual column bit line configurations are used to allow an optional dummy column bit line (DCBL) to operate with an optional sense amplifier and column bit line (CBL) to latch information on the column bit line. Can be. During segment selection, the optional dummy column bit line DCBL is pulled down through one of the n-channel transistors 21. The bit line DCBL can operate as a control signal line for selective sense amplifiers and for precharge of the I / O bus and multiplexer. This is analogous to the use of dummy bit lines by Shuster et al. Where the dummy bit lines have inputs from each W / L. The present invention has the advantage that the DCBL has only inputs from each segment select line and reduces fan-in. In fact, the configuration of Shuster et al. Improved for standard (i.e., not segmented bit lines) structures by having a partially decoded row address signal compared to a fully decoded W / L input to the dummy bit line. Can reduce fan-in. The segment latch can act as a presense amplifier when used with an optional sense amplifier. In operation, the segment latches do not necessarily provide a full voltage swing when driving the bit lines. An optional sense amplifier ensures that the bit lines provide the full voltage swing.

5 is a schematic diagram of a memory cell segment. Memory cell 24 is connected to segment bit lines BL and BL ₋ via n-channel pass transistors 26. The word line WL is connected to the gates of the transistors 26. Bit line p-channel pull-up transistors 40 and 42 are connected to supply a voltage Vdd to their sources. The drains of the transistors 40 and 42 are connected to the bit lines BL and BL ₋ , respectively. The bit line n-channel pulldown transistors consist of transistors 28 and 30. The drain of n-channel segment latch transistor 32 is connected to the sources of transistors 28 and 30. The source of transistor 32 is connected to voltage Vss (Vss may be for example a ground potential). The precharge transistors of the bit lines BL and BL ₋ are composed of n-channel transistors 36 and 38. N-channel transistor 34 has drain and source connected across bit lines BL and BL_ and a gate connected to gates PCE of transistors 36 and 38 to provide bit line equalization. do. N-channel transistors 44 and 46 and inverter 50 provide segment selection.

In operation, segment bit lines BL and BL_ are precharged and equalized by transistors 34, 36, and 38 before a READ or WRITE operation on selected memory cell 24. Information is transferred from bit lines BL and BL_ to pass through transistor 26 to memory cell 24 and from memory cell 24. Information from memory cell 24 is latched in association with a segment latch pulse at the gate of transistor 32. READ operations include precharge and equalization of bit lines; wordline activation (eg, during equalization); Segment latches; Segment connection to the column bit line CBL; And by receiving the output from the heat. The order of operation for WRITE is, for example, bit line precharge and equalization: bringing column bit lines to levels in accordance with input data; Connecting segments to column bit lines CBL; Segment latch, and word line WL (high voltage level word line) activation. Segment selection is accomplished via a segment connection signal at the gate of transistor 44. During the READ operation, the column bit line CBL is connected to the segment bit line BL via transistor 44 (when the gate of transistor 44 receives the segment connection signal). During the WRITE operation, the intensity signal is sent to the gate of transistor 44 of the appropriate segment and the write signal W is sent to the gate of transistor 46 of the segment. The column bit line CBL determines the voltage state on the segment bit line BL. The reverse voltage state is placed on segment bit line BL_ via inverter 50 and transistors 44 and 46.

An alternative embodiment of the present invention is shown in the schematic diagram of FIG. FIG. 6 shows a segmented portion with p-channel latch transistor 52 latching p-channel pull-up transistors 40 and 42. n-channel pull-down transistors are primarily latched through n-channel latch transistor 32. The segment latch signal is passed through inverter 54 to enable transistors 52 and 32 simultaneously. Latching pull-up and pull-down transistors mode through each of the transistors 52 and 32 floats all of the segment bit lines before latching to minimize amplification of the voltage difference caused by noise.

The segment bit line structure can be implemented in various layouts. In one form, the column bit lines operate in parallel with the segment bit lines with the same level of interconnection, allowing the cells to be interconnected at three pitch intervals. This is well suited for at least one rod hardened SOI memory cell layout. In other possibilities the column bit lines operate in parallel with the segment bit lines, but only with an extra level of interconnection. This would be quite desirable if the peripheral circuitry also uses the extra level of interconnect. The redundant interconnect can also be used for bussing power to the memory array. For extra levels of interconnect, it may be convenient to have different bit line pairs per column, such as within a segment. Because segmented bit lines are short (as compared to memory of the same size without segmented structures), smaller devices may be used per segment than would be possible with a memory cell of the same function having a simple row of memory cells. Segmented bit line structures maintain a suitable aspect ratio and short bit lines without the need for excessive I / O buses that require separate area, power, and increased delay associated with the prior art described previously. Is better because it allows them to listen. This superiority is especially increased in memory structures with multiple bit input / output (I / O) configurations.

As the number of segments in the segment bit line structure is greatly increased, insensitivity to leakage or photocurrent can be reduced by additional pass transistors attached to the bus. This problem can be alleviated by having the unselected segments equalized on the mid rail (the rail called the supply voltage). Alternatively, selected segments may be equalized in the intermediate rail. 7 is a schematic diagram of a circuit for such a configuration. 7 shows the p-channel transistor 60 connected to the n-channel transistor 62 at a common drain. Each of the transistors 60 and 62 has a gate and a source coupled. N-channel pass transistors 64 and 66 are connected to a common drain of transistors 60 and 62 in the drain / source region. The column bit line CBL is connected to the segment bit line BL through transistors 64 and 66. In operation, column bit line CBL and segment bit line BL are intermediate by transistors 60 and 62 while the gates of transistors 64 and 66 receive a high segment select signal. Equalized on the rails.

The predecode of the word line address may be used such that one group of predecoded signals selects a segment. This group not only activates word line selection within the selected segment, but also controls precharge and latching of the sense amplifier for the selected segment. This configuration provides the advantage of precise control of the relative timing of word line selection, precharge and latching. FIG. 8A is a schematic diagram of a circuit capable of carrying out the above-described predecode configuration with four segments and sixteen word lines per segment. FIG. 8A shows the aforementioned segment structure shown in FIG. 2. In addition, the word line driver W / L is shown consisting of a series-connected NAND gate 70 and an inverter 72 (subscripts indicated by the number of word lines, i.e., 1-16). Low order bits, high order bits, and segment select lines are all NAND by NAND gate 70 to select one word line from the desired segment. For example, to select word line 15 from segment # 3, a logic high signal must be received from lower order bit 3, higher order bit 3 and segment select line 3.

An optional delay circuit (optional delay 1) delays the turn off of the precharge until after the word line is activated. 8b shows an address transition versus time at address A, an address transition detection pulse (ATD) versus time, a word line (WL) selection (on / off) versus time, and free (for turning on the precharge and equalization circuits). A timing diagram illustrating the relative timing of activation (PEQ) versus time of charge and equalization and bit line (BL and BL_) voltage versus time. An optional delay 1 provides gamma dot hardness, because without the delay, noise such as gamma dots causes one or both bit lines to drop to a low voltage state before receiving information from the cell. This can latch the wrong memory state. Referring again to FIG. 8A, another optional delay circuit of FIG. 8A (selective delay 2) allows time for setting the voltage difference of the bit lines before latching. 8C shows the delay of the precharge and equalization activation vs. time, and optional delay 2 relative to the sense amplifier latch signal vs. time (used to latch the sense amplifier). An optional delay 2 may not be necessary if the optimal delay 1 is to turn on the word lines before the precharge is off.

8d shows the circuit used to achieve the selective delay 1. A chain of inverters 74 (more or fewer inverters may be considered but only two inverters are shown) provide one input to the NAND gate 76. The other input to NAND gate 76 is the input to inverter chain 74 or rather the control signal for segment selection. Inverter 78 receives the output of NAND gate 76 to provide a sense amplifier latch signal. The signal is selected from the output of the selected inverter in the inverter chain 74 to provide a control signal for precharging the bit lines.

8E is a schematic diagram of another embodiment for implementing selective delays 1 and 2 through inverter chain 74. The precharge control signal is selected from the output of the selected inverter in the chain. The sense amplifier latch control signal is received from the output of the inverter chain. Although only four inverters are shown in the chain, more chains are expected.

In the absence of sufficient time in the cycle for precharge, a circuit having a low-speed response to the control signal turning on segment selection and a high-speed response to the control signal turning off segment selection is shown in FIGS. 8d and 8e. It can be used as an alternative to the circuit shown. Other circuits are also expected. The main purpose is to use the segment select line of the predecode circuit to control the timing with respect to the word line select.

Another example of the predecode configuration of FIG. 8A is shown in the schematic diagram of FIG. 9 shows a circuit which does not include a segment selection signal at the time of word line selection. Therefore, instead of NAND having the strength selection signal and the word line address, the segment selection line signal is directed directly to the segment control circuit. This other example turns on W / Ls in unselected segments.

Lines for transmitting the segment select signal may be used to generate a bit line ready signal on an optimal dummy column bit line that controls column bit line sensing timing. FIG. 10A shows segment select lines connected to n-channel transistors 21 through a delay circuit 88. FIG. A series of p-channel transistors that precharge the optional dummy column bit line DCBL are connected between the voltage Vdd and the column bit line DCBL. If one of the segment select lines is switched to a high voltage, the precharge is removed from the column bit line DCBL. Then, after the time period determined by the delay circuit 88 due to the gate of one n-channel transistor 21 activated by one of the segment select lines, the bit line DCBL drops to a low voltage. . The above operation initializes the bit line ready signal from the dummy column bit line DCBL. Note that the segment select lines can be controlled by an address transition detection pulse. For example, as shown in the schematic diagram of FIG. 10B, segment selection may be performed by a CMOS inverter including a p-channel transistor 90 connected to an n-channel transistor 92. The inverter may be gated by an address transition detection signal ATD.

The present invention described above may be constructed in accordance with various methods known in the semiconductor manufacturing art.

Although the invention has been described in detail herein in the preferred embodiments and by any of the above-described alternative examples, it is to be understood that this description is illustrative and not in a limiting sense. In addition, it will be apparent to those skilled in the art that various modifications may be made to embodiments of the present invention and other embodiments of the present invention with reference to the present invention. For example, an n-type transistor can be replaced with a p-type transistor and vice versa. Bipolar transistors can also be used in place of field effect transistors and vice versa. As will be claimed in the following, it will be appreciated that such variations and incidental embodiments are within the scope and spirit of the present invention.

Claims (10)

A plurality of rows and columns of memory cell segments, each segment comprising a precharge circuit, an equalization circuit, a latch and at least one memory cell that are operably uniquely associated with the segment And a column bit line that can be selectively wrapped in one of the columns of the plurality of segments, and a plurality of segment selection lines, each of which can select a selected segment. 2. The static random access memory of claim 1, further comprising a dummy column bit line having an input from each segment line to generate a timing control signal. The static random access memory of claim 1, wherein the at least one memory cell comprises cross coupled inverters. 4. The static random access memory of claim 3 wherein each cross coupled inverter comprises a p-channel transistor sharing a gate and a drain with an n-channel transistor. 2. The static random access memory of claim 1 further comprising circuitry operable to logically NAND both word address and segment selection to access a row of memory cells in the segment. 2. The apparatus of claim 1, further comprising a segment selection circuit comprising a p-channel transistor comprising a source connected to a gate, and an n-channel transistor comprising a source connected to a gate, wherein the n-channel and p- A static random access memory, characterized in that the channel transistors share a drain, 2. The static random access memory of claim 1 wherein the latch comprises a pull-up transistor. 2. The static random access memory of claim 1 wherein the latch further comprises a pull-down transistor. A plurality of rows and columns of memory cell segments, each of the segments comprising a precharge circuit, an equalization circuit, a latch and at least one memory cell that are operably uniquely associated; A column bit line that can be selectively connected to one of the segments of the columns, A plurality of segment selection lines, each of which may select a selected segment, and And a dummy column bit line having an input from a signal that activates subgroups of word lines. 10. The memory of claim 9 wherein the signal originates from a partially decoded row address.

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