JP2980472B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundant circuit.

[0002]

2. Description of the Related Art In recent years, a semiconductor memory device is often provided with a redundant configuration in order to prevent a decrease in yield due to an increase in capacity. That is, a spare memory cell array is mounted on the chip in advance and found by inspection for the purpose of mitigating a decrease in yield due to a bit defect, a column defect, or a row defect on the chip that occurred during the manufacturing process. A defective chip is replaced by replacing a defective portion with a spare cell. Conventional devices with such redundant circuits include, for example, the 1982 IEEE International Solid-State
Cirduit Conference Digest of Technical Paper, “A
64Kb CMOS SRAMs ", S.Konishi., Et al., Pp. 258-259.

Here, in order to replace a defective bit with a spare cell array by utilizing a redundant configuration, a mechanism for accessing the spare cell array when an address signal for selecting a defective cell is externally input is realized. Required.

In general, a fuse element is formed using a wiring layer or the like, and a laser blow for irradiating a laser to blow is performed to realize such an access mechanism. For example, in an SRAM that relieves defective cells in units of rows (rows), fuses are arranged between each word line and a circuit that drives the word line. Then, the fuse provided on the word line of the defective row is blown by a laser in advance, so that even if an address signal for selecting this word line is inputted, it is not activated. A conventional example of such an SRAM is disclosed in, for example,
No. 8899 or JP-A-60-20397.

FIG. 12 shows a configuration of an SRAM in which eight spare rows are arranged in 1024 normal rows as such a conventional device. In this device, in order to drive a normal memory cell MC by dividing it into sections, two word lines are provided.
Are arranged in layers.

A row main decoder RMD1501 is arranged at an end of the memory cell array NMA1501. The row main decoder RMD1501 usually includes a NAND circuit NA150 for each main word line NMW.
Word line buffer WB1 composed of one and two stage inverters
501 and fuse FU for defective low isolation
1501 are connected in series. The row predecode signal generated by the address decoder AD1601 shown in FIG. 13 is supplied to the row main decoder RMD1501.

As shown in FIG. 13, for example, a 10-bit address signal is externally input to the input terminals Ax0 to Ax9 to the address decoder AD1601. The address signal is decoded by the row predecoder RPD1601, and the row predecode signals / X0 ./X1, X0.
Output as 1, ... This signal is also applied to a spare row decoder RRD1801 described later, output as a spare row selection signal, and applied to a spare memory cell array.

In the row direction of the memory cell array NMA1501, a column decoder CD1501 and a section decoder SD1501 are provided for each section.

In FIG. 12, the selection of the memory cell MC in the row direction is performed as follows. The row predecode signal is supplied to the row main decoder RMD1501,
Any one of the 24 normal main word lines NMW
A book is selected. Further, the section decoder SD15
01 selects any section, and the word line SW in that section rises.

The selection in the row direction is performed by the column decoder CD15.
This is performed by selecting any one bit line by 01.

In the spare memory cell array RMW, spare memory cells for eight rows are arranged. A spare main word line RMW is provided at an end of the spare memory cell array RMW.
Are provided. A spare word line buffer WB1501 is provided for selecting. The spare row decoder RRD1 shown in FIG.
The spare row decode signal generated by the block 801 is input.

The spare row decoder R shown in FIG.
The RD 1801 is also disclosed in Japanese Patent Application Laid-Open No. 63-168900, and receives the above-mentioned row predecode signals /X0./X1, X0./X1,. The input row predecode signal is input to a NAND circuit NA1801 via a switching CMOS transmission gate circuit TG in which a P-channel transistor and an N-channel transistor are connected in parallel. here,
CMOS transmission gate circuit TG for switch
The open / closed state of each gate in the output signal F, from the two sets of fuse selection circuits FS1801 and FS1802,
/ F. One of the gates is opened by the signals F and / F, and any one of the four predecode signals passes through and is output.

A plurality of switching CMOS transmission gate circuits TG are provided, and respective output signals SP01i to SP89i are input to a NAND circuit NA1801. Further, this NAND circuit NA1801 has
Spare enable signature circuit S for selecting any of a plurality of spare row decoders RRD1801
The spare enable signal SPEi from the ES 1701 is input.

When spare row decoder RRD 1801 is not selected, spare enable signal SPEi is at a low level, and a high-level spare row decode signal is output irrespective of signals SP01i to SP89i. When the spare enable signal SPEi is at the high level, the level of the spare row decode signal is determined based on the signals SP01i to SP89i that have passed through the respective switching CMOS transmission gate circuits TG.

The fuse selection circuit FS includes a fuse FU 1701 and an inverter IN 170 as shown in FIG.
1, capacitors C1701 and C1702, and an N-channel transistor N1701. And fuse FU
The combination of the levels of the signals F and / F differs depending on whether or not the signal 1701 is blown. Fuse FU17
When 01 is not blown, the signal F is at a high level and the signal / F is at a low level. Fuse FU1701
Is blown, the signal F is low and the signal / F is high.

In a conventional SRAM having such a configuration, if any of the normal rows has a defect, the defective low isolation fuse FU1501 in the defective row is blown by a laser. This allows
Even if an address signal for selecting the defective row is input, the defective row is not accessed. Further, since each normal main word line NMW is fixed at a high level by a normally-on P-channel transistor P1501 as shown in FIG. 12, it does not enter a floating state but maintains a non-selected state.

When this defective row is selected, one of the spare rows is automatically selected instead. To select any of the spare rows, a spare row decoder RRD1
It is necessary to perform fuse blowing on the fuse selection circuit FS 801 as well. As shown in FIG.
In order to select one spare row, a maximum of ten row predecode signals / X0 ./X1, X0.
.., X8 and X9 and a spare row decoder RRD18
A total of 11 blows is required, including a spare enable signature circuit SES1701 for selecting 01.

FIG. 1 is a circuit diagram of a conventional SRAM having such a configuration, in which only the circuit configuration of the normal main word line NMW and the spare main word line RMW is shown.
6. As described above, the row main decoder RMD1901 composed of a NAND circuit and the word line buffer WB150 are connected to the 1024 rows of normal main word lines NMW.
1 and the fuse FU1901 are arranged in series. A word line buffer WB1901 is arranged for the eight rows of spare main word lines RMW. The normal main word line NMW and the spare main word line RMW are in a selected state when at the low level.

FIG. 1 shows a configuration of a normal main word line NMW and a spare main word line RMW in another conventional SRAM.
FIG. Normally, the row main decoder RMD2001 and the inverter IN200 are connected to the end of the main word line NMW.
2. The fuse FU2001 and the inverter IN2001 are connected in series. Unlike the one shown in FIG. 16, here, the fuse FU2001 is connected to the inverter IN2.
001 and the inverter IN2002. Normally, when the load capacity of the main word line NMW is large, the fuse F
By providing U between the inverters IN2001 and IN2002 of the word line buffer WB, the charge / discharge speed can be increased.

Here, inverters IN2001 and IN2
002 is connected to the drains of N-channel transistors N2001 and N2002. The sources of the transistors N2001 and N2002 are grounded. The gate of the transistor N2001 is connected to the output node of the inverter IN2001, and the transistor N2002 is in a normally-on state. Although not necessarily required, the transistor N2001 normally has a function of feeding back the level of the main word line NMW2001 to stably maintain the level of the input node of the inverter IN2001. The transistor N2002 is connected to the fuse FU2001.
Is provided to reliably maintain the level of the input node of the inverter IN2001 at the low level when the inverter IN2001 and the inverter IN2001 are driven.
2 is set sufficiently lower than that of the transistor constituting the second transistor. The normal main word line NMW and the spare main word line RMW are in a selected state when at low level.

FIG. 18 shows a configuration of a normal main word line NMW and a spare main word line RMW in another SRAM. The normal main word line NMW and the spare main word line RMW are in the selected state when they are at the high level, contrary to those shown in FIGS. For this reason,
The number of stages of inverters provided for each word line is one, unlike those of FIGS. A row main decoder RMD2101 composed of a NAND circuit, a word line buffer WB2102 composed of one inverter, and a fuse FU2101 are connected in series to an end of the normal main word line NMW. A word line buffer WB2101 composed of one inverter is connected to an end of the spare main word line RMW.

The normal main word line NM shown in FIG.
The configuration of W and the spare main word line RMW corresponds to the configuration shown in FIG. 16 in which the number of inverters is reduced to one.

The normal main word line NM shown in FIG.
The configuration of W and the spare main word line corresponds to the configuration shown in FIG. 17 in which the number of inverter stages is reduced to one.
The normal main word line NMW and the spare main word line shown in FIG. 19 are in a selected state at the high level similarly to the case shown in FIG.

Each of the above-described redundant circuits has a row (low).
It is provided in the direction. On the other hand, there is a type in which a redundant circuit is provided in a column direction. Such a configuration is effective in preventing a delay in the word line propagation time and reducing power consumption during operation.

FIG. 2 shows a configuration of a conventional column-direction redundant circuit.
0, each section SEC91 to SEC9
N in which a normal column and a spare column are arranged, and a section SEC1001 including only normal columns as shown in FIG.
~ SEC100N and section S consisting only of spare columns
EC100N + 1 and EC100N + 1.

In the circuit shown in FIG. 20, the core region is N
Is divided into sections SEC91 to SEC9N. Each section includes a memory cell array MCA91,
A sense amplifier and write circuit SAW91 and a column gate CG91 are provided.

The memory cell array MCA91 has eight I
/ O1 to I / O8, and each I / O
Has n normal columns and S spare columns. Therefore, s normal columns can be relieved for each I / O. This means that 8 * s * N spare columns are arranged for the entire SRAM.

In the circuit shown in FIG. 21, only the normal columns are arranged in the normal sections SEC1001 to SEC100N, and the spare columns are arranged in the spare section SEC100.
N + 1. Spare section SEC100
Eight I / O1 to I / O8 are configured in N + 1, and s spare columns are arranged in each I / O.

In the circuits shown in FIG. 20 and FIG. 21, respectively, when there is a defect in a normal column, isolation is performed using a control signal without using a fuse. The control signals include a section decode signal S for selecting a section, a column decode signal C for selecting a column, and column gates CG91 and CG10.
1 and a common bit line selection signal CB for selecting a common bit line.
L, a spare decode signal SPD given to the spare decoder, and a spare hit signal SPH indicating that the corresponding spare column has been selected.
Is used.

Among these control signals, the column decode signal C, the section decode signal S, and the preliminary hit signal SPH are generated by a circuit as shown in FIG. M column address input signals CAI are input to the column address input buffer CAB, and the output thereof is applied to the column decoder CD1101 and output as H column decode signals C. The output of the column address input buffer CAB is connected to the fuse selection circuit FS110.
1 and its output is the spare column decoder SCD
1101.

On the other hand, n section address input signals for selecting a section are input to the section address input buffer SAB, and the output from the buffer SAB is applied to the section decoder SD1101.
N section decode signals S are output. Also,
The output from section address input buffer SAB is provided to fuse selection circuit FS1102, and the output from fuse selection circuit FS1102 is provided to spare section decoder SSD1101. Here, the fuse selection circuits FS1101 and FS1102 have a configuration as shown in FIG. 15 similarly to the fuse circuit FS1801 shown in FIG.

The outputs of spare column decoder SCD1101 and spare section decoder SSD1101 are applied to AND circuit 1101, and output signal SPD (1) of AND circuit 1101 is applied to OR circuit 1101. The OR circuit 1101 receives s output signals from such an AND circuit as the number of spare columns, and outputs one spare hit signal SPH.

The increase in the memory cell array area due to the provision of the redundant circuit in the circuit shown in FIG. 20 and the required number of spare column decoders are as follows. As described above, since the number of spare columns is 8 · s · N columns, the rate of increase in the memory cell array area is (8 · s · N) / (8 · n ·
N) = s / n. The decoder for the spare column is s ·
N pieces are required.

In the circuit shown in FIG. 21, the rate of increase in the memory cell array area is 1 / N, and s column decoders for spare columns are required.

In the above-described conventional device, when a redundant circuit is provided, the following elements must be added as compared with a device having no redundant circuit.

(1) Spare memory cell array and word line buffer (2) Defective low isolation fuse (3) Normally provided so that the normal main word line after fuse blowing is not always in a floating state but always in a non-selected state Transistor in state (4) Spare row decoder The approximate rate of increase in area by adding such elements is as follows.

(1) Increase in area due to addition of spare memory cell array and word line buffer 1024 ordinary memory cell arrays are provided.
Assuming that a spare memory cell array of eight rows is added to this, the area is increased by 0.8% from 1032/1024 = 1.008.

(2) Increase in area due to the addition of defective row isolation fuses It is necessary to provide 1024 fuses, the same number as the normal 1024 rows, between the memory cell array and the word line buffer. This fuse must be arranged near the memory cell array, but a distance of about 100 μm is required between the fuse and the circuit and wiring around the fuse element when blowing with a laser so as not to damage the circuit and wiring. The area increases by this distance.

(3) An increase in area due to the addition of a normally-on transistor This transistor may be formed using a MOS transistor having a very low driving force or a high-resistance element. A column increase is sufficient.

(4) Increase of area by adding spare row decoder In the spare row decoder shown in FIG. 14, the number of spare rows is 11 × 8, and nine sets of decoders including 88 fuses are required. Becomes As a rough estimate, the area of one spare row decoder required for spare row 1 is about 20,000 μm
² Therefore, when eight spare row decoders are provided, an area of about 160000 μm ² is increased.

Next, a description will be given of the number of fuse blowing steps which is increased by adopting the redundant circuit configuration. Table 1
7 shows the number of fuse blows for the spare row in the SRAM of 64K bits to the SRAM of 16M.

[0042]

[Table 1] Here, one spare row is provided for every 128 normal rows. Taking a 64K bit SRAM as an example, two spare rows are provided for every 256 normal rows. The maximum number of blown fuses in a defective row is two. In this case, the number of fuse blows necessary for storing the address of the defective row and the number of fuse blows for enabling the spare row in the spare row decoder are 18 at the maximum. Therefore, the total number of fuse blows is 2 at maximum.
It becomes 0.

As apparent from Table 1, most of the number of fuse blows is occupied by the spare row decoder for storing the address of the defective row and for the spare enable.
And the number of blows will increase significantly with the increase in capacity.

As described above, the increase in the area and the number of manufacturing steps due to the configuration of the redundant circuits in the row direction has been described. Similarly, the increase in the area and the number of manufacturing steps when the redundant circuits are provided in the column direction will be described. .

As described above, in the circuit configuration shown in FIG. 20, the rate of increase in area due to the provision of the spare memory cell array is s / n, and in the circuit configuration shown in FIG. / N.

Since no fuse for isolating the defective column is used, the increase in area by this amount is zero. Similarly, since a transistor in a normally-on state is not added, the area does not increase by this amount.

The configuration shown in FIG. 20 requires s × N spare column decoders, while the configuration shown in FIG. 21 requires s spare column decoders. 1Mbit SRAM with 8 I / O configuration, with 1 normal column
If eight spare columns are provided in 024 columns, the column address required for decoding is 7 bits, and the area of about 15000 μm ² per spare column increases. Therefore,
Since a total of eight spare column decoders are required, about 1
Increase by 20,000 μm ² .

Table 2 shows the number of fuse blowing steps by providing a redundant circuit in the column direction.

[0049]

[Table 2] As with the row direction shown in Table 1, the spare column is the normal column 128
One row is provided for each row. As is evident from Table 2, the number of blows greatly increases with an increase in capacity, although not as much as when a spare row is provided.

[0050]

As described above,
In a conventional semiconductor memory device, the area is increased and the number of manufacturing steps is greatly increased due to the redundant circuit configuration. This has led to an increase in chip size and an increase in manufacturing time and manufacturing cost.

The present invention has been made in view of the above circumstances, and provides a semiconductor memory device capable of suppressing an increase in chip area and reducing a process of storing information necessary for selecting a spare row or a spare column. The purpose is to provide.

[0052]

A semiconductor memory device according to the present invention includes a plurality of normal rows and a plurality of blocks in which memory cells are arranged in one spare row. A plurality of normal row selection lines for selecting any one of the normal rows, one spare row selection line for selecting the spare row in place of a defect in one of the normal rows, and a plurality of normal row selection lines. A normal row selection control circuit including a fuse for disconnection at the time of failure which is cut when there is a defect in the corresponding normal row selection line, and provided in the spare row selection line, A spare row selection control circuit for driving the spare row selection line, wherein each of the normal row selection control circuits is based on an output of a row decoder.
When the normal row is selected, the normal row selection line is driven to a selected state, and when the normal row is not selected, the normal row selection line is driven to a non-selected state. Then, a first potential setting means for setting the potential of the blown fuse terminal to a non-selection potential given when the normal row is not selected, and provided for each normal row, the fuse of the normal row is provided. When the potential of the terminal is applied, one common terminal provided in common to each normal row is set to the first potential when the normal row is selected, and the first potential is set when the normal row is not selected. A second potential setting unit that does not perform an operation of setting the potential of the common terminal, and a third potential setting unit that is provided at the common terminal and that constantly performs an operation of setting the common terminal to the second potential. The second potential setting means is configured to The drive capability of setting a terminal to the first potential is greater than the drive capability of the third potential setting means to set the common terminal to the second potential, and the spare row selection control circuit includes A block selection signal for selecting any one of them and the potential of the common terminal are given, and the spare row selection line is selected only when the block is selected and the common terminal is at the second potential. And a driving unit for driving the spare row selection line to a non-selected state in any other case. The same applies to the case where the above configuration for rows is applied to columns. In this case, the semiconductor memory device of the present invention includes a plurality of normal columns and a plurality of blocks each having a memory cell arranged in one spare column, and each of the plurality of blocks selects one of the normal columns. A normal column selection line, one spare column selection line for selecting the spare column in place of a defect in any of the normal columns, and a corresponding normal column selection line provided for each of the normal column selection lines. A normal column selection control circuit including a defective fuse for cutting when a corresponding corresponding normal column selection line is defective, and a spare column selection line, A spare column selection control circuit to be driven, and each of the normal column selection control circuits drives the normal column selection line to a selected state when the normal column is selected, based on an output of a column decoder. Normal when the column is not selected A drive unit for driving the normal column selection line to a non-selection state, and setting the potential of the cut fuse terminal to a non-selection potential applied when the normal column is not selected when the defective fuse is cut. The first potential setting means, which is provided for each normal column, is supplied with the potential of the fuse terminal of the normal column, and the common terminal provided commonly for each normal column is connected to the normal terminal. A second potential setting means for performing an operation of setting the first potential when the column is selected and not performing an operation of setting the first potential when the normal column is not selected; A third potential setting means for constantly setting a terminal to a second potential; and a driving capability of the second potential setting means for setting the common terminal to the first potential. 3 potential setting means before the common terminal. Greater than the driving ability to set to the second potential,
The spare column selection control circuit is provided with a block selection signal for selecting one of the blocks and the potential of the common terminal, and when the block is selected and the common terminal is at the second potential. And driving means for driving the spare column selection line to a selected state, and in any other case, driving the spare column selection line to a non-selected state.

Alternatively, the semiconductor memory device of the present invention may be similarly provided with the configuration provided in the row direction in the column direction.

[0054]

In each block, if any of the normal rows has a defect, the disconnection fuse for the normal row corresponding to the normal row is cut. First potential setting means sets the potential of the blown fuse terminal to a non-selection potential. When a normal row having no defect is selected based on the output of the row decoder, the driving unit drives the normal row selection line to a selected state. In this case, of the second potential setting means provided for each normal row, the one provided for the selected normal row sets the common terminal to the first potential, and sets the other non-selected normal potentials. Those provided in the row do not perform such a setting operation.
The third potential setting means performs an operation of always setting the common terminal to the second potential. However, the driving ability of the second potential setting means to set the common terminal to the first potential is larger than the driving ability of the third potential setting means to set the common terminal to the second potential. In this case, the common terminal is the first
Is set to the potential of Therefore, regardless of whether the block is selected or not, since the common terminal is at the first potential, the spare row selection control circuit drives the spare row selection line to the non-selected state. When a normal row having a defect is selected, the fuse terminals of the normal row are set to the non-selection potential. Therefore, all the second potential setting means provided in each normal row do not perform the operation of setting the common terminal to the first potential. For this reason, the common terminal is set to the second potential by the third potential setting means. When the block is selected and the common terminal is at the second potential, the spare row selection control circuit drives the spare row selection line to the selected state. in this way,
A plurality of normal rows and one spare row are provided for each block. If the normal row is defective and this row is selected, the spare row is automatically selected. Therefore, a spare row decoder for selecting a spare row and a unit for storing information for selecting a spare row are unnecessary, and the chip area can be reduced. Further, a step of writing the spare row selection information is not required. A similar effect occurs when a similar configuration is provided in the column direction.

[0055]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration in a row direction in one block in a semiconductor memory device according to a first embodiment of the present invention. The first embodiment is equivalent to the case where the present invention is applied to the conventional apparatus shown in FIG.

In each block, 128 normal main word lines NMW1 to NMW128 and one spare main word line RMW are provided.

Each of the normal main word lines NMW has a row main decoder RMD1 comprising a NAND circuit at its end.
Word line buffer WB comprising 1 and 2 inverters
11 and a defective low isolation fuse FU11 are connected in series. Normally, the main word line N
At the other end of MW1 to NMW128, a normally-on P-channel transistor P12 having a small driving force is provided.

An inverter IN12, a NOR circuit NOR11, and an inverter IN11 are connected in series to an end of the spare main word line RMW.

One common block line R11 is provided in a direction orthogonal to the word lines. This common block line R11 has normal main word lines NMW1 to NMW
The drain of the P-channel transistor P11, the drain of the N-channel transistor N11, and the other input terminal of the NOR circuit NOR11 provided at the intersection with the MW128 are connected.

The source of the P-channel transistor P11 is connected to the power supply voltage VDD terminal, and the gate is usually connected to the main word line NMW. The N-channel transistor N11 has a gate connected to the power supply voltage VDD terminal, is in a normally-on state, and has a source grounded. This N
The driving capability of the channel transistor N11 is set sufficiently smaller than that of the P-channel transistor P11.

In the first embodiment having such a configuration, the operation is as follows. Normal main word line NMW1
To NMW 128, or even if there is a defect in any of the other normal main word lines NMW.
Is selected, the selected normal main word line N
Only MW goes low. Then, only the P-channel transistor P11 whose gate is connected to the selected normal main word line NMW turns on, and the spare selection line R1
Charge 1. As a result, a high-level signal is input to the NOR circuit NOR11, and the spare main word line RMW is held at the high level and maintains a non-selected state regardless of the block selection signal input to the inverter INV12.

Normal main word lines NMW1 to NMW12
In the case where a defective main word line NMW is selected and the defective main word line NMW is selected, the following operation is performed and the spare main word line RMW is replaced.

For example, it is assumed that the normal main word line NMW1 in the normal memory cell array is defective, the defective low isolation fuse FU11 is blown, and the normal main word line NMW1 is selected. When the defective row isolation fuse FU11 is blown, the word line buffer 11 and the row main decoder RMD11 and the normal main word line NMW1 are cut off. Thereby, the low main decoder RMD
Regardless of the low predecode signal input to 11,
Normally, main word line NMW1 is charged by P-channel transistor P12 and held at a high level.

When the normal main word line NMW1 is selected in this state, all the normal main word lines NMW1 are selected.
To NMW128 are in a non-selected state at a high level.
As a result, all the P-channel transistors P11 are turned off, and the N-channel transistor N11 is normally on, so that the block common line R11 goes low. Since this low-level signal is input to one input terminal of the NOR circuit NOR11, the inverter IN1
2, the level of spare main word line RMW changes according to a block selection signal input through the same. When a high-level block selection signal is input to the inverter IN12, the spare main word line RMW goes low and is selected.

As described above, in the first embodiment, when the normal main word line NMW is selected in each block, any one of the normal main word lines NMW is selected according to the row predecode signal. If any one of the normal main word lines NMW has a defect, the defective isolation fuse is blown, and if the defective normal main word line NMW is selected, all the normal main word lines NMW are row pre-decoded. It becomes a non-selection state irrespective of the signal. Thereby, the spare main word line RMW can be automatically selected. When this block is selected, the spare main word line R
MW is selected.

FIG. 2 shows a configuration of a semiconductor memory device according to a second embodiment of the present invention. This second embodiment is shown in FIG.
The present invention is applied to the conventional apparatus shown in FIG. 17, the row main decoder RMD21, the inverter IN22, the defective row isolation fuse FU21, and the inverter IN are connected to the ends of the normal main word lines NMW1 to NMW128, respectively.
21 are connected in series, and N-channel transistors N21 and N23 are further provided.

The output terminal of NAND circuit NA21 is connected to one end of spare main word line RMW, and one input terminal receives a block selection signal.

A block common line R21 is provided in a direction orthogonal to the word line, and one end of the block common line R21 is connected to the NAND circuit N.
A21 is connected to the other input terminal. This block common line R21 and each of the normal main word lines NMW1 to NM
N-channel transistor N
22 are provided. The drain of each N-channel transistor N22 is connected to the block common line R21, the source is grounded, and the gate is connected to the input terminal of each inverter IN21. Further, the drain of a normally-on P-channel transistor P21 whose driving capability is sufficiently smaller than that of the N-channel transistor N22 is connected to the block common line R21.

Normal main word lines NMW1 to NMW12
8, if no defect exists, or if a defect is present but another is selected,
The input terminal of the selected low inverter IN21 goes high, and the main word line NMW normally goes low. An N-channel transistor N22 having a gate connected to the input terminal of the selected low inverter IN21.
Turns on to discharge the block common line R21. The NAND circuit NA21 is supplied with a low-level input from the block common line R21, and the spare main word line RMW is always kept at a high level and is in a non-selected state.

Normal main word lines NMW1 to NMW12
8 is defective, the defective low isolation fuse FU21 is blown, and the normal main word line NMW is connected to the N-channel transistor N21.
, And N23, and is kept at a high level, and becomes a non-selected state. When a defective main word line NMW is selected, all the N-channel transistors N22 are kept off and the N-channel transistors P21 are normally on, so that the block common line R21 is charged to a high level. Become. This high level input is NAN
D circuit NA21 is applied and spare main word line RMW
The level changes according to the block selection signal, and when a high-level block selection signal is input, the level changes to a low level to be in a selected state.

FIG. 3 shows the configuration of the semiconductor memory device according to the third embodiment of the present invention. The configuration of this embodiment is similar to that of the first embodiment shown in FIG. A row main decoder RMD31, a defective row isolation fuse FU31, and a word line buffer WB including a two-stage inverter are connected in series to the ends of the normal main word lines NMW1 to NMW128, respectively.
Further, a P-channel transistor P31 is connected between the node connecting the input terminal of the word line buffer WB and the output terminal of the row main decoder RMD31 and the power supply voltage VDD terminal.
Is connected. This P-channel transistor P31
Is in a normally-on state with its gate grounded.

Further, an inverter IN32, a NOR circuit NOR31, and an inverter IN31 are connected in series to an end of the spare main word line RMW.

A block common line R31 is provided in a direction orthogonal to the word lines, and one end is connected to one input terminal of a NOR circuit NOR31.

Normal main word lines NMW1 to NMW12
8, if no defect exists, or if a defect is present but another is selected,
The selected normal main word line NMW goes low. A P-channel transistor P3 whose gate is connected to the input terminal of the selected row word line buffer WB
2 is turned on by inputting a low level to the gate, and charges the block common line R31. The NOR circuit NOR31 receives a high-level input from the block common line R31, and the spare main word line RMW is always kept at a high level and is in a non-selected state.

Normal main word lines NMW1 to NMW12
In the case where there is a defect in any one of 8, the defective low isolation fuse FU is blown, and the normal main word line NMW is held at a high level by the P-channel transistor P <b> 31 to be in a non-selected state. When a defective main word line NMW is selected, all P-channel transistors P32 are kept off, and N
Since the channel transistor N31 is normally on, the block common line R31 is discharged to a low level. This low-level input is supplied to a NOR circuit NOR31, and when a high-level block selection signal is input, the spare main word line RMW goes to a low level to be in a selected state.

In the fourth embodiment of the present invention shown in FIG. 4, contrary to the above-described first to third embodiments, each word line is in a selected state when it goes high. 18 corresponds to a device in which the present invention is applied to the conventional device shown in FIG. Normally, a block common line R41 is provided in a direction orthogonal to main word lines NMW1 to NMW128, an N-channel transistor N41 is provided at each intersection, and a normally-on P-channel transistor P41 having sufficiently lower driving capability than this transistor N41. Drain is connected.

Normal main word lines NMW1 to NMW12
In the case where there is no defect in 8 or when there is a defect and a portion other than the defective portion is selected, the selected normal main word line NMW goes high. In this case, the N-channel transistor N41 whose gate is connected to the selected normal main word line NMW is turned on, and the block common line R
41 is at the low level, and the spare main word line RMW is held at the low level to maintain the non-selected state.

When the normal main word line NMW is defective and its fuse FU41 is blown and the defective normal main word line NMW is selected, all the normal main word lines NMW1 to NMW128 are held at the low level. You. All the N-channel transistors N41 are turned off, and the P-channel transistor P41 is normally on, so that the block common line R41 goes high.
When the block selection signal is at a high level and this block is selected, the spare main word line RMW goes to a high level to be in a selected state.

FIG. 5 shows the configuration of an apparatus according to a fifth embodiment of the present invention. In the fifth embodiment, similarly to the fourth embodiment, each word line becomes a selected state when it goes high, and corresponds to the case where the present invention is applied to the conventional device shown in FIG. . An N-channel transistor P52 is provided at each intersection of the block common line R51 and the normal main word lines NMW1 to NMW128.
The drain of a normally-on N-channel transistor N51 having sufficiently lower driving capability than that of the N-channel transistor N51 is connected.

Normal main word lines NMW1 to NMW12
In the case where there is no defect in 8 or when there is a defect and a portion other than the defective portion is selected, the selected normal main word line NMW goes high as in the fourth embodiment. Since the P-channel transistor P52 whose gate is connected to the input terminal of the selected low-level inverter IN52 is turned on, the block common line R51 goes high, and the spare main word line RMW is held low and remains unselected. I do.

Normally, there is a defect in the main word line NMW,
When a defective normal main word line NMW is selected, all the normal main word lines NMW1 to NMW128
Are held at the low level. P-channel transistor P
52 are all off, and the N-channel transistor N51 is in the on state, so that the block common line R51 is at low level. When the block selection signal is low and this block is selected, the spare main word line RMW goes high and enters the selected state.

The sixth embodiment of the present invention shown in FIG.
This corresponds to a transistor obtained by changing the polarity of the transistor used in the fifth embodiment. That is, the P-channel transistors P51 to P53 provided in each of the normal main word lines NMW1 to NMW128 in the fifth embodiment and the block common line R
51, N-channel transistors N61 to N63, respectively.
And a P-channel transistor P61. Further, an inverter IN62 is provided between the block common line R61 and one input terminal of the NOR circuit NOR61. The operation of the sixth embodiment is similar to that of the fifth embodiment. Normal main word lines NMW1 to 128
Is defective, and the defective row is selected, all of the normal main word lines NMW1 to NMW128 are in a non-selected state at a high level, and the block common line R61
Is charged by the P-channel transistor P61. When this block is selected, the spare main word line RMW
Becomes low level and becomes selected.

In the first to sixth embodiments, when a normal normal main word line NMW is selected, the transistor connected to the selected word line NMW and the transistor connected to the selected word line NMW share the same block. The normally-on transistors connected to the lines R11 to R61 are simultaneously turned on, and a through current flows from the power supply voltage VDD terminal to the ground voltage Vcc terminal. However, since this through current flows through only one selected block, the influence is sufficiently small in view of the current consumption during the operation of the entire device.

Further, for example, in the second embodiment shown in FIG. 2, the block common line R21 is connected to the P-channel transistor P
If it is attempted to drive with N21 and N-channel transistor N22, the delay time may be long. However, if the driving capabilities of the transistors P21 and N22 are set to be high, the above-described increase in the through current is caused. Therefore, instead of driving the spare main word line RMW with a one-stage NAND circuit, the number of stages is increased by providing an inverter IN61 as in the sixth embodiment shown in FIG.
It is possible to greatly reduce the load capacity of the block common line R61 and increase the speed.

In each of the first to sixth embodiments, the configuration in one block is shown. The whole apparatus can be configured as shown in FIG. 7, for example.

In one block B1, 128 normal main word lines NMW and one spare main word line RMW are provided. Eight such blocks are provided as a whole, and the number of main word lines NMW is usually 1024 and the number of spare main word lines RMW is eight.

In the conventional device shown in FIG. 12, eight spare main word lines RMW and 1024 normal main word lines NMW are provided in separate areas, but the device shown in FIG. As described above, the whole is divided into a plurality of blocks, and one spare main word line is arranged in each block together with the normal main word line NMW.

Further, unlike the conventional device, a circuit (normal row / spare row) for performing the control described with reference to FIGS. 1 to 6 instead of the spare word line buffer is provided at the end of spare main word line RMW. A control circuit). A further significant feature compared to the conventional circuit of FIG. 12 is that a spare row decode signal for storing a spare row decode signal and address information for generating the spare row decode signal, which is required conventionally, must be arranged using a fuse or the like. There is no.

The circuit of the embodiment in which the redundant circuit is formed in the row direction has been described above, but the redundant circuit can be similarly provided in the column direction.

First, as shown in FIG. 8, the entire circuit is divided into N sections SEC81 to SEC8 in the column direction.
If it is divided into N and each section SEC is provided with M columns, there will be M × N columns in total.

FIG. 9 shows a configuration of a semiconductor memory device according to a seventh embodiment of the present invention in the column direction. A memory cell array (not shown) is divided into a plurality of blocks in the column direction, and FIG. 9 shows a configuration in one block. In the seventh embodiment, only one I / O is included in one block.

The end portions of the bit line pairs BL and / BL for N columns connecting the memory cell array regions in the column direction are connected to N column gates CG1201 to CG120N, and the column gates CG1201 to CG120N are sense amplifiers. And a common bit line pair C to the write circuit SAW1201.
They are connected by BL and / CBL. Column gates CG1201 to CG1201
A normal and spare column control buffer NSCB1201 for controlling the operation state of the CG 120N is provided.

Normal and spare column control buffer NSCB
Reference numeral 1201 denotes a corresponding column decode line C among column decode lines CD1 to CDN provided corresponding to N columns.
A column decode signal is input from D, and a block decode signal for selecting a block is further input to operate. And a normal and spare column control buffer NSCB
The control signal output from 1201 is the column gate CG
1201 and CG 120N to control the open / close state.

Normal and spare column control buffer NSCB
In 1201, a defective column isolation fuse FU120 is provided between the column decode line CD1 and the column gate control lines CGC1201 and CGC120N connecting the column gates CG1201 and CG120N.
1 and FU120N, and N of normally on
The channel transistors N1201 and N120N are respectively connected.

The block decode line BDL is connected to one input terminal of an AND circuit AND1201. A
The other input terminal of the ND circuit AND1201 includes an N-channel transistor N1211 having a gate connected to the column gate control line CGC1201 and a source grounded, and an N-channel transistor N121N also having a gate connected to the column gate control line CGC120N. Are connected to the drains of normally N-channel P-channel transistors P1201. The output terminal of the AND circuit AND1201 is connected to the control terminal of the column gate CG1211. The column gate CG1211 has input terminals connected to the common bit line pair CBL and / CBL, respectively.
The output terminal is connected to the bit line pair BL, / BL in the spare column.

The present embodiment having such a configuration operates as follows. If none of the N normal columns 1 to N has a defect, or if another column is selected even if a defect exists, one of the column gates CG is selected by the column decode signals CD1 to CDN. To conduct.

The column gate CG is, for example, as shown in FIG.
Alternatively, the configuration as shown in FIG. The column gate CG in FIG. 10A is formed of an N-channel transistor, and the common bit line pair CB
N-channel transistors N1301 and N1302 are connected between L and / CBL and the bit line pair BL and / BL, respectively, and their gates are connected to a column gate control line CGC. When the column gate control line CGC is at a high level, the transistors N1301 and N1302 conduct,
The common bit line pair CBL, / CBL and the bit line pair BL, /
BL are connected to each other.

The column gate CG shown in FIG.
Are common bit lines CBL, / CBL and bit line pair BL,
/ BL between N-channel transistors N1
303 and a P-channel transistor P1301, and an N-channel transistor N1304 and a P-channel transistor P1302 are connected in parallel. The gates of the N-channel transistors N1303 and N1304 are commonly connected to a column gate control line CGC, and the gates of the P-channel transistors P1301 and P1302 are commonly connected to the output terminal of the inverter IN1301. The output terminal of the inverter IN1301 is connected to the column gate control line CG
It is connected to C. Similarly to the column gate CG of FIG. 10A, when the column gate control line CGC goes high, the transistors N1303, N1304, P1301, and P1302 conduct, and the column gate CG shown in FIG. Common bit line pair CBL, / CBL
And bit line pair BL, / BL are connected to each other.

Next, for example, when there is a defect in the normal column 1 and the defective column isolation fuse FU1201 is blown, the spare column is replaced as follows. When the fuse FU1201 is blown, the column gate control line CGC1201 of column 1 is always at the low level, and the column gate CG1201 is kept closed. When the column gate control line CGC1201 becomes low level,
Since the N-channel transistor N1211 is turned off and the P-channel transistor P1201 is turned on, one input level to the AND circuit AND1201 becomes a high level. When this block is selected, since the block decode signal is at a high level, this signal is applied to the other input terminal of the AND circuit AND1201 and AND
A high-level output is supplied from the circuit AND1201 to the column gate CG1211. As a result, the column gate CG1211 is opened, and the common bit lines CBL, / C
BL and the pair of bit lines BL and / BL in the spare column are connected to each other, and defects are relieved.

FIG. 11 shows the configuration of one block in the column direction of a semiconductor memory device according to the eighth embodiment of the present invention. In this embodiment, one block includes an I / O having N normal columns.
Eight Os (I / O1 to I / O8) and one extra row are provided. Also, corresponding to eight I / Os,
Sense amplifier and write circuits SAW1401-140
8 are provided. One normal and spare column control buffer NSCB 1401 is provided for one block, and each I / O has the same configuration as the normal and spare column control buffer NSCB 1201 shown in FIG. 9 for each I / O.
We prepare for every.

When a normal column is selected in all I / O1 to I / O8, one of N columns is selected for each I / O, and the corresponding column gate CG is opened. The common bit line pair CBL, / CBL is connected to the bit line pair BL, / BL.

When a defective column is selected in any one of I / O1 to I / O8, the operation is as follows. For example, if the column 1 in the I / O1 is defective and the fuse FU1401 is blown, this column 1
Of the column decode line CD
The closed state is maintained regardless of the level of 1. When the column gate control line CGC1401 of the column 1 is held at a low level, the N-channel transistor N1401 is turned off and the P-channel transistor P1401 is in an on state, so that a high-level signal is output from the AND circuit AND140.
1 is input to one of the input terminals. When this block is selected, the high-level block decode signal
Given to the other input terminal of the ND circuit AND1401,
A high-level output is applied to the column gate CG1411 to conduct. Thereby, common bit line pair CBL, / C
BL and the pair of bit lines BL and / BL in the spare column are electrically connected to each other to be relieved.

According to the above-described embodiment, the following effects can be obtained.

When a redundant circuit is provided in either the row direction or the column direction, neither a spare row decoder nor a spare column decoder is required. Therefore, it is possible to contribute to the reduction of the chip area. As described above, in the case of a 1M-bit SRAM of 1024 rows × 1024 columns with an 8-bit configuration, the area of the spare row decoder per spare row is as follows.
It is about 20,000 μm ² . Therefore, when eight spare rows are provided, a total area of about 160000 μm ² is required. According to the first to sixth embodiments, such an area can be reduced.

Further, the number of steps for blowing the fuse can be reduced. In either case where redundancy is provided in the row or column direction, it is not necessary to blow a fuse to store a defective address. Only the defective row or defective column isolation fuse needs to be blown, and the manufacturing cost can be reduced.

As described above with reference to Table 1, in the case of a 1M-bit SRAM having eight spare rows, conventionally, a maximum of 96 fuse blows were required. On the other hand,
According to the sixth embodiment, it is sufficient to blow up to eight times.

In the column direction, as shown in Table 2, 1M
In the case of a bit SRAM having eight spare columns, it has conventionally been necessary to blow a maximum of 64 times. On the other hand, in the seventh or eighth embodiment, it is sufficient to blow eight times at the maximum.

In designing the circuit, the first to eighth embodiments provide an effect that the required increase or decrease of the memory cell array is simpler than the conventional case.

According to the first to sixth embodiments, for example, 12
One block is composed of eight normal rows and one spare row.
Alternatively, according to the eighth embodiment, 1 in 128 normal rows and 1 spare row
One block is composed. By increasing or decreasing such a block as one unit, it is possible to easily change the required scale of the memory cell array as a whole. Thereby, the development period of the on-chip memory in the standard cell or the like can be reduced.

The above-described embodiments are merely examples, and do not limit the present invention. For example, the number of a plurality of normal rows or normal columns provided in one block may be an arbitrary number of 2 or more. In the case where there is a defect in the normal row or the normal column, the normal row or the normal column is set to the non-selection state by using the fuse for isolation in the embodiment, but the defective normal row selection line or the normal column selection is used. Other means for electrically disconnecting the line from the selection means may be used instead.

[0111]

As described above, according to the semiconductor memory device of the present invention, a plurality of normal rows and one spare row, or a plurality of normal columns or one spare column are provided in each of a plurality of blocks. If any of the normal rows or the normal columns has a defect, the defective normal row or the normal column is deselected. Further, when the block is selected and the normal row or the normal column is selected, all the normal rows or the normal columns are in a non-selected state. In such a case, the spare row or spare column is automatically selected. For this reason, a decoder for selecting any of the spare row or spare column is not required, the chip area is reduced, and a step of storing information for selecting the spare row or spare column is also unnecessary, and the number of manufacturing steps is reduced. Decrease.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a schematic configuration of a semiconductor memory device according to first to sixth embodiments of the present invention.

FIG. 8 is an explanatory diagram showing a configuration of a semiconductor memory device according to a seventh or eighth embodiment of the present invention in the column direction.

FIG. 9 is a circuit diagram showing a configuration of a semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of a column gate of a semiconductor memory device according to a seventh or eighth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of a semiconductor memory device according to an eighth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a schematic configuration of a conventional semiconductor memory device.

FIG. 13 is a circuit diagram showing a configuration of an address decoder in the semiconductor memory device.

FIG. 14 is a circuit diagram showing a configuration of a spare row decoder in the semiconductor memory device.

FIG. 15 is a circuit diagram showing a configuration of a fuse selection circuit in the semiconductor memory device.

FIG. 16 is a circuit diagram showing a configuration in a row direction in the semiconductor memory device.

FIG. 17 is a circuit diagram showing a configuration of another conventional semiconductor memory device in a row direction.

FIG. 18 is a circuit diagram showing a configuration of another conventional semiconductor memory device in a row direction.

FIG. 19 is a circuit diagram showing a configuration in a row direction in another conventional semiconductor memory device.

FIG. 20 is a circuit diagram showing a configuration of another conventional semiconductor memory device in a column direction.

FIG. 21 is a circuit diagram showing a configuration of another conventional semiconductor memory device in a column direction.

FIG. 22 is a circuit diagram showing a configuration of a circuit for generating a control signal in the semiconductor memory device.

[Explanation of symbols]

NMW1 to NMW128 Normal main word line RMW Spare main word line IN11, IN12, IN21, IN22, IN31,
IN32, IN41, IN42, IN51, IN52,
IN61 to IN64 Inverters NOR11, NOR31, NOR51, NOR61 N
OR circuit RMD11, RMD21, RMD31, RMD41, R
MD51, RMD61, RMD71 Low main decoder NA21, NA71 NAND circuit WB Word line buffer FU11, FU21, FU31, FU41, FU51,
FU61, FU71 Defective low isolation fuse FU1201, FU1301, FU1401 Defective column isolation fuse R11, R21, R31, R41, R51, R61 Block common line CD71 Column decoder SD71 Section decoder SEC81-SEC8N Section CG1201, CG120N, CG1211, CG14
01, CG140N, CG1411 Column gate SAW1201, SAW1401, SAW1408 Sense amplifier and write circuit CD1 to CDN Column decode line AND1201, AND1401 AND circuit CBL, / CBL Common bit line pair CGC1201, CGC120N, CGC1401, C
GC140N Column gate control line NSCB1201, NSCB1401 Normal and spare column control buffer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 29/00 G11C 11/401 H01L 21/82

Claims (2)

(57) [Claims] 1. A semiconductor device comprising: a plurality of normal rows; and a plurality of blocks each having a memory cell arranged in one spare row, wherein each of the blocks includes a plurality of normal row selection lines for selecting any of the normal rows. One spare row selection line for selecting the spare row in place of a defect in any of the normal rows, and driving a corresponding normal row selection line provided for each of the normal row selection lines, A normal row selection control circuit including a disconnection fuse for disconnection when there is a defect in the normal row selection line; and a spare row selection control provided on the spare row selection line for driving the spare row selection line. And each of the normal row selection control circuits drives the normal row selection line to a selected state when the normal row is selected, based on an output of the row decoder, and when the normal row is not selected, Deselect the normal row selection line Driving means for driving to a selected state, and a first potential setting for setting the potential of the blown fuse terminal to a non-selection potential given when the normal row is not selected when the defective fuse is cut off. Means, provided for each normal row, given the potential of the fuse terminal of the normal row, and one common terminal provided in common for each normal row, the first common terminal is selected when the normal row is selected. A second potential setting means for performing an operation of setting to the first potential, and not performing an operation of setting to the first potential when the normal row is not selected; and And a third potential setting means for performing an operation of setting the potential to the potential. The driving capability of the second potential setting means for setting the common terminal to the first potential is determined by the third potential setting means. Setting the common terminal to the second potential The spare row selection control circuit is provided with a block selection signal for selecting one of the blocks and the potential of the common terminal, the block is selected, and the common terminal is A driving means for driving the spare row selection line to a selected state only when the potential is 2 and driving the spare row selection line to a non-selected state in any other case. Semiconductor storage device. 2. A semiconductor device comprising: a plurality of normal columns; and a plurality of blocks each having memory cells arranged in one spare column, wherein each of the blocks includes a plurality of normal column selection lines for selecting one of the normal columns. A spare column selection line for selecting the spare column in place of a defect in any of the normal columns, and a corresponding normal column selection line provided for each of the normal column selection lines, A normal column selection control circuit including a fuse for disconnection when a failure occurs in the normal column selection line, and a spare column selection control provided on the spare column selection line and driving the spare column selection line Each of the normal column selection control circuits drives the normal column selection line to a selected state when the normal column is selected based on an output of a column decoder, and when the normal column is not selected, Deselect the normal column selection line Driving means for driving to a selected state, and a first potential setting for setting the potential of the blown fuse terminal to a non-selection potential applied when the normal column is not selected when the defective fuse is cut off Means, provided for each of the normal columns, provided with the potential of the fuse terminal of the normal column, and one common terminal provided in common for each of the normal columns. A second potential setting means for performing an operation of setting to the first potential, and not performing an operation of setting to the first potential when the normal column is not selected; and And a third potential setting means for performing an operation of setting the potential to the potential. The driving capability of the second potential setting means for setting the common terminal to the first potential is determined by the third potential setting means. Setting the common terminal to the second potential The spare column selection control circuit is provided with a block selection signal for selecting any of the blocks and the potential of the common terminal, the block is selected, and the common terminal is connected to the second terminal. A driving unit that drives the spare column selection line to a selected state only when the potential is 2 and drives the spare column selection line to a non-selected state in any other case. Semiconductor storage device.