KR100925474B1 - Methods for manufacturing thin film transistor panels for liquid crystal display - Google Patents

Abstract

A gate wiring including a gate line, a gate electrode, and a gate pad is formed on the insulating substrate. Next, a gate insulating film covering the gate wiring is formed, and then a semiconductor pattern is formed on the gate insulating film of the gate electrode. Subsequently, a data line including a data line, a source electrode, a drain electrode, and a data pad is formed on the semiconductor pattern or the gate insulating layer. Subsequently, a protective film covering the data line and the semiconductor pattern is applied, and then a portion of the protective film is removed to form a first contact hole exposing the drain electrode. Subsequently, the protective film is subjected to plasma treatment using Cl 2 / O 2 or HCl / O 2 gas, and then dry cleaning using O 2 plasma or wet cleaning using an etching solution containing HNO 3, such as an etching solution of Al or Cr. Next, a pixel electrode connected to the drain electrode exposed through the first contact hole is formed.

Plasma, dry cleaning, wet cleaning, contact hole, organic insulating film, contact resistance

Description

The manufacturing method of the thin-film transistor board | substrate for liquid crystal display devices {METHODS FOR MANUFACTURING THIN FILM TRANSISTOR PANELS FOR LIQUID CRYSTAL DISPLAY}

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II-II 'of FIG. 1,

3A is a layout view illustrating a manufacturing process of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A.

FIG. 4A is a layout view of a thin film transistor substrate manufactured according to an embodiment of the present invention, and illustrates the next step of FIG. 3A.

4B is a cross-sectional view taken along line IVb-IVb 'of FIG. 4A.

FIG. 5A is a layout view of a thin film transistor substrate manufactured according to an embodiment of the present invention, and illustrates the next step of FIG. 4A.

5B is a cross-sectional view taken along line Vb-Vb ′ of FIG. 5A.

5C is a cross-sectional view showing the next step in FIG. 5B.

FIG. 6A is a layout view of a thin film transistor substrate manufactured according to an embodiment of the present invention, and illustrates the next step of FIG. 5A.

FIG. 6B is a cross-sectional view taken along line VIb-VIb ′ of FIG. 5A;

7 is a graph showing the etching characteristics of chromium according to the amount of O 2,

8 is a graph showing the change in transmittance according to the wavelength of the visible light region,

9A is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 9B is a cross-sectional view taken along line VIIb-VIIb 'of FIG. 9A;

10A is a layout view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 10B is a sectional view taken along the line VIIb-VIIb 'of FIG. 10A,

11A is a layout view schematically illustrating a structure of a thin film transistor substrate for a liquid crystal display according to a fourth exemplary embodiment of the present invention.

11B and 11C are cross-sectional views taken along the lines Ib-XIb 'and VIc-XIC' of FIG. 11A,

12A is a layout view illustrating a process of manufacturing a thin film transistor substrate for a liquid crystal display according to a fourth embodiment of the present invention;

12B and 12C are cross-sectional views taken along lines XIIb-XIIb 'and XIIc-XIIc of FIG. 12A, and

13A and 13B are cross-sectional views illustrating the next steps of FIGS. 12B and 12C, respectively;

FIG. 14A is a layout view of a thin film transistor substrate showing the next step of FIG. 13A;

14B and 14C are cross-sectional views taken along line XIVb-XIVb 'and XIVc-XIVc' in FIG. 14A, respectively.

15A, 16A, 17A and 15B, 16B, and 17B are cross-sectional views taken along the lines IVB-XIVb 'and XIVC-XIVc' in Fig. 14A, respectively, illustrating the next steps of Figs. 14B and 14C;

FIG. 18A is a layout view of a thin film transistor substrate showing the next step of FIG. 17A;

18B and 18C are cross-sectional views taken along the lines 'b-'b' and 'c-'c', respectively, in FIG. 18A.

The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. Device to display an image by adjusting the amount of transmitted light.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is one of the liquid crystal display devices. Data lines, gate pads, and data pads are formed, and the other substrates are generally formed with a color filter, a black matrix, and a common electrode on the front surface.

In manufacturing such a liquid crystal display device, an insulating interlayer is formed between a wiring and a wiring or a wiring and an electrode by using silicon oxide (SiO 2) or silicon nitride (SiNx) to insulate the conductive wiring from each other. The coupling capacity is so large that recently, organic insulating films having low dielectric constants such as benzocyclobutene (BCB), perfloucyclobutene (PFCB), and acrylic resin (acryl) are often used to realize high opening ratios of thin film transistors. Since the organic insulating film has photosensitivity, it is not necessary to use a separate photosensitive film, and the process of etching the protective film can be omitted, thereby simplifying the process.

However, since the organic insulating film is relatively softer than the silicon nitride film or the like, the film material tends to remain in the contact hole when patterning the contact hole to expose the pad, resulting in a high contact resistance of the contact portion.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a thin film transistor substrate for a liquid crystal display device capable of stably securing a contact resistance of a contact portion.

In order to achieve this object, in the present invention, the plasma treatment is performed using a gas containing Cl 2 / O 2 or HCl / O 2, followed by dry cleaning using an O 2 plasma or an etching solution containing HNO 3, such as an etchant of Al or Cr. Wet cleaning is used to remove impurities remaining in the contact holes.

According to an embodiment of the present invention, a gate wiring including a gate line, a gate electrode, and a gate pad is formed on an insulating substrate. Next, a gate insulating film covering the gate wiring is formed, and a semiconductor pattern is formed on the gate insulating film of the gate electrode. Subsequently, a data line including a data line, a source electrode, a drain electrode, and a data pad is formed on the semiconductor pattern or the gate insulating layer. Subsequently, a protective film covering the data line and the semiconductor pattern is applied, and then a portion of the protective film is removed to form a first contact hole exposing the drain electrode. Subsequently, the protective film is subjected to plasma treatment using Cl2 / O2 or HCl / O2 gas, and then at least one of dry cleaning using O2 plasma or wet cleaning using an etchant containing HNO 3, such as an etchant of Al or Cr, is performed. do. Next, a pixel electrode connected to the drain electrode exposed through the first contact hole is formed.

In this case, the protective film may be formed of an inorganic insulating material such as silicon oxide or silicon nitride, or an organic insulating material such as BCB (benzocyclobutene) or acrylic resin (acryl).

In this case, the passivation layer has second and third contact holes exposing the data pad and the gate pad, respectively, and the auxiliary data pad and the auxiliary gate pad connected to the data pad and the gate pad through the second and third contact holes, respectively. It may further comprise the step of forming.

In this case, the method may further include forming a black matrix and a color filter on the insulating substrate, and forming an insulating layer covering the black matrix and the color filter.

In this case, the method may further include forming a chromium film on or below the gate wiring and the data wiring.

In this case, the data line, the contact layer pattern, and the semiconductor pattern may be formed by a photolithography process using one photoresist pattern.

Here, the photoresist pattern may be formed using one mask.

Then, a thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same according to the first embodiment of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily practice the present invention. It explains in detail.

First, the structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 2.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1, respectively.

1 and 2, the lower layer 220, 240, and 260 made of an aluminum-based conductive material such as Al-Nd having high resistance on the insulating substrate 10 have excellent contact characteristics with other materials. Gate wirings 22, 24, and 26 are formed to include upper layers 221, 241, and 261 made of chromium (Cr), molybdenum (Mo), and the like. The gate wirings 22, 24, and 26 are connected to the gate lines 22 extending in the horizontal direction, the gate pads 24 connected to the ends of the gate lines 22 to receive gate signals from the outside, and to transfer the gate signals to the gate lines. And a gate electrode 26 of the thin film transistor connected to the gate line 22.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiNx) covers the gate wirings 22, 24, and 26, and the gate insulating film 30 is formed along with a protective pad 70 formed thereafter. It has a contact hole 74 that exposes 24.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 30 of the gate electrode 24, and n + is doped with silicide or n-type impurities at a high concentration on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as hydrogenated amorphous silicon are formed, respectively.

On the resistive contact layers 55 and 56 and the gate insulating layer 30, such as the gate wirings 22, 24 and 26, chromium (Cr), which is a material having low resistance and a material having excellent contact properties with other materials, or Data wirings 62, 65, 66, 68 containing molybdenum (Mo) and the like are formed. The data lines 62, 65, 66, and 68 are formed in the vertical direction and are connected to the data line 62 and the data line 62, which cross the gate line 22 to define a unit pixel, and are connected to the ohmic contact layer 55. Is connected to one end of the source electrode 64 and the data line 62 extending up to the upper part of the circuit board, and is separated from the data pad 68 and the source electrode 64 to which an image signal from the outside is applied. And a drain electrode 66 formed over the ohmic contact layer 56 opposite the source electrode 64.

It is an organic insulating material having a low dielectric constant of 3.0 or less, such as bisbenzocyclobutene (BCB) or perfluorocyclobutene (PFCB), and the like, having excellent heat resistance of 300 ° C. or higher on the data lines 62, 65, 66, and 68, and the semiconductor layer 40 which is not covered by these. And a planarized protective film 70 is formed. In this case, the passivation layer 70 has contact holes 76 and 78 exposing the drain electrode 66 and the data pad 68, and the contact exposing the upper layer 241 of the gate pad together with the gate insulating layer 30. It has a hole 74. The passivation layer 70 may include an insulating layer made of an inorganic insulating material such as silicon oxide (SiO 2) or silicon nitride (SiN x).

The pixel electrode 82 and the contact holes 74 and 78 positioned in the pixel are electrically connected to the drain electrode 66 through the contact hole 76 on the passivation layer 70, respectively. An auxiliary gate pad 86 and an auxiliary data pad 88 electrically connected to the first electrode 68 are formed, and a conductive film pattern made of indium tin oxide (ITO) or indium zinc oxide (IZO) is formed.

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate lines 22, 24, and 26. It is also possible to add a storage capacitor wiring.

Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 3A to 8.

First, as shown in FIGS. 3A and 3B, the lower layers 220, 240, and 260 of Al-Nd and the upper layers 221, 241, and 261 of chromium are sequentially stacked on the insulating substrate 10, and a mask is used. Patterning is performed by a photolithography process to form a horizontal gate line including the gate line 22, the gate pad 24, and the gate electrode 26.

Next, as shown in FIGS. 4A and 4B, the gate insulating film 30, the semiconductor layer 40, and the ohmic contact layer 50 are deposited by chemical vapor deposition, respectively, and patterned by a photo process using a mask. The semiconductor layer 40 and the ohmic contact layer 50 are formed on the gate insulating layer 30 facing the electrode 26.

Next, as illustrated in FIGS. 5A to 5B, a conductive film made of aluminum or an aluminum alloy or molybdenum or molybdenum alloy or chromium is laminated, and patterned by a photo process using a mask to cross the gate line 22 to form a matrix. A data line 62 defining a pixel of the pixel, a source electrode 65 connected to the data line 62 and extending to an upper portion of the gate electrode 26, and a data pad 68 connected to one end of the data line 62. ) And data lines 62, 65, 66, and 68 that are separated from the source electrode 65 and include a drain electrode 66 facing the source electrode 65 with respect to the gate electrode 26.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed.

Next, as shown in Fig. 5C, a protective film 70 made of an organic insulating film is applied. Although the protective film 70 was formed using the photosensitive material here, it can also apply | coat as a non-photosensitive material. Alternatively, the protective film 70 may be formed by laminating an insulating film such as a silicon oxide film (SiO 2) or a silicon nitride film (SiN x).

Next, as shown in FIG. 6B, the protective film 70 is exposed and developed to form contact holes 76 and 78 exposing the drain electrode 66 and the data pad 68. In addition, the gate insulating layer 30 is etched to form a contact hole 74 exposing the upper layer 241 of the gate pad 24. At this stage, some of the organic insulating material remains inside the contact holes 74, 76, 78.

Subsequently, the protective film 70 is subjected to plasma treatment using a gas containing Cl 2 / O 2 or HCl / O 2. In this case, a portion of the chromium film exposed through the contact holes 74, 76, and 78 may be etched. Then, dry cleaning using an O 2 plasma or wet cleaning using an etching solution containing HNO 3, such as an etching solution of Al or Cr, is performed. As a result, the contact resistance of the contact portion may be reduced by removing the organic insulating material remaining in the contact holes 74, 76, and 78. At this time, the surface roughness of the protective film 70 is increased to improve the adhesion between the transparent conductive film formed in a later step and the protective film 70.

Next, as shown in FIG. 2, the ITO film is laminated and patterned using a mask to form the pixel electrodes 82 and the contact holes 74 and 78 connected to the drain electrode 66 through the contact holes 76. The auxiliary gate pad 86 and the auxiliary data pad 88 connected to the gate pad 24 and the data pad 68, respectively, are formed therethrough.

Next will be described an experimental example that can support the effect according to the embodiment of the present invention.

Experimental Example 1

Experimental Example 1 will be described with reference to Figure 7 and Table 1 for the etching characteristics of the chromium (Cr) according to the change of the O2 flow rate during the plasma treatment.

FIG. 7 is a graph showing the etching ratio, etching uniformity, and photoresist loss of chromium (Cr) according to the change of O 2 flow rate, and Table 1 is a graph showing the numerical values of the graph of FIG. 7.

In Experimental Example 1, the high frequency (radio frequence) source power is 1800W, the pressure is 300mT, the interval between the upper electrode and the lower electrode of the installation is 60mm, Cl2 gas flow rate is 400 Sccm, the flow rate of O2 gas is 100 to The etching rate, etching uniformity and loss of photoresist of Cr were measured while changing in the range of 300 Sccm. In the figure, 은 is the etching rate (E / R) of Cr, the unit is Å / min, 은 is the etch uniformity of Cr, the unit is%, and ● is the loss amount of the photoresist film (P.R).

As shown in Table 1 and FIG. 7, the etching ratio of Cr according to the O2 flow rate in the range of 100 Sccm to 300 Sccm is in the range of 340 kW / min to 540 kW / min, and the etching uniformity of Cr is in the range of 8.0% to 14.5%, The loss of the photoresist was measured in the range of 1620Å to 2870Å. Within this range, as the amount of O 2 increases, the loss of the photoresist film increases, but it does not significantly affect the formation of the pattern, and it can be seen that the etching ratio and the etching uniformity of Cr are almost constant. Through these results, it can be seen that the etching ratio and etching uniformity of Cr can be controlled by performing plasma treatment by appropriately adjusting the O 2 flow rate.

O ₂ flow rate (Sccm) 100 150 200 250 300 Cr etching ratio (비 / min) 346 446 500 540 539 Uniformity (%) 14.4 9.0 8.3 10.0 - Photoresist loss 1623 2680 2869 - -

Experimental Example 2

In Experimental Example 2, a contact resistance according to whether dry cleaning or wet cleaning is performed after the plasma treatment will be described with reference to Table 2.

Table 2 shows the contact parts according to whether 200 cleaning parts were formed to perform plasma treatment using Cl2 / O2 gas, followed by dry cleaning using O2 plasma or wet cleaning using an etchant containing HNO 3, such as an etchant of Al or Cr. The contact resistance of is measured.

As shown in Table 2, when one or more of dry cleaning or wet cleaning is performed after plasma treatment as in conditions 1 to 3, the contact resistance of the contact is in the range of 105 to 107, and after plasma treatment as in condition 4 When dry and wet cleaning are not performed, it can be seen that the contact resistance of the contact portion is in the range of 1010 to 1011. In particular, when only wet cleaning is performed after plasma treatment as in condition 1, it can be seen that the contact resistance of the contact portion decreases to 105 levels. The contact resistance is reduced by performing plasma treatment using Cl2 / O2 gas and then performing one or more of dry cleaning using O2 plasma or wet cleaning using an etchant containing HNO3 such as an Al or Cr etchant. It can be seen.

Treatment condition Contact resistance of the point Dry cleaning Wet cleaning R1 R2 R3 R4 R5 Average resistance Condition 1 No progress Progress 2.41 ㅧ 10 ⁵ 7.18 ㅧ 10 ⁵ 1.29 ㅧ 10 ⁶ 6.09 ㅧ 10 ⁵ 5.04 ㅧ 10 ⁵ 6.7 ㅧ 10 ⁵ Condition 2 Progress No progress 9.65 ㅧ 10 ⁶ 1.02 ㅧ 10 ⁷ 3.46 ㅧ 10 ⁷ 3.48 ㅧ 10 ⁷ 2.16 ㅧ 10 ⁷ 2.22 ㅧ 10 ⁷ Condition 3 Progress Progress 1.12 ㅧ 10 ⁷ 1.19 ㅧ 10 ⁷ 2.29 ㅧ 10 ⁷ 1.52 ㅧ 10 ⁷ 1.37 ㅧ 10 ⁷ 1.49 ㅧ 10 ⁷ Condition 4 No progress No progress 10 ¹⁰ -10 ¹¹ 10 ¹⁰ -10 ¹¹ 10 ¹⁰ -10 ¹¹ 10 ¹⁰ -10 ¹¹ 10 ¹⁰ -10 ¹¹ 10 ¹⁰ -10 ¹¹

Experimental Example 3

In Example 3, the influence of the display characteristics such as the transmittance of the liquid crystal display according to the plasma treatment on the protective film using Cl 2 / O 2 gas will be described with reference to FIG. 8.

Example 3 is a graph showing a change in transmittance according to the wavelength region of visible light. Here, ◆ assumes a transmittance at 100 which is not subjected to the plasma treatment, and # is a transmittance as a relative value of Condition 1 to Condition 3 in Example 2 with respect to the condition which is not subjected to the plasma treatment.

As shown in FIG. 8, in the implementation according to the conditions 1 to 3, the decrease in the transmittance in the visible light wavelength region is not large, and as the wavelength is shortened and approaches the ultraviolet wavelength region, the decrease in the transmittance becomes larger and the wavelength becomes longer and the infrared wavelength is increased. As it approaches the area, it can be seen that the decrease in transmittance is greatly reduced. Through this process, plasma treatment using Cl2 / O2 or HCl / O2 gas in the protective film, followed by dry cleaning using O2 plasma or wet cleaning using an etchant containing HNO3, such as an etching solution of Al or Cr, transmittance in the visible region It can be seen that display characteristics such as do not deteriorate significantly.

As described above, the method for manufacturing a thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention includes dry cleaning or HNO 3 using O 2 plasma after plasma treatment using Cl 2 / O 2 or HCl / O 2 gas. Wet cleaning using an etchant may reduce the contact resistance of the contact portion by removing the organic insulating material remaining in the contact holes 74, 76, and 78.

On the other hand, the thin film transistor substrate for a liquid crystal display device may form a color filter together with the thin film transistor. This will be described in detail with reference to the drawings.

First, a structure and a manufacturing method of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 9A and 9B.

FIG. 9A is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 9B is a cross-sectional view taken along the line VII-b 'of FIG. 9A.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a second embodiment of the present invention will be described with reference to FIGS. 9A and 9B.

The structure of the thin film transistor substrate for a liquid crystal display according to the second embodiment of the present invention is also substantially the same as that of the first embodiment.

However, as shown in FIGS. 9A and 9B, a black matrix including a single layer or a multilayer layer including copper, aluminum, or chromium or molybdenum, chromium nitride, molybdenum nitride, or the like on the lower insulating substrate 10. 152 is formed. The black matrix 152 has an opening in a matrix pixel, and is formed in a mesh shape, and blocks light leaking between the pixels, and subsequently enters light incident into the semiconductor layer 40 of the thin film transistor. It may have a modified form to block. In this case, although not shown in the embodiment of the present invention, a gate pad and a data pad may be formed on the same layer as the black matrix to transmit scan signals and image signals from the outside to gate lines and data lines formed later.

In the upper pixel of the lower insulating substrate 10, red (R), green (G), and blue (B) color filters 160 whose edge portions cover the black matrix 152 are formed, respectively. Here, the color filter 160 may be formed to overlap each other on the black matrix 152, and it is preferable to use a material whose color characteristics do not change due to the manufacturing temperature of the thin film transistor of 350 ° C. or higher.

The organic insulating layer 170 is formed on the black matrix 152 and the color filter 160 by a material having excellent dielectric constant and heat resistance such as BCB or PFCB.

The manufacturing method of the thin film transistor substrate for a liquid crystal display according to the second embodiment of the present invention having the structure is almost the same as the manufacturing method according to the first embodiment described above.

However, the conductive material is deposited by a method such as sputtering and dry or wet etching by a photolithography process using a mask to form a black matrix 152 on the lower insulating substrate 10.

Here, the conductive material is formed of a multilayer film including a conductive material having a low resistance, such as aluminum or an aluminum alloy or a copper or a copper alloy, or a silver series, or chromium or molybdenum or titanium having excellent contact characteristics with ITO, or a chromium nitride having low reflectivity. It is desirable to.

In this case, the gate pad 24 and the data lines 62, 65, 66, and 68 may be formed on the same layer as the black matrix 152.

Subsequently, a photosensitive material including pigments of red, green, and blue is sequentially applied and patterned by a photo process using a mask to sequentially form the red, green, and blue color filters 160. In this case, the photosensitive material is preferably a heat-resistant material that does not change the color characteristics even at temperatures higher than 350 ℃, red, green, blue color filter 160 is formed using three masks, but to reduce the manufacturing cost It is also possible to form by using while moving the mask. In addition, using a laser transfer method or a print method can be formed without using a mask, thereby minimizing the manufacturing cost. In this case, as shown in the figure, the edges of the color filters 160 of red, green, and blue may be formed to overlap the black matrix 152.

Next, the organic insulating layer 170 is formed on the lower insulating substrate 10 by using an organic material such as BCB or PFCB having excellent heat resistance and planarization characteristics of 350 ° C. or higher.

Also in the method for manufacturing a thin film transistor substrate for a liquid crystal display device according to a second embodiment of the present invention using a gas containing Cl2 / O2 or HCl / O2 in the protective film 70 made of an organic insulating film after the plasma treatment using the O2 plasma Dry cleaning or wet cleaning using an etchant of Al, Cr, HNO 3 is performed to remove the organic insulating material remaining in the contact holes 74, 76, and 78. This reduces the contact resistance of the contacts. At this time, the surface roughness of the protective film 70 increases, which may improve the adhesion between the transparent conductive film and the protective film 70 formed in a later process.

According to the second embodiment of the present invention, not only the same effect as the first embodiment of the present invention but also the two substrates by forming the color filter 160 and the black matrix 152 together with the thin film transistors on the thin film transistor substrate 10. Since the alignment error between them is not taken into consideration, the aperture ratio can be improved.

Here, the color filter is formed under the thin film transistor, but the color filter may be formed over the thin film transistor. A thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same according to a third embodiment of the present invention will be described with reference to FIGS. 10A and 10B.

FIG. 10A is a layout view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention, and FIG. 10B is a cross-sectional view taken along line VII-Bb ′ of FIG. 10A.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention will be described with reference to FIGS. 10A and 10B.

The structure of the thin film transistor substrate for a liquid crystal display according to the third embodiment of the present invention is also substantially the same as that of the first embodiment.

10A and 10B, the color filters 160 of R (red), G (green), and B (blue) are alternately formed on each of the pixels on the passivation layer 70. The organic insulating layer 170 is formed on the 160. Here, contact holes 76 and 78 exposing the drain electrode 66 and the data pad 68, respectively, are formed through the organic insulating layer 170, the color filter 160, and the passivation layer 70. In addition, a contact hole 74 exposing the upper layer 241 of the gate pad 24 is formed through the organic insulating layer 170, the color filter 160, the passivation layer 70, and the gate insulating layer 30. On the color filter 160 of the pixel, a pixel electrode 82 positioned in the pixel while being electrically connected to the drain electrode 66 through the contact hole 76 is formed.

The manufacturing method of the thin film transistor substrate for a liquid crystal display according to the third embodiment of the present invention having the structure is almost the same as the manufacturing method according to the first embodiment described above.

However, a photosensitive material containing a dye is coated on the passivation layer 70, and then exposed and developed to form a color filter 160 of R (red), G (green), and B (blue).

Next, the organic insulating layer 170 is formed on the color filter by spin coating, and the organic insulating layer 170, the color filter 160, and the protective layer 70 are patterned to form the drain electrode 66 and the data pad 68. Respective contact holes 76 and 78 are formed, respectively, and the gate insulating film 30 is also patterned to form contact holes 74 that expose the upper film 241 of the gate pad 24. In this case, color filter material, organic insulating material, and the like may remain in the contact holes 76, 78, and 74. In order to prevent this, as in the first embodiment of the present invention, after plasma treatment using a gas containing Cl 2 / O 2 or HCl / O 2, dry cleaning using an O 2 plasma or HNO 3, such as an etchant of Al or Cr, is included. Wet cleaning using an etchant is performed. This step removes the organic insulating material or color filter material still remaining inside the contact holes 76, 78, 74. This can reduce the contact resistance of the contact portion. In this case, the surface roughness of the organic insulating layer 170 may be increased to improve adhesion to the pixel electrode 82.

In this embodiment of the present invention, as described above, the present invention can be applied to a manufacturing method using five masks, but can also be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to a fourth embodiment of the present invention will be described in detail with reference to FIGS. 11A to 11C.

11A is a layout view of a thin film transistor substrate for a liquid crystal display according to a fourth exemplary embodiment of the present invention, and FIGS. 11B and 11C are lines XIb-XIb 'and XIc-XIc', respectively, of the thin film transistor substrate shown in FIG. The cross section for

Similar to the first embodiment, the lower layers 220, 240, and 260 made of aluminum-based conductive materials such as Al-Nd and chromium (material having excellent contact properties with other materials) are formed on the insulating substrate 10. Gate wirings 22, 24, 26 including a gate line 22, a gate pad 24, and a gate electrode 26 made of upper layers 221, 241, and 261 made of Cr) or molybdenum (Mo) or the like. Is formed. The gate wirings 22, 24, and 26 have the same structure as the gate wirings that are parallel to the gate lines 22 on the insulating substrate 10 and receive a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 28 includes the lower layer 280 and the upper layer 281. The sustain electrode 28 overlaps the conductor pattern 68 for the sustain capacitor connected to the pixel electrode 82 to be described later to form a sustain capacitor which improves the charge retention capability of the pixel, and the pixel electrode 82 and the gate line to be described later. If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

A gate insulating film 30 made of silicon nitride (SiNx) is formed on the gate wirings 22, 24, and 26 and the storage electrode 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and silicon doped with n-type impurities such as phosphorus (P) is heavily doped on the semiconductor patterns. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 is formed.

On the ohmic contact layer patterns 55, 56, and 58, data lines 62, 64, 65, and 66 made of chromium (Cr) or molybdenum (Mo), which are materials having excellent contact properties with aluminum alloys having low resistance or other materials. , 68). The data lines 62, 64, 65, 66, and 68 are formed in the data line 62 formed in the vertical direction, the source electrode 65 of the thin film transistor which is a branch of the data line, the gate electrode 26, or the channel portion of the thin film transistor. A data pad 68 connected to one end of the drain electrode 66 and the data line 62 of the thin film transistor positioned opposite to the source electrode 65 with respect to (C) to apply an image signal from the outside; Also included is a conductor pattern 64 for a storage capacitor over the electrode 28. When the sustain electrode 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. Have exactly the same shape. That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 65 and 68, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 68 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the source electrode 65 in the channel portion C of the thin film transistor. ) And the drain electrode 66 are separated, and the data line intermediate layer 55 and the contact layer pattern 56 for the drain electrode are also separated, but the semiconductor pattern 42 of the thin film transistor is continuously connected here. Create a channel.

A passivation layer 70 made of an organic insulating material such as silicon nitride or acrylic is formed on the data lines 62, 64, 65, 66, and 68, and the drain layer 66 and the data pad 68 are formed on the passivation layer 70. And the contact holes 76, 73, and 74 that expose the aluminum-based conductive material of the conductor pattern 64 for the storage capacitor, and are in contact with the gate insulating film 30 and the gate pad 24. Has)

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (IZO) or indium tin oxide (ITO), and is held through the contact hole 76 and the drain electrode 66 through the contact hole 74. It is electrically connected to the conductor pattern 64 for the capacitor to transmit the image signal. On the other hand, the gate pad 24 and the data pad 68 are formed with auxiliary gate pads 84 and auxiliary data pads 86 connected to them through contact holes 72 and 73, respectively, which are pads 24. 68) and to protect the pads and the adhesion of the external circuit device, and is not essential, their application is optional.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 11A through 11C using four masks will be described in detail with reference to FIGS. 11A through 11C and 12A through 18C. do.

First, as shown in FIGS. 12A to 12C, Al-Nd is formed as a lower layer 220, 240, and 260, and chromium is formed as an upper layer 221, 241, and 261, and photo etching is performed using a first mask. In the process, a gate wiring including a gate line 22, a gate pad 24, a gate electrode 26, and a storage electrode 28 is formed on the insulating substrate 10.

Next, as shown in FIGS. 13A and 13B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kPa, 500 kPa to 2,000 kPa, 300 kPa to 600 kPa using chemical vapor deposition. After the continuous deposition to a thickness of, the conductor layer 60 made of aluminum, aluminum alloy or chromium is deposited by 1,500 kPa to 3,000 kPa in the order of sputtering or the like.

Next, the photosensitive film 110 is applied thereon with a thickness of 1 μm to 2 μm. Subsequently, the photoresist 110 is irradiated with light through a second mask and developed to form photoresist patterns 112 and 114 as shown in FIGS. 14B and 14C. At this time, among the photoresist patterns 112 and 114, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, which is the channel portion C of the thin film transistor, is the data wiring portion A, that is, the data wiring. The thickness of the second portion 112 is smaller than that of the second portion 112 positioned at the portion where the 62, 64, 65, 66, and 68 are to be formed.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

At this time, the width of the slit is preferably smaller than the resolution of the exposure machine used during exposure, in the case of using a semi-transparent film may use a thin film having a different transmittance or a different thickness in order to control the transmittance when manufacturing a mask.

When the light is irradiated to the photosensitive film through the mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. When the next photoresist film is developed, only the portion where the polymer molecules are not decomposed is left, and a thinner photoresist film is left at the center portion where the light is not irradiated. In this case, if the exposure time is extended, all molecules are decomposed, and this should be avoided.

The thin photoresist film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot completely transmit light, and then develops and ripples. It can also be formed by making a part of the photosensitive film flow to the part in which the photosensitive film does not remain.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 15A and 15B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, either a dry etching method or a wet etching method may be used. In this case, only the conductor layer 60 may be etched, and the photoresist patterns 112 and 114 may be performed under almost no etching conditions. However, in the case of dry etching, since only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not easily found, the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching, so that the first portion 114 is removed so that the conductor layer 60 is not exposed.

In this way, as shown in Figs. 15A and 15B, only the source / drain conductor pattern 67 and the storage capacitor conductor pattern 64 remain, and all the conductor layers of the other portion B are removed so that the intermediate layer thereunder. 50 is revealed. In this case, the remaining conductor patterns 64 and 67 are the same as those of the data lines 62, 64, 65, 66, and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. .

Next, as shown in FIGS. 16A and 16B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed by the dry etching method together with the first portion 114 of the photosensitive film. do. In this case, the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 are simultaneously etched, and the gate insulating layer 30 should be performed under an unetched condition, and in particular, the photoresist patterns 112 and 114 and the semiconductors are etched. It is desirable to etch under conditions where the etch ratio to layer 40 is approximately equal.

This removes the first portion 114 of the channel portion 114 to reveal the source / drain conductor patterns, as shown in FIGS. 16A and 16B, and the intermediate layer 50 and the semiconductor layer of the other portion B. 40 is removed to expose the gate insulating film 30 below. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. At this stage, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.

Subsequently, ashing removes the photoresist residue remaining on the source / drain conductor pattern of the channel part C.

Next, as illustrated in FIGS. 17A and 17B, the source / drain conductor pattern 67 of the channel portion C and the source / drain intermediate layer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57, and the wet / interface pattern 57 may be wet-etched with respect to the source / drain intermediate layer pattern 57. ) May be performed by dry etching.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

After forming the data lines 62, 64, 65, 66, and 68 in this manner, as shown in FIGS. 18A to 18C, spin coating an organic insulating material by chemical vapor deposition to obtain a protective film having a thickness of 3,000 kPa or more. Form 70. Next, after the photosensitive film is applied thereon, light is irradiated through the third mask and then developed to form a photosensitive film pattern. Next, the protective film 70 is dry-etched to expose the gate pad 24, the data pad 64, the drain electrode 66, and the conductive pattern 68 for the storage capacitor to expose the contact holes 72, 73, 74, and 76. To form. At this stage, some of the organic insulating material may remain inside the contact holes 72, 73, 74, and 76. Subsequently, as in the first embodiment of the present invention, plasma treatment is performed using gas containing Cl 2 / O 2 or HCl / O 2 in the protective film 70. In this case, a portion of the chromium film exposed through the contact holes 72, 73, 74, and 76 may be etched. Then, dry cleaning using an O 2 plasma or wet cleaning using an etching solution containing HNO 3, such as an etching solution of Al or Cr, is performed. Through this, the organic insulating material remaining in the contact holes 72, 73, 74, and 76 may be removed to reduce the contact resistance of the contact portion. At this time, the surface roughness of the protective film 70 is increased to improve the adhesion between the transparent conductive film formed in a later step and the protective film 70.

Next, as shown in FIGS. 11A and 11C, an ITO layer having a thickness of 400 μs to 500 μs is deposited and etched using a fourth mask to etch the pixel electrode 82, the auxiliary gate pad 84, and the auxiliary data pad 88. Form.

In the fourth embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48) may be formed using a single mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

As described above, in the method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, after plasma treatment using Cl 2 / O 2 or HCl / O 2 gas in a protective film, dry cleaning using an O 2 plasma or an etching solution of Al or Cr As described above, the contact resistance of the contact portion may be reduced by removing the organic insulating material remaining in the contact hole by wet cleaning using an etchant including HNO 3. In addition, since the color filter is formed on the thin film transistor substrate together with the thin film transistor, the alignment error of the two substrates does not have to be taken into account, so that the aperture ratio may be improved.

Claims (7)

Forming a gate wiring including a gate line, a gate electrode, and a gate pad on the insulating substrate, Forming a gate insulating film covering the gate wiring; Forming a semiconductor pattern on the gate insulating layer of the gate electrode; Forming a data line including a data line, a source electrode, a drain electrode, and a data pad on the semiconductor pattern or the gate insulating layer; Applying a passivation layer covering the data line and the semiconductor pattern; Removing a portion of the passivation layer to form a first contact hole exposing the drain electrode; Performing a plasma treatment on the protective film using Cl 2 / O 2 or HCl / O 2 gas; Performing at least one of dry cleaning using an O 2 plasma or wet cleaning using an etchant containing HNO 3, such as an etching solution of Al or Cr, to the protective film subjected to the plasma treatment; and Forming a pixel electrode connected to the drain electrode exposed through the first contact hole, The data line and the semiconductor pattern are formed by a photolithography process using one photoresist pattern. The manufacturing method of the thin film transistor substrate for liquid crystal display devices. In claim 1, The passivation layer may include at least one of an inorganic insulating material selected from silicon oxide or silicon nitride, or an organic insulating material selected from benzocyclobutene (BCB), perfluorocyclobutene (PFCB), and acrylic resin (acryl). . In claim 1, The passivation layer has second and third contact holes exposing the data pad and the gate pad, respectively; And forming an auxiliary data pad and an auxiliary gate pad connected to the data pad and the gate pad, respectively, through the second and third contact holes. In claim 1, Forming a black matrix and a color filter on the insulating substrate, and And forming an insulating film covering the black matrix and the color filter. In claim 1, And forming a chromium film on or below the gate wiring and the data wiring. In claim 1, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the photosensitive film pattern is formed using one mask. In claim 6, Forming the gate insulating film, the semiconductor pattern and the data wiring Sequentially depositing the gate insulating film, the semiconductor layer, and the conductive layer, Applying a photoresist film on the conductive layer, Exposing the photoresist to form a photoresist pattern having a first portion having a first thickness and a second portion thicker than the first thickness, and a third portion from which the photoresist is removed; Etching the conductive layer and the semiconductor layer under the third portion; Sequentially removing the first portion and the conductive layer positioned below the first portion to form the data line and the semiconductor pattern, and Removing the photoresist pattern Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a.

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