KR100920262B1 - 저-온 포스트-도펀트 활성화 공정 - Google Patents

저-온 포스트-도펀트 활성화 공정 Download PDF

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Publication number
KR100920262B1
KR100920262B1 KR1020047006129A KR20047006129A KR100920262B1 KR 100920262 B1 KR100920262 B1 KR 100920262B1 KR 1020047006129 A KR1020047006129 A KR 1020047006129A KR 20047006129 A KR20047006129 A KR 20047006129A KR 100920262 B1 KR100920262 B1 KR 100920262B1
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South Korea
Prior art keywords
source
drain regions
substrate
forming
gate electrode
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KR1020047006129A
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English (en)
Korean (ko)
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KR20040047967A (ko
Inventor
유빈
오그레로버트비.
패튼에릭엔.
타베리싸이루스이.
자이앙키
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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Publication of KR20040047967A publication Critical patent/KR20040047967A/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1020047006129A 2001-10-25 2002-10-11 저-온 포스트-도펀트 활성화 공정 Expired - Lifetime KR100920262B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/983,625 US6902966B2 (en) 2001-10-25 2001-10-25 Low-temperature post-dopant activation process
US09/983,625 2001-10-25
PCT/US2002/032555 WO2003036701A1 (en) 2001-10-25 2002-10-11 Low-temperature post-dopant activation process

Publications (2)

Publication Number Publication Date
KR20040047967A KR20040047967A (ko) 2004-06-05
KR100920262B1 true KR100920262B1 (ko) 2009-10-05

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ID=25530028

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KR1020047006129A Expired - Lifetime KR100920262B1 (ko) 2001-10-25 2002-10-11 저-온 포스트-도펀트 활성화 공정

Country Status (6)

Country Link
US (1) US6902966B2 (https=)
EP (1) EP1444725A1 (https=)
JP (1) JP2005523573A (https=)
KR (1) KR100920262B1 (https=)
CN (1) CN1316569C (https=)
WO (1) WO2003036701A1 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7422968B2 (en) * 2004-07-29 2008-09-09 Texas Instruments Incorporated Method for manufacturing a semiconductor device having silicided regions
US7018888B2 (en) * 2004-07-30 2006-03-28 Texas Instruments Incorporated Method for manufacturing improved sidewall structures for use in semiconductor devices
KR101113533B1 (ko) * 2006-03-08 2012-02-29 어플라이드 머티어리얼스, 인코포레이티드 기판상에 형성되는 구조체의 열적 처리를 위한 장치 및 방법
JP5309454B2 (ja) * 2006-10-11 2013-10-09 富士通セミコンダクター株式会社 半導体装置の製造方法
US7943512B2 (en) * 2007-12-13 2011-05-17 United Microelectronics Corp. Method for fabricating metal silicide
US7842590B2 (en) * 2008-04-28 2010-11-30 Infineon Technologies Austria Ag Method for manufacturing a semiconductor substrate including laser annealing
US8922189B2 (en) * 2008-11-18 2014-12-30 Texas Instruments Incorporated Controlled on-time buck PFC
CN102104006A (zh) * 2011-01-17 2011-06-22 复旦大学 一种场效应晶体管的制备方法
CN104025269B (zh) * 2012-11-12 2017-09-08 深圳市柔宇科技有限公司 一种自对准金属氧化物薄膜晶体管器件的制造方法
KR20160058499A (ko) 2014-11-17 2016-05-25 삼성전자주식회사 반도체 소자, 및 그 반도체 소자의 제조방법과 제조장치

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242081A (ja) 1996-12-26 1998-09-11 Sony Corp 半導体装置の製造方法

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JP3504336B2 (ja) * 1994-06-15 2004-03-08 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6300659B1 (en) * 1994-09-30 2001-10-09 Semiconductor Energy Laboratory Co., Ltd. Thin-film transistor and fabrication method for same
JP4130237B2 (ja) * 1995-01-28 2008-08-06 株式会社半導体エネルギー研究所 結晶性珪素膜の作製方法及び半導体装置の作製方法
US5977559A (en) * 1995-09-29 1999-11-02 Semiconductor Energy Laboratory Co., Ltd. Thin-film transistor having a catalyst element in its active regions
TW317643B (https=) * 1996-02-23 1997-10-11 Handotai Energy Kenkyusho Kk
US6387803B2 (en) * 1997-01-29 2002-05-14 Ultratech Stepper, Inc. Method for forming a silicide region on a silicon body
US6066547A (en) * 1997-06-20 2000-05-23 Sharp Laboratories Of America, Inc. Thin-film transistor polycrystalline film formation by nickel induced, rapid thermal annealing method
JP4318768B2 (ja) * 1997-07-23 2009-08-26 株式会社半導体エネルギー研究所 半導体装置の作製方法
US5937315A (en) 1997-11-07 1999-08-10 Advanced Micro Devices, Inc. Self-aligned silicide gate technology for advanced submicron MOS devices
US6037204A (en) * 1998-08-07 2000-03-14 Taiwan Semiconductor Manufacturing Company Silicon and arsenic double implanted pre-amorphization process for salicide technology
US6291278B1 (en) 1999-05-03 2001-09-18 Advanced Micro Devices, Inc. Method of forming transistors with self aligned damascene gate contact
US6287925B1 (en) 2000-02-24 2001-09-11 Advanced Micro Devices, Inc. Formation of highly conductive junctions by rapid thermal anneal and laser thermal process
US6251757B1 (en) * 2000-02-24 2001-06-26 Advanced Micro Devices, Inc. Formation of highly activated shallow abrupt junction by thermal budget engineering
US6274488B1 (en) * 2000-04-12 2001-08-14 Ultratech Stepper, Inc. Method of forming a silicide region in a Si substrate and a device having same
US6420218B1 (en) * 2000-04-24 2002-07-16 Advanced Micro Devices, Inc. Ultra-thin-body SOI MOS transistors having recessed source and drain regions
US6365446B1 (en) * 2000-07-03 2002-04-02 Chartered Semiconductor Manufacturing Ltd. Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process
US6399450B1 (en) * 2000-07-05 2002-06-04 Advanced Micro Devices, Inc. Low thermal budget process for manufacturing MOS transistors having elevated source and drain regions
TW509984B (en) * 2000-07-24 2002-11-11 United Microelectronics Corp Manufacture method of metal silicide
US6365476B1 (en) * 2000-10-27 2002-04-02 Ultratech Stepper, Inc. Laser thermal process for fabricating field-effect transistors
US6403434B1 (en) * 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242081A (ja) 1996-12-26 1998-09-11 Sony Corp 半導体装置の製造方法
US6159856A (en) 1996-12-26 2000-12-12 Sony Corporation Method of manufacturing a semiconductor device with a silicide layer

Also Published As

Publication number Publication date
WO2003036701A1 (en) 2003-05-01
JP2005523573A (ja) 2005-08-04
US6902966B2 (en) 2005-06-07
CN1575507A (zh) 2005-02-02
US20030082880A1 (en) 2003-05-01
EP1444725A1 (en) 2004-08-11
KR20040047967A (ko) 2004-06-05
CN1316569C (zh) 2007-05-16

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