KR100917058B1 - Method for fabricating triple gate oxide of semiconductor device - Google Patents
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- KR100917058B1 KR100917058B1 KR1020020086134A KR20020086134A KR100917058B1 KR 100917058 B1 KR100917058 B1 KR 100917058B1 KR 1020020086134 A KR1020020086134 A KR 1020020086134A KR 20020086134 A KR20020086134 A KR 20020086134A KR 100917058 B1 KR100917058 B1 KR 100917058B1
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- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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Abstract
본 발명은 로직 영역 및 I/O 블록에 영향을 주지 않도록 하여 로직 프로세스에 고전압 프로세스를 추가할 수 있도록 한 반도체 소자의 트리플 게이트 산화막 형성 방법에 관한 것으로, 반도체 기판의 소자 격리 영역에 소자 격리층을 형성하는 단계; 전면에 나이트라이드층을 형성하고 고전압 소자 형성 영역이 노출되도록 패터닝하는 단계; 상기 고전압 형성 영역의 표면에 제 1 두께의 제 1 게이트 산화막을 형성하는 단계; 로직 트랜지스터 형성 영역,I/O 트랜지스터 형성 영역상의 나이트라이드를 제거하고 로직 트랜지스터 형성 영역,I/O 트랜지스터 형성 영역에 각각 웰 영역들을 형성하는 단계; 제 2 두께의 제 2 게이트 산화막을 로직 트랜지스터 형성 영역,I/O 트랜지스터 형성 영역 상에 형성하고, 로직 영역상의 제 2 게이트 산화막을 제거하는 단계; 상기 로직 영역 상에 제 3 두께의 제 3 게이트 산화막을 형성하는 단계를 포함한다.
The present invention relates to a method for forming a triple gate oxide film of a semiconductor device in which a high voltage process can be added to a logic process without affecting the logic region and the I / O block. Forming; Forming a nitride layer on the front surface and patterning the high voltage device forming region to be exposed; Forming a first gate oxide film having a first thickness on a surface of the high voltage forming region; Removing nitride on the logic transistor formation region, the I / O transistor formation region and forming well regions in the logic transistor formation region and the I / O transistor formation region, respectively; Forming a second gate oxide film having a second thickness on the logic transistor formation region, the I / O transistor formation region, and removing the second gate oxide film on the logic region; Forming a third gate oxide film of a third thickness on the logic region.
고전압 게이트 산화막, 트리플 게이트 산화막High Voltage Gate Oxide, Triple Gate Oxide
Description
도 1a내지 도 1n은 본 발명에 따른 반도체 소자의 트리플 게이트 산화막 형성을 의한 공정 단면도
1A to 1N are cross-sectional views illustrating a process of forming a triple gate oxide film of a semiconductor device according to the present invention.
-도면의 주요 부분에 대한 부호의 설명-Explanation of symbols on main parts of drawing
11. 반도체 기판 12. 고농도 n형 웰 영역11.
13. 고농도 p형 웰 영역 14. 패드 산화막13. High concentration p
15.19. 나이트라이드 16.20.25. 포토레지스트 패턴15.19. Nitride 16.20.25. Photoresist pattern
17. HDP 산화막 18. PGI 패턴17.
21. 제 1 게이트 산화막 22. p형 웰 영역21.
23. n형 웰 영역 24. 제 2 게이트 산화막23. n-type
26. 제 3 게이트 산화막
26. Third Gate Oxide
본 발명은 반도체 소자에 관한 것으로, 구체적으로 로직 영역 및 I/O 블록에 영향을 주지 않도록 하여 로직 프로세스에 고전압 프로세스를 추가할 수 있도록 한 반도체 소자의 트리플 게이트 산화막 형성 방법에 관한 것이다.
The present invention relates to a semiconductor device, and more particularly, to a method of forming a triple gate oxide layer of a semiconductor device in which a high voltage process can be added to a logic process without affecting a logic region and an I / O block.
반도체소자에서 전기적으로 전압이 높은 고전압영역과 전압이 낮은 저전압 영역이 동시에 사용되는 멀티플 게이트 산화막(Multiple Gate Oxide)을 갖는 트랜지스터에서는 고전압영역의 게이트 산화막의 두께는 두껍게 형성하고, 저전압영역에서는 게이트 산화막의 두께를 얇게 형성하여서 전기적으로 절연이 적절하게 이루어지도록 구성되어져 있다.In a transistor having a multiple gate oxide in which a high voltage region having a high voltage and a low voltage region having a low voltage are used at the same time in a semiconductor device, a thick gate oxide film is formed in a high voltage region. It is configured to form a thin thickness and to electrically insulate properly.
반도체 소자의 고집적화 고기능화와 함께 메모리 소자와 로직 소자를 합병(merge)시킨 새로운 원 칩 소자(one-chip device)에 대한 요구가 날로 증가하고 있다. 이러한 합병된 디램과 로직 소자는 그 구조의 복잡함으로 인해 소자 제조에 있어서 공정 진행상 많은 어려움이 있다.Higher integration of semiconductor devices Along with high functionalization, there is an increasing demand for new one-chip devices in which memory devices and logic devices are merged. These merged DRAM and logic devices have many difficulties in the process of device manufacturing due to the complexity of the structure.
특히, 게이트 산화막의 경우, 로직 소자에 있어서는 소자의 속도를 향상시키기 위해 충분히 얇은 두께가 요구되나, DRAM 소자에 있어서는 얇은 게이트 산화막을 적용할 경우 게이트 산화막이 파괴될 염려가 있으므로 두껍게 형성하여야 한다.In particular, in the case of the gate oxide film, a thin enough thickness is required in the logic device to improve the speed of the device. However, in the DRAM device, when the thin gate oxide film is applied, the gate oxide film may be destroyed, so that the gate oxide film should be formed thick.
이러한 이유로 메모리 소자와 로직 소자를 하나의 칩에 합병시킨 소자를 제조하는데 있어서는 이중 게이트 산화막 형성 방법을 적용한다.For this reason, a method of forming a double gate oxide film is used to manufacture a device in which a memory device and a logic device are merged into one chip.
종래 기술의 이중 게이트 산화막 형성 방법에 의하면 게이트 산화막을 패터 닝할 때 일반적인 건식 식각을 이용한다.According to the method of forming a double gate oxide film of the related art, general dry etching is used when patterning a gate oxide film.
이러한 건식 식각 공정에 있어서는, 사불화메탄(CF4;tetra-fluoro methane)+수소(H2)나 삼불화메탄(CHF3;tri-fluoro methane)+산소(O2) 화학물을 사용한 반응성 이온 식각(RIE; Reactive Ion Etch)을 이용하여 산화막을 제거한다.In such a dry etching process, reactive ions using tetrafluorofluoromethane (CF 4 ) + hydrogen (H 2 ) or trifluorofluoromethane (CHF 3 ) + oxygen (O 2 ) chemicals The oxide layer is removed by etching (reactive ion etching).
그러나 이러한 건식 식각 공정의 경우, 식각 후 불소(F)가 산화막의 하부 막질로 존재하는 실리콘웨이퍼 표면에 습식 세정 방법에서보다 더 높은 농도로 잔존하게 되어 이후 공정에 나쁜 영향을 미치게 된다.However, in the dry etching process, fluorine (F) remains on the surface of the silicon wafer, which is present as a lower film of the oxide film, after etching, at a higher concentration than in the wet cleaning method, thereby adversely affecting the subsequent process.
또한, 식각 가스의 주입 에너지에 의해 실리콘웨이퍼 표면이 손상되어 실리콘웨이퍼 표면이 거칠어지거나 실리콘웨이퍼 표면 근방에 형성되어 있는 pn 접합층이 파괴될 수도 있다.In addition, the silicon wafer surface may be damaged by the injection energy of the etching gas, thereby roughening the silicon wafer surface or destroying the pn junction layer formed near the silicon wafer surface.
그러나 이와 같은 종래 기술의 게이트 산화막 형성 공정은 다음과 같은 문제점이 있다.However, the gate oxide film forming process of the prior art has the following problems.
종래 기술에서는 메모리 소자와 로직 소자를 하나의 칩에 합병시킨 소자를 제조하는데 있어서는 이중 게이트 산화막 형성 방법을 적용하는데, 특성이 우수한 다중의 게이트 산화막을 제공할 수 없어 0.18㎛ 프로세스에서 고전압 게이트 산화막을 구현하지 못한다.
In the prior art, a double gate oxide film forming method is applied to fabricate a device in which a memory device and a logic device are merged into one chip, and a high voltage gate oxide film is realized in a 0.18 μm process because a multi-gate oxide film having excellent characteristics cannot be provided. can not do.
본 발명은 이와 같은 종래 기술의 게이트 산화막 형성 공정의 문제를 해결하 기 위하여 안출한 것으로, 로직 영역 및 I/O 블록에 영향을 주지 않도록 하여 로직 프로세스에 고전압 프로세스를 추가할 수 있도록 한 반도체 소자의 트리플 게이트 산화막 형성 방법을 제공하는데 그 목적이 있다.
The present invention has been made to solve the problem of the gate oxide film forming process of the prior art, and a semiconductor device capable of adding a high voltage process to a logic process without affecting the logic region and the I / O block. It is an object of the present invention to provide a method for forming a triple gate oxide film.
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 트리플 게이트 산화막 형성 방법은 반도체 기판의 소자 격리 영역에 소자 격리층을 형성하는 단계; 전면에 나이트라이드층을 형성하고 고전압 소자 형성 영역이 노출되도록 패터닝하는 단계; 상기 고전압 형성 영역의 표면에 제 1 두께의 제 1 게이트 산화막을 형성하는 단계; 로직 트랜지스터 형성 영역,I/O 트랜지스터 형성 영역상의 나이트라이드를 제거하고 로직 트랜지스터 형성 영역,I/O 트랜지스터 형성 영역에 각각 웰 영역들을 형성하는 단계; 제 2 두께의 제 2 게이트 산화막을 로직 트랜지스터 형성 영역,I/O 트랜지스터 형성 영역상에 형성하고, 로직 영역상의 제 2 게이트 산화막을 제거하는 단계; 상기 로직 영역상에 제 3 두께의 제 3 게이트 산화막을 형성하는 단계를 포함하는 것을 특징으로 한다.
According to an aspect of the present invention, there is provided a method of forming a triple gate oxide layer of a semiconductor device, the method including: forming an isolation layer in an isolation region of a semiconductor substrate; Forming a nitride layer on the front surface and patterning the high voltage device forming region to be exposed; Forming a first gate oxide film having a first thickness on a surface of the high voltage forming region; Removing nitride on the logic transistor forming region, the I / O transistor forming region and forming well regions in the logic transistor forming region and the I / O transistor forming region, respectively; Forming a second gate oxide film having a second thickness on the logic transistor formation region, the I / O transistor formation region, and removing the second gate oxide film on the logic region; And forming a third gate oxide film of a third thickness on the logic region.
본 발명에 따른 반도체 소자의 트리플 게이트 산화막 형성 방법의 바람직한 실시예에 관하여 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the method of forming a triple gate oxide film of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a내지 도 1n은 본 발명에 따른 반도체 소자의 트리플 게이트 산화막 형성을 의한 공정 단면도이다. 1A to 1N are cross-sectional views illustrating a process of forming a triple gate oxide film of a semiconductor device according to the present invention.
본 발명은 0.18㎛ 프로세스에서 고전압 게이트 산화막 구현할 수 있도록 한 것으로 먼저, 도 1a에서와 같이, 반도체 기판(11)에 고농도 n형 웰 영역(12),고농도 p형 웰 영역(13)을 형성하고 전면에 패드 산화막(14),나이트라이드층(15)을 형성한다.According to the present invention, a high-voltage gate oxide film can be realized in a 0.18 μm process. First, as shown in FIG. 1A, a high concentration n-
그리고 전면에 포토레지스트를 도포하고 선택적으로 패터닝하여 STI 포토레지스트 패턴(16)을 형성한다.Then, a photoresist is applied to the entire surface and selectively patterned to form the
이어, 포토레지스트 패턴(16)을 이용하여 반도체 기판(11)의 소자 격리 영역을 선택적으로 식각하여 트랜치를 형성한다.Subsequently, the device isolation region of the
그리고 도 1b에서와 같이, 상기 트랜치를 포함하는 전면에 HDP 산화막(17)을 증착한다.1B, the
이어, 도 1c에서와 같이, HDP 산화막(17)상에 포토레지스트를 도포하고 패터닝하여 PGI 패턴(18)을 형성한다.Subsequently, as shown in FIG. 1C, a photoresist is applied and patterned on the
그리고 도 1d에서와 같이, PGI CMP(Chemical Mechanical Polishing) 공정을 진행하여 소자 격리층을 형성한다.As shown in FIG. 1D, the device isolation layer is formed by performing a PGI CMP (Chemical Mechanical Polishing) process.
이어, 도 1e에서와 같이, 액티브 영역상에 남아 있는 나이트라이드층을 습식 식각 공정으로 제거하고 도 1f에서와 같이, 전면에 100Å 두께의 나이트라이드층(19)을 형성한다.Next, as shown in FIG. 1E, the nitride layer remaining on the active region is removed by a wet etching process, and as shown in FIG. 1F, a
그리고 도 1g에서와 같이, 전면에 포토레지스트(20)를 도포하고 고전압 소자 형성 영역이 노출되도록 패터닝 한다.As shown in FIG. 1G, the
이어, 도 1h에서와 같이, 고전압 형성 영역의 표면에 900Å 두께의 제 1 게 이트 산화막(21)을 형성한다.1H, a first
그리고 도 1i에서와 같이, 습식 식각 및 HF 용액을 이용한 디핑(dipping) 공정으로 로직 트랜지스터 형성 영역,I/O 트랜지스터 형성 영역상의 나이트라이드(19)를 제거한다.As illustrated in FIG. 1I, the
이어, 도 1j에서와 같이, 포토리소그래피 공정으로 마스킹하여 로직 트랜지스터 형성 영역,I/O 트랜지스터 형성 영역에 각각 p형 웰 영역(22),n형 웰 영역(23)을 형성한다.Subsequently, as shown in FIG. 1J, the p-
그리고 도 1k에서와 같이, 120Å 두께의 제 2 게이트 산화막(24)을 로직 트랜지스터 형성 영역,I/O 트랜지스터 형성 영역상에 형성한다.As shown in FIG. 1K, a second
이어, 도 1l에서와 같이, 로직 영역만 노출되도록 포토레지스트 패턴(25)을 형성하고 로직 영역상의 제 2 게이트 산화막(24)을 제거한다.Next, as shown in FIG. 1L, the
그리고 도 1m에서와 같이, 세정 공정을 진행하고 로직 영역상에 제 3 게이트 산화막(26)을 형성한다.As shown in FIG. 1M, the cleaning process is performed, and a third
이어, 도 1n에서와 같이, 전면에 게이트를 형성용 폴리 실리콘층을 형성하여 후속 공정을 진행한다.Subsequently, as shown in FIG. 1N, a polysilicon layer for forming a gate is formed on the entire surface to proceed the subsequent process.
이상 설명한 내용을 통해 당업자라면 본 발명의 기술 사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.
따라서, 본 발명의 기술적 범위는 실시예에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의하여 정해져야 한다.
Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.
이상에서 설명한 본 발명에 따른 반도체 소자의 트리플 게이트 산화막 형성 방법은 다음과 같은 효과가 있다.The triple gate oxide film forming method of the semiconductor device according to the present invention described above has the following effects.
이와 같은 본 발명은 서로 두께가 다른 게이트 산화막을 로직 영역,I/O 영역, 고전압 소자 형성 영역에 각각 형성하여 고전압 게이트 산화막(500Å이상)를 구현할 경우에는 로직쪽에 대한 손상을 거의 주지 않기에 로직과 I/O(5V)와 고전압 게이트 산화막를 동시에 구현할 수 있는 효과가 있다.In the present invention, when the gate oxide films having different thicknesses are formed in the logic region, the I / O region, and the high voltage element formation region, respectively, the logic voltage and the logic side are hardly damaged when the high voltage gate oxide layer (500 Å or more) is implemented. I / O (5V) and a high voltage gate oxide film can be implemented simultaneously.
Claims (4)
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| KR100769134B1 (en) * | 2005-08-03 | 2007-10-22 | 동부일렉트로닉스 주식회사 | Method for Forming a Gate Dielectric of a Semiconductor Device |
| KR100769135B1 (en) * | 2005-08-12 | 2007-10-22 | 동부일렉트로닉스 주식회사 | Method for Forming a Gate Dielectric of a Semiconductor Device |
| US20230141716A1 (en) * | 2021-11-05 | 2023-05-11 | Micron Technology, Inc. | Finfets having various different thicknesses of gate oxides and related apparatus, methods, and computing systems |
| WO2024019435A1 (en) * | 2022-07-18 | 2024-01-25 | 주식회사 에이치피에스피 | Method for manufacturing semiconductor device |
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|---|---|---|---|---|
| KR20000020234A (en) * | 1998-09-18 | 2000-04-15 | 김영환 | Method for forming dual gate oxide of semiconductor device |
| JP2001156260A (en) | 1999-09-17 | 2001-06-08 | Nec Corp | Integrated circuit device, electronic circuit equipment, and circuit-manufacturing method |
| US6268266B1 (en) | 1999-10-22 | 2001-07-31 | United Microelectronics Corp. | Method for forming enhanced FOX region of low voltage device in high voltage process |
| KR20020010779A (en) * | 2000-07-31 | 2002-02-06 | 박종섭 | Method of forming gate-oxide in semicondcutor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20000020234A (en) * | 1998-09-18 | 2000-04-15 | 김영환 | Method for forming dual gate oxide of semiconductor device |
| JP2001156260A (en) | 1999-09-17 | 2001-06-08 | Nec Corp | Integrated circuit device, electronic circuit equipment, and circuit-manufacturing method |
| US6268266B1 (en) | 1999-10-22 | 2001-07-31 | United Microelectronics Corp. | Method for forming enhanced FOX region of low voltage device in high voltage process |
| KR20020010779A (en) * | 2000-07-31 | 2002-02-06 | 박종섭 | Method of forming gate-oxide in semicondcutor device |
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