KR100909054B1 - Driving circuit of liquid crystal display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display driving circuit for reducing an error in gray voltage, and includes a switch resistor of a switching element such as a polycrystalline silicon thin film transistor in a plurality of resistors connected in series to separate a plurality of gray voltages. As a result, the error of the gray scale voltage due to the switch resistance can be reduced.

Liquid Crystal Panel, Poly-silicon Thin Film Transistor, Digital Analogue Converter (DAC)

Description

Circuit for Driving Liquid crystal display device

1 is a block diagram of a general liquid crystal display device.

2 is a block diagram of a general data driver.

3 is a circuit diagram schematically showing a conventional DAC.

Figure 4 is a schematic view showing a conventional resistance string portion

5 is a circuit diagram schematically showing another conventional data driver.

6 is a circuit diagram schematically illustrating a DAC of a driving circuit of a liquid crystal display according to a first embodiment of the present invention.

FIG. 7 is a circuit diagram schematically illustrating a first resistor string unit of a driving circuit of a liquid crystal display according to a first embodiment of the present invention. FIG.

8 is a circuit diagram schematically illustrating a DAC of a driving circuit of a liquid crystal display according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram schematically illustrating a second resistance string unit of a driving circuit of a liquid crystal display according to a second embodiment of the present invention. FIG.

Explanation of symbols for the main parts of the drawings

50: gamma reference voltage section 51: upper decoder                 

52: lower decoder 53: first resistor string portion

54: second resistance string portion 55: LSB decoder portion

56: switching unit 57: decoder

Rsw: switch resistance R _unit : unit resistance

V _h : positive reference voltage V _l : negative reference voltage

R _N : highest resistance R ₁ : lowest resistance

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of a liquid crystal display device. Specifically, a switch resistor is designed by including a switch resistor of a switching element such as a polycrystalline silicon thin film transistor in a plurality of resistors connected in series to separate a plurality of gray voltages. The present invention relates to a driving circuit of a liquid crystal display device which can reduce the error of the gray scale voltage.

In general, the liquid crystal display device is in the spotlight as a portable display device because it is relatively light / thin / short / small compared to other display devices, a typical Note Book PC (Note Book) PC.

Such a liquid crystal display may be classified into a liquid crystal panel displaying a video signal and a driving circuit applying a driving signal to the liquid crystal panel from the outside.

Although not shown in the drawing, the liquid crystal panel is a display device in which liquid crystal is injected between two transparent substrates (glass substrates) bonded to each other with a predetermined space, and a plurality of liquid crystal panels arranged at regular intervals on one of the two transparent substrates. A gate line, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate line, a plurality of pixel electrodes formed in each pixel region having a matrix defined by the gate lines and the data lines, A plurality of thin film transistors for applying the signal of the data line to each pixel electrode in accordance with the signal of the gate line is formed at a portion where the gate line and the data line cross each other. A color filter layer, a common electrode, and a black matrix layer are formed on the remaining substrates.

Therefore, when the turn-on signal is sequentially applied to the gate line, an image is displayed because the data signal is applied to the pixel electrode of the corresponding line.

A general liquid crystal display device having a liquid crystal panel configured as described above and a data driving circuit for applying data to the liquid crystal panel will be described with reference to the accompanying drawings.

1 is a block diagram of a general liquid crystal display device.

That is, as described above, the liquid crystal display device includes a liquid crystal panel 1 in which a plurality of pixel regions defined by a plurality of gate lines G and data lines D perpendicular to each other are arranged in a matrix form, and The driving circuit unit 2 and the liquid crystal module (LCM) driving system 7 which supply driving signals and data signals to the liquid crystal panel 1 are divided.

Here, the LCM driving system 7 supplies power to the driving circuit unit 2, and the vertical synchronization signal (Vsync: frame discrimination signal), the horizontal synchronization signal (Hsync: line discrimination signal), and the data enable signal (DE: Enable signal only during the period in which the data voltage is output) and a clock signal.

In addition, the driving circuit unit 2 includes a data driver 1b for inputting a data signal to each data line D of the liquid crystal panel 1 and a gate line G of the liquid crystal panel 1. A timing controller for generating a gate signal 1a for applying a gate driving pulse, a driving pulse for driving the gate driver 1a, and a load signal and a data signal for driving the data driver 1b; 3), the power supply unit 4 for supplying the required voltage to the liquid crystal display panel 1 and the respective portions, and digital data input from the data driver 1b by receiving power from the power supply unit 4 as analog. A gamma reference voltage unit 5 for supplying a reference voltage required for conversion into data, and a constant voltage V _DD and a gate high voltage used in the liquid crystal panel 1 using the voltage output from the power supply unit 4. V _GH), Site is configured to include a low voltage (V _GL), the reference voltage (V _ref) and a common voltage (Vcom) DC / DC converter 6 to output the like.

In this case, the data driver 1b applies a data signal output from the timing controller 3 to the data line D. The data driver 1b will be described in detail as follows.

2 is a block diagram of a general data driver, in which the data driver 1b includes a bidirectional shift register 11, a data register 12, a latch 13, and a level shift. The unit 14, a digital to analog converter (DAC) 15 and the output unit 16.

First, the input signals of the data driver 1b include 6-bit R (red), G (green), and B (blue) data signals, 10 gamma reference voltages from VGMA1 to VGMA10, LS signals as output control signals, and data. There is a digital timing signal for driving the driver 1b.

The bidirectional shift register 11 installed at the top of the data driver 1b receives a horizontal clock signal HCLK and an input from the timing controller 3 while receiving an externally applied voltage Vdd and a system operating voltage Vss. When a signal (DIO1 or DIO2) commanding the start is applied, the operation is started to shift the pulse sequentially.

Then, the data register unit 12 stores the input data signal, R [0: 5], G [0: 5], and B [0: 5] data one by one in accordance with the sequentially shifted pulses. When the storage of one horizontal line data is all repeated, the data stored by the latch unit 13 are output at once.

The latch unit 13 applies the latch to the level shifter 14 unit, and the level shift unit 14 applies the data to the DAC 15 by level shifting the applied data to the system operating voltage.

Next, the DAC 15 selects a corresponding gray voltage from the 64 gray voltages (analogs) generated from the gamma reference voltages VGMA1 to VGMA10 input from the outside, and applies the corresponding gray voltage to the output unit 16. Numeral 16 amplifies the gray voltage applied according to the LS signal, which is an output control signal, and applies it to the actual liquid crystal panel 1 through the output terminals of Y1, Y2, ..., Y384.

At this time, although the DAC 15 uses a capacitor element, when the driving circuit is composed of the DAC 15 using such a capacitor element, the output voltage characteristic is linear to the output voltage characteristic at a power supply voltage in a range normally used for the driving circuit. There is a drawback that it is difficult to obtain straightness. For this reason, as the driving circuit of the liquid crystal display device, one constructed of a resistance division type DAC 15 using a resistance element is used.

The resistive division type DAC 15 is composed of a resistive element or a switching element as individual components, and the resistive element or switching element is mounted on a fabrication IC made of single crystal silicon to form the liquid crystal panel 1. Although it can also be comprised separately in the exterior, productivity can be improved by designing in parallel with the manufacturing process of the liquid crystal panel 1 by polycrystal silicon.

3 is a circuit diagram schematically showing a conventional DAC, in which a conventional DAC (15 in FIG. 2) uses a gamma reference voltage unit using 3 bits of RGB 6bit data signals latched by the latch unit (13 in FIG. 2). An upper decoder 31 and a lower decoder 32 for selecting reference voltages of an upper voltage and a lower voltage from the reference voltage supplied from FIG. 1, respectively, and the upper decoder 31 and the lower decoder 32, respectively. A resistor string unit 33 and a plurality of unit resistors (not shown) are connected in series to separate the eight gray voltages by receiving the upper and lower reference voltages selected from the resistor string unit 33 and the resistor string unit 33. It includes a LSB (Least Significant Bit) decoder 34 for selecting the corresponding gradation voltage according to the remaining three bits of the data signal of the eight gradation voltages to be output to the output unit (16 in FIG. 2).

Reference numeral 30 denotes an output terminal of the gamma reference voltage unit 5.

Although not shown, the upper decoder 31 and the lower decoder 32 may each select the upper and lower reference voltages supplied from the gamma reference voltage unit 5 using a plurality of switching elements such as transistors.

In addition, a plurality of unit resistors are configured such that each of the plurality of unit resistors has the same resistance value from the output terminal of the upper decoder 31 and the output voltages are sequentially outputted, and the plurality of unit resistors are selected by the upper decoder 31 and the lower decoder 32. The reference voltage can be divided.

In this case, it is common to use polycrystalline silicon doped with N-type or P-type impurities of about 1016 particles / cm ³ as the resistance element. These impurity concentrations need to control their resistance very precisely in order to suppress average output unevenness.

FIG. 4 is a view schematically showing a resistor string unit of the prior art, wherein the resistor unit of the prior art has a plurality of unit resistors R _unit for generating eight gray voltages, an inner portion of the upper decoder 31 and the lower decoder 32. It can be seen that including the switch resistance (Rsw) value.

The output voltage values output through the plurality of unit resistors Runit are respectively.

V _out0 = Rsw / (2Rsw + 8R _unit ) × (V _h -V _l ) + V _l

V _out1 = (R _unit + Rsw) / (2Rsw + 8R _unit ) × (V _h -V _l ) + V _l

.

V _out7 = (7R _unit + Rsw) / (2Rsw + 8R _unit ) × (V _h -V _l ) + V _l .

At this time, the output voltage (V _out ) is shown in proportional to R _unit / (2Rsw + 8R _unit ) to the reference voltage difference between the positive and negative portions.

However, if a switch (not shown) of the upper decoder 31 and the lower decoder 32 that selects the upper and lower reference voltages, respectively, is formed of a polycrystalline silicon thin film transistor, the error of the resistance value Rsw of the switch may increase. As a result, the DAC output is not stable.

Therefore, the resistance value of the unit resistor R _unit is significantly larger than the resistance values of the upper decoder 31 and the lower decoder 32 switches, thereby reducing the error of the DAC output value.

In this case, when the DAC having a high unit resistance value is to be implemented, an area is increased and a speed of the DAC is reduced.

On the other hand, if the electric field in the same direction is continuously applied due to the material properties of the liquid crystal, there is a problem that the liquid crystal is deteriorated, it is necessary to drive by inverting the polarity of the gray voltage with respect to the common voltage.

FIG. 5 is a circuit diagram schematically illustrating another conventional DAC, and includes a plurality of resistor string parts 43 each having a plurality of resistors connected in series to generate a plurality of gray voltages from the reference voltage of the gamma reference voltage unit 5. And a bipolar DAC 41 and a negative DAC 42 for selecting one of a plurality of gray voltages output through the resistor string unit 43 and allowing the selected gray voltages to have different polarities. There is a switching unit 44 for selecting an input of the bipolar DAC 41 or the negative DAC 42 by a polarity control signal and outputting the input to the data line.

Here, the bipolar DAC 41 and the negative DAC 42 receive 64 input voltages from the resistor string part 43 to display 64 gray levels, respectively, and input among the 64 input voltages. 63 analog switches and decoders are provided to select the voltage corresponding to the data.

In addition, the bipolar DAC 41 and the negative DAC 42 may select one output signal using a device such as a multiplexer.

Accordingly, the driving circuit of another conventional liquid crystal display device applies 64 input voltages from the resistor string portion 43 in which a plurality of unit resistors are connected in series to the bipolar DAC 41 and the negative DAC 42, respectively. By selecting one of the 64 input voltages and switching the output values of the positive and negative DACs 42, the data values output to the data lines can be reversed.

However, by designing the bipolar DAC 41 and the negative DAC 42 in consideration of such inversion, the data driver 1b may be complicated and the power consumption may increase.

As described above, the driving circuit of the liquid crystal display of the prior art has the following problems.                         

First, when a switch of an upper decoder and a lower decoder for selecting a reference voltage is implemented as a polycrystalline silicon thin film transistor, an error occurs in the DAC output value because the difference between the unit resistance and the switch resistance is small.

Second, the data driver is complicated and the power consumption is increased because a positive polarity DAC and a negative polarity DAC using a series resistor to make each of 64 gray voltages have to be polarized for the inversion of the liquid crystal.

The present invention is to solve the above problems, by designing the switch resistance value of the switching element to include a plurality of resistance values connected in series to separate the plurality of gray voltages to reduce the error of the gray voltage due to the switch resistance It is an object of the present invention to provide a driving circuit of a liquid crystal display device.

The driving circuit of the liquid crystal display device according to the present invention for achieving the above object comprises a liquid crystal panel, a gamma reference voltage portion, a gate driver and a data driver in the driving circuit of the liquid crystal display device, wherein the data driver is the gamma. The MSB decoder unit for selecting the upper reference voltage and the lower reference voltage using a switch controlled by the data signal among the reference voltages output from the reference voltage unit, and the internal switching resistance of the MSB decoder unit as one unit resistance A resistance string unit for separating and outputting a plurality of gray voltages from the plurality of unit resistors connected to each other, and an LSB decoder unit for selecting and outputting one of a plurality of gray voltages separated from the resistance string unit using the data signal; It is characterized by.

Here, the MSB decoder is preferably composed of an upper decoder and a lower decoder, respectively.

The switching device preferably includes a plurality of polycrystalline silicon thin film transistors doped with P-type impurities or doped with N-type impurities to select upper and lower reference voltages from the gamma reference voltage unit, respectively.

Preferably, the MSB decoder further connects a predetermined resistor to make the switch resistance equal to the unit resistance.

In addition, another feature of the present invention is a driving circuit of a liquid crystal display device comprising a liquid crystal panel, a gamma reference voltage unit, a gate driver and a data driver, wherein the data driver is gamma by a polarity control signal for selecting polarity. The switching unit for selecting the reference voltage of the positive and negative polarity from the reference voltage supplied from the reference voltage unit, respectively, and switching the polarity and outputting the highest voltage among the plurality of resistors connected in series to separate the plurality of gray voltages. A value is set to be the highest resistance value by adding to the switch resistance value of the switching part, and the lowest resistance value is set to the lowest resistance value by adding the switch resistance value of the switching part to the lowest resistance among the resistors and corresponding to the highest resistance value and the lowest resistance value. A resistor string unit for separating a plurality of gray voltages, and the resistors Buffering the plurality of gray scale voltages from the separating agent, and the ring is a driving circuit of a liquid crystal display device including a decoder for selecting and outputting one of said plurality of gray scale voltages.                     

Herein, the switching unit selects reference voltages of the positive and negative parts from the reference voltage, respectively, and converts the reference voltages of the positive and negative parts to the resistance string part and is doped with a p-type impurity or n-type. It is preferable to have a plurality of polycrystalline silicon thin film transistors doped with impurities.

Hereinafter, the driving circuit of the liquid crystal display according to the present invention will be described.

The driving circuit of the liquid crystal display device of the present invention includes a liquid crystal panel in which a plurality of pixel regions defined by a plurality of gate lines and data lines perpendicular to each other are arranged in a matrix form, and a data signal is input to each data line of the liquid crystal panel. A data driver, a gate driver for applying a gate driving pulse to each gate line of the liquid crystal panel, a driving pulse for driving the gate driver, and a load signal and a data signal for driving the data driver A timing controller, a power supply for supplying a voltage required for the liquid crystal panel and each part, and a gamma for supplying a reference voltage required for converting digital data input from the data driver into analog data by receiving power from the power supply. A reference voltage section and the power supply; Outputs a constant voltage (V _DD ), a gate high voltage (V _GH ), a gate low voltage (V _GL ), a reference voltage (V _ref ), and a common voltage (Vcom) used in the liquid crystal display panel by using the voltage output from the supply unit. It is configured to include a DC / DC converter.

Here, the data driver applies a data signal output from the timing controller to the data line when the horizontal synchronization signal is applied from the timing controller to the gate driver.

In this case, the data driver includes a bidirectional shift register part, a data register part, a latch part, a level shifter part, a digital to analog convertor (DAC) and an output part, and is driven as follows.

First, when a horizontal clock signal HCLK and a signal DIO1 or DIO2 are commanded from the timing controller while the bidirectional shift register unit receives an externally applied voltage Vdd and a system operating voltage Vss. Start the operation to shift the pulses sequentially.

Next, the data register unit stores the input data signals, R [0: 5], G [0: 5], and B [0: 5] data one by one according to the sequentially shifted pulses, and repeats this process. When the horizontal line data is all stored, the data stored by the latch unit is output at once.

The latch unit latches the applied data to the level shifter unit, and the level shifter unit level-shifts the applied data to a system operating voltage and applies the data to the DAC.

Next, the DAC generates 64 gray voltages (analogs) from the gamma reference voltage unit input from the outside, selects one of the 64 gray voltages corresponding to the data signal, and applies the gray voltage to the output unit. The gray voltage applied to the control signal LS signal is amplified and applied to the actual liquid crystal panel through the output terminals of Y1, Y2, ..., Y384.                     

Here, the DAC is a resistance division type DAC using a resistance element, and the resistance division type DAC is a separate component that directly designs a resistance element or a switching element on a lower substrate, that is, an array substrate of the liquid crystal panel.

In this case, a pass gate structure including a polycrystalline silicon thin film transistor doped with P-type impurities or doped with N-type impurities may be used as the resistor and the switching device.

In addition, by controlling the P-type or N-type impurity concentration very precisely, the resistance value can be adjusted to achieve a uniform output, and the resistance value can be adjusted by controlling the width and length of the pass gate.

Therefore, the driving circuit of the liquid crystal display device of the present invention will be described by taking an embodiment in consideration of the switch resistance of the switching element such as the polycrystalline silicon thin film transistor.

First embodiment

6 is a circuit diagram schematically illustrating a DAC of a driving circuit of a liquid crystal display according to a first embodiment of the present invention.

As shown in FIG. 6, the DAC of the data driver according to the present invention uses upper and lower portions supplied from the gamma reference voltage unit 50 using 3 bits of the RGB 6bit data signals latched by the latch unit (not shown). An upper decoder 51 and a lower decoder 52 for selecting a reference voltage, respectively, and a plurality of unit resistors in which the switching resistance values of the upper decoder 51 and the lower decoder 52 are one unit resistance value in series. The LSB decoder unit selects one of the first resistor string units 53 to be connected to each other by a plurality of gray voltages and the remaining 3 bits of the plurality of gray voltages separated from the first resistor string unit 53. It comprises 55.

Here, the upper decoder 51 and the lower decoder 52 are referred to as MSB decoders, and are doped with P-type impurities or doped with N-type impurities to select upper and lower reference voltages from the gamma reference voltage unit, respectively. A plurality of switching elements such as polycrystalline silicon thin film transistors are provided.

In addition, in the first resistor string unit 53, a plurality of unit resistors are connected in series to each output terminal of the upper decoder 51 and the lower decoder 52 to separate a plurality of gray voltages. The switch resistance value of the switching element used in the decoder 51 and the lower decoder 52 is designed to be equal to the resistance value of the unit resistance.

In this case, a predetermined resistor may be further connected to make the two switch resistance values of the upper decoder 51 and the lower decoder 52 equal to the same resistance value as the unit resistance.

That is, FIG. 7 is a circuit diagram schematically illustrating the first resistor string unit according to the present invention, wherein the first resistor string unit 53 uses the reference voltage selected by the upper decoder 51 and the lower decoder 52. A plurality of unit resistors are connected in series to produce a plurality of gray voltages, and are used by the upper decoder 51 and the lower decoder 52 to select reference voltages of the positive and negative polarities. All switch resistance values are designed to be the same as the unit resistance.

As a result, when all switch resistance values of the switching elements of the upper decoder 51 and the lower decoder 52 are equal to the resistance value of the unit resistance, the output voltage of the first resistor string part 53 is set to the upper decoder ( 51) and the difference between the upper and lower reference voltages selected by the lower decoder 52 increases in proportion to the resistance value of the upper coder.

For example, in the first resistor string unit 53 having eight output terminals, a switch resistance value obtained by adding the internal switch resistance of the upper decoder 51 and a predetermined resistance is set to half of the resistance of the unit resistance, and the lower resistance When the switch resistance value obtained by adding the internal switch resistance and the predetermined resistance of the decoder 52 is half the resistance value of the unit resistance, the voltage values output through the first resistance string unit 53 are respectively.

V _out0 = 1/16 (V _h -V _l ) + V _l

V _out1 = 3/16 (V _h -V _l ) + V _l

V _out2 = 5/16 (V _h -V _l ) + V _l

.

V _out7 = 15/16 (V _h -V _l ) + V _l .

Therefore, the driving circuit of the liquid crystal display according to the first embodiment of the present invention includes the switch resistances of the upper decoder 51 and the lower decoder 52 in the resistance of the first resistor string part 53 to increase the unit resistance value. It is possible to output an analog signal having a uniform gray voltage.

Second embodiment

The driving circuit of the liquid crystal display according to the second exemplary embodiment of the present invention is to invert the polarity of the gray scale voltage with respect to the common voltage.

8 is a circuit diagram schematically illustrating a DAC of a driving circuit of a liquid crystal display according to a second embodiment of the present invention.

As shown in FIG. 8, a switching unit for selecting reference voltages of the positive and negative polarities from the reference voltage supplied from the gamma reference voltage unit 50 by a polarity control signal for selecting the polarity, respectively. And a switch resistance value of the switching unit 56 is set to the highest resistance value among the plurality of resistors for separating the plurality of gray voltages and set as the highest resistance value, and the switching is performed to the lowest resistance among the resistors. A second resistance string unit 54 which is set to the lowest resistance value in combination with the switch resistance value of the unit 56 and separated into a plurality of gradation voltages corresponding to the highest resistance value and the lowest resistance value, and the second resistance string. And a decoder unit 57 for buffering the plurality of gray voltages separated in the unit 54 and selecting and outputting one of the plurality of gray voltages.

The switching unit 56 outputs the reference voltages of the positive and negative portions selected from the gamma reference voltage unit 56 to the second resistance string unit 54 according to the polar control signal. can do.

In addition, the switching unit 56 selects reference voltages of the positive electrode unit and the negative electrode unit from the reference voltage, respectively, and converts the reference voltages of the positive electrode unit and the negative electrode unit to the second resistor string unit 54 and outputs them. To this end, a plurality of switching elements such as polycrystalline silicon thin film transistors doped with P-type impurities or N-type impurities are provided.

In this case, since resistances according to driving of the plurality of switching elements may occur, the switch resistance of the switching element may be included in the uppermost resistance value of the second resistance string portion 54 so that the second resistance string portion 54 may have a resistance. Set to the highest resistance value. Similarly, the switch resistance is included in the lowest resistance value of the second resistance string portion 54 and set as the lowest resistance value of the second resistance string portion 54.

Therefore, the driving circuit of the liquid crystal display according to the second embodiment of the present invention can design a DAC that can be driven using one second resistance string portion 54, thereby simplifying the circuit and reducing power consumption. Can be reduced.

FIG. 9 is a circuit diagram schematically illustrating a second resistance string part of a driving circuit of a liquid crystal display according to a second exemplary embodiment of the present invention, wherein the reference electrode of the positive electrode part and the negative electrode part is selected from the gamma reference voltage part 50. There is a switch resistor Rsw of the switching section 56 for switching and outputting to the second resistance string section 54.

In addition, the switch resistor of the switching unit 56 in each of the highest resistance (R _N ) and the lowest resistance (R ₁ ) of the second resistance string portion 54 in which a plurality of resistors are connected in series to produce a plurality of gray scale voltages. The uppermost resistor R _N and the lowest resistor R _{1 of} the second resistor string unit 54 are designed to include values.

For example, in order to separate 64 gray voltages, the uppermost resistor R _N and the lowest resistor R ₁ of the string unit having 64 resistors connected in series are connected to the second resistor string unit 54. The switch resistance value of 56) is reset to the highest resistance (R _N ) and the lowest resistance (R _l ).

In this way, the resistance value of the resistance of the second resistance string portion 54 is

R ₀ '+ Rsw = R0

R ₁ '= R ₁

R ₂ '= R ₂

.

R _N-1 '= R _N-1

R _N '+ Rsw = R _N

Therefore, in the driving circuit of the liquid crystal display according to the second exemplary embodiment of the present invention, the switch resistance of the switching unit 56 is applied to the uppermost resistor R _N and the lowest resistor R ₁ of the second resistor string unit 54. In order to reduce the resistance value error of the second resistance string part 54 due to the switch resistance, a plurality of gray scale voltages can be stably output.

The driving circuit of the liquid crystal display device of the present invention as described above has the following effects.

First, the driving circuit of the liquid crystal display device of the present invention may output an analog signal having an equal gray scale voltage by including switch resistances of the upper decoder and the lower decoder in the resistance value of the resistance string part to become a unit resistance.

Second, the driving circuit of the liquid crystal display device of the present invention is designed to include the switch resistance of the switching unit in the uppermost resistance and the lowest resistance of the resistance string portion, it is possible to stably output a plurality of gray voltages.

Claims (6)

In a driving circuit of a liquid crystal display device comprising a liquid crystal panel, a gamma reference voltage portion, a gate driver, and a data driver, The data driver An MSB decoder unit for selecting an upper reference voltage and a lower reference voltage using a switching element controlled by a data signal among the reference voltages output from the gamma reference voltage unit;  A resistance string unit configured to set the switch resistance value of the internal switching element of the MSB decoder unit as one unit resistor and to separate and output a plurality of gray voltages from the plurality of unit resistors connected in series; And an LSB decoder unit which selects and outputs one of the plurality of gray voltages separated from the resistor string unit by using the data signal. The method of claim 1, And the MSB decoder unit comprises an upper decoder and a lower decoder, respectively. The method of claim 1, The switching element includes a plurality of polycrystalline silicon thin film transistors doped with P-type impurities or doped with N-type impurities in order to select an upper reference voltage and a lower reference voltage from the gamma reference voltage unit, respectively. Drive circuit of the device. The method of claim 1, And the predetermined resistance is further connected to make the MSB decoder equal to the unit resistance. In a driving circuit of a liquid crystal display device comprising a liquid crystal panel, a gamma reference voltage portion, a gate driver, and a data driver, The data driver A switching unit for selecting the reference voltages of the positive and negative polarity units from the reference voltage supplied from the gamma reference voltage unit and switching the polarity to output the polarity control signals for selecting the polarity; In order to separate a plurality of gray voltages, the highest resistance value of the plurality of resistors connected in series with the switch resistance value of the switching unit is set to a new highest resistance value, and the lowest resistance among the resistors is equal to the switch resistance value of the switching unit. A resistor string unit configured to add a new lowest resistance value and separate the plurality of gray voltages corresponding to the new highest resistance value and the new lowest resistance value; And a decoder unit for buffering a plurality of gray voltages separated from the resistor string unit and selecting and outputting one of the plurality of gray voltages. The method of claim 5, wherein The switching unit selects reference voltages of the positive electrode unit and the negative electrode unit from the reference voltage, respectively, and converts the reference voltages of the positive electrode unit and the negative electrode unit into the resistance string unit to be doped with p-type impurities or n-type impurities. And a plurality of doped polycrystalline silicon thin film transistors.

Images