KR100908820B1 - Plasma doping method and manufacturing method of semiconductor device using same - Google Patents

Abstract

The present invention is to provide a plasma doping method that can stabilize the plasma during plasma doping, prevent outgassing of the photoresist and prevent dopant loss, and a method of manufacturing a semiconductor device using the same. step; Forming a photoresist pattern on the doped region; Applying a first plasma doping to the doped region using the photoresist pattern as a barrier, starting from a dose lower than the desired dose and gradually increasing the dose to the required dose; And performing a second plasma doping to the doped region with a higher dose than the first plasma doping, and thereby stabilizing the plasma by keeping the chamber in a plasma form at all times, and doping the first plasma with low dose energy. Outgassing of the photoresist film can be prevented, and second plasma doping by dividing twice and three times with different doses and different energy can prevent dopant loss when removing the photoresist film, thereby stabilizing and improving electrical characteristics. It has an effect.

Plasma doping, outgassing, photoresist, polysilicon

Description

Plasma doping method and manufacturing method of semiconductor device using same {METHOD FOR PLASMA DOPING AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME}

The present invention relates to semiconductor manufacturing technology, and more particularly, to a plasma doping method and a method of manufacturing a semiconductor device using the same.

As semiconductor devices shrink, low energy and high doses in shallow junctions, P + additional implants, and dual polysilicon gate processes in converted schemes There is a need for an impurity doping process that requires a high dose.

To this end, plasma doping is currently performed as an impurity doping process. Plasma doping can yield higher doses than the beam line ion implants, thereby ensuring mass productivity.

However, in the case of plasma doping, since plasma is directly doped by using plasma in the chamber, the plasma needs to be stabilized, that is, the chamber atmosphere needs to be stabilized. Conditioning wafers are carried out to stabilize the chamber atmosphere, but when they are not sufficient, there is a problem in that electrical characteristics are changed due to different doping concentrations depending on the wafers.

1 is a graph showing a problem caused by the inability to stabilize the plasma.

Referring to FIG. 1, it can be seen that the threshold voltage of each slot of the wafer dummy slot changes. As the wafer number increases, the threshold voltage Vt decreases. This is because when the plasma is doped, when the idle time exists after the run, the threshold voltage is lower than that of the subsequent wafer where the plasma is not stabilized because the plasma is not stabilized in the first sheet of the wafer pile.

In addition, since plasma doping injects a large amount of ions at a time, outgasing occurs in the photoresist film used as a barrier film, which causes a problem that the doping concentration is changed while the plasma is shaken at the beginning of the doping.

Another problem is that plasma doping does not have an average ion implantation distance (Rp) because most of the dopants are doped on the surface, unlike the beamline ion implantation, which accelerates and injects ions, thereby biasing the platen. In addition, there is a problem that dopant loss of 70% or more is caused by a subsequent photoresist film strip process, and to solve this problem, the residual dose is saturated even if the doping dose is increased. There is this.

2 is a graph showing the concentration distribution according to the change and depth of the dose amount.

Referring to Figure 2, the dose is gradually increased to 1.0E17, 1.2E17, 1.5E17, it can be seen that there is little change in the concentration of boron. That is, even if the doping dose is increased to solve the dopant loss caused by the photoresist strip process, it can be seen that the residual dose is almost the same.

The present invention has been proposed to solve the above problems of the prior art, and provides a plasma doping method and a method of manufacturing a semiconductor device using the same, which can prevent stabilization of plasma, prevent outgassing of photoresist, and dopant loss during plasma doping. Its purpose is to.

A semiconductor device manufacturing method for achieving the above object comprises the steps of preparing a substrate having a doped region; Forming a photoresist pattern on the doped region; Applying a first plasma doping to the doped region using the photoresist pattern as a barrier, starting from a dose lower than the desired dose and gradually increasing the dose to the required dose; And subjecting the doped region to a second plasma doping at a higher dose than the first plasma doping.

In the above-described plasma doping and a method of manufacturing a semiconductor device using the same, the plasma can be stabilized by keeping the chamber in a plasma form at all times, and the outgassing of the photosensitive film is performed by first plasma doping so that the dose is gradually increased. The second plasma doping may be performed by dividing twice and three times with different doses and different energies to prevent dopant loss when removing the photoresist, thereby stabilizing and improving electrical characteristics.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a diagram illustrating a chamber in which plasma doping is performed.

Referring to FIG. 3, a chamber in which plasma doping is performed is composed of a gas inlet, a gas baffle, an RF coil, a platen, and a Faraday Cup. have.

After loading the wafer (substrate) into the platen in the chamber to perform the plasma doping, injecting gas for doping into the gas inlet, and applying a voltage to the RF coil to generate a plasma (Plasma), The generated plasma is moved toward the wafer by a bias applied to the platen. At this time, by checking the type and amount of the doping in the Faraday cup to adjust the amount of doping.

In particular, the plasma is formed using a mixture of Ar or Ar / H ₂ to maintain the chamber in a plasma form at all times. This is because the doping of impurities in the wafer by the unstable plasma is not good at the time until the plasma is stabilized in the run state for generating the plasma. In this case, it is not only difficult to find a proper conditioning, but also to inhibit the throughput, so that the plasma can be stabilized without conditioning.

4A to 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 4A, a gate insulating film 100 is formed on a substrate 11 having an NMOS region and a PMOS region. The substrate 11 may be a semiconductor (silicon) substrate on which a DRAM process is performed, and may include an isolation layer and a well. In addition, the gate insulating film 100 may have a stacked structure of the gate oxide film 12A and the gate nitride oxide film 12B.

The gate insulating film 100 may be formed by first forming an oxide film on the substrate 11 and nitriding the surface of the oxide film. When the gate insulating film 100 is formed by stacking the gate oxide film 12A and the gate nitride oxide film 12B, impurities used during subsequent ion implantation penetrate the gate insulating film 100 than when a single layer of the gate oxide film 12A is formed. As a result, penetration into the lower substrate 11 can be prevented.

The nitriding process for forming the gate nitride oxide film 12B may be performed by any one selected from the group consisting of furnace nitridation, plasma nitridation, and rapid thermal nitridation.

As shown in FIG. 4B, an N-type polysilicon layer 13 is formed on the gate nitride oxide film 12B. The N-type polysilicon layer 13 may be a polysilicon layer doped with N-type impurities (arsenic or phosphorus) in-situ.

Subsequently, the photosensitive film pattern 14 is formed on the N-type polysilicon layer 13 in the NMOS region. The photoresist pattern 14 may be formed by coating a photoresist on the N-type polysilicon layer 13 and patterning the photoresist to remain on the N-type polysilicon layer 13 in the NMOS region by exposure and development.

As shown in FIG. 4C, the first plasma doping is performed on the N-type polysilicon layer 13 in the PMOS region with the photoresist pattern 14 as a barrier.

The first plasma doping may be performed for 3 to 5 seconds. The first plasma doping is to prevent outgassing of the photoresist pattern 14 used as a barrier layer, and may be 2 to more than the required dose. Start with a dose that is as low as three wins and gradually increase to the required dose. For example, when the dose required is -E11 / mm, it can be carried out by gradually increasing the dose in the order of E9 / mm, E10 / mm and E11 / mm. This is because when the doping is performed with many doses at once, the photoresist pattern 14 is damaged by ion bombardment or the like, and outgassing occurs. This is because the gas can be prevented.

That is, high dose is applied to convert the N-type polysilicon layer 13 to P-type. When the first plasma doping is gradually performed to raise the dose, the photoresist pattern 14 is instantaneously high. Defect can be outgassed to prevent the plasma from shaking.

The first plasma doping may be performed using P-type impurities, and BF ₃ and B ₂ H ₆ may be used as P-type impurities.

As shown in Fig. 4D, the second plasma doping is performed on the N-type polysilicon layer 13 in the PMOS region. The second plasma doping is for converting the N-type polysilicon layer 13 to the P-type polysilicon layer 13A. The second plasma doping is performed at a higher dose than the first plasma doping, but the doping dose and energy are different. This can be done twice or three times.

First, the first plasma doping is to form a thin deposition layer 15 on the photosensitive film pattern 14 and the P-type polysilicon layer 13A at the same time as doping, using BF ₃ and B ₂ H ₆ gas, Low energy of 1KV-7KV and 30% -50% of total dose can be performed.

Since the deposition layer 15 formed through the first plasma doping is formed to a thickness of 20 μs to 100 μs and serves as a barrier, it is possible to dop with higher energy and dose than the first plasma doping in the subsequent secondary and tertiary plasma doping. Do.

Most of the dopants are distributed on the surface of the P-type polysilicon film 13A by performing the first plasma doping with a low energy of 1 KV to 7 KV. For example, the dopants of the dopants have a form in which many dopants are concentrated on the deposition layer 15, such as 'P ₁ ', and the distribution ratio of the dopants decreases as the P-type polysilicon film 13A is lowered.

Subsequently, secondary and tertiary plasma doping are performed as shown in FIG. 4E. Secondary and tertiary plasma doping is to improve the doping profile of impurities in the P-type polysilicon layer 13A, using the same gas as the primary plasma doping, and having a higher dose and higher energy than the first plasma doping. However, it can be performed with an energy of 8 to 20 KV and 50% to 70% of the total doping dose. The total doping dose through the second plasma doping may be 1.0E15 to 1.0E17 atoms / cm ² .

In addition, by forming the deposition layer 15 in FIG. 4D, impurities may be prevented from penetrating into the gate insulating film 100 even when plasma doping with higher dose and higher energy than primary plasma doping is performed.

As described above, the doping profile of the P-type polysilicon layer 13A is changed from P ₁ to P ₂ due to the secondary and tertiary plasma doping. That is, since the deposition layer 15 can act as a barrier and can be doped with higher energy than the first plasma doping, the distribution of impurities is more impurity inside P ₁ to P-type polysilicon layer 13A concentrated on the surface. This distribution changes to P ₂ .

As shown in FIG. 4F, the photoresist pattern 14 is removed. The photosensitive film pattern 14 may be removed by a strip process and a cleaning process using oxygen plasma. In addition, since the deposition layer formed on the photoresist pattern 14 and the P-type polysilicon layer 13A is thin, it does not affect the stripping of the photoresist pattern 14.

In particular, since more impurities are distributed in the P-type polysilicon layer 13A, such as P ₂ , the dopant loss is reduced even when the photosensitive film pattern 14 is stripped and cleaned. It can be minimized.

Subsequently, as shown in FIG. 4F, activation annealing is performed on the N-type and P-type polysilicon layers 13 and 13A. Activation annealing is for activating doped impurities. Spike-Rapid Thermal Annealing (S-RTA) or Conventional RTA (C-RTA) can be used. It can be annealed for a short time by heating up to a higher temperature at a faster ramp up rate than conventional rapid annealing.

As shown in FIG. 4E, the N-type and P-type polysilicon layers 13 and 13A and the gate insulating film 100 are patterned.

Before patterning, a tungsten layer or a tungsten silicide layer may be formed on the N-type and P-type polysilicon layers 13 and 13A to reduce the resistance of the gate, and a hard mask nitride film may be formed to serve as a hard mask during patterning. can do.

By patterning, dual polysilicon gates having an N-type polysilicon electrode 13B in the NMOS region and a P-type polysilicon electrode 13C in the PMOS region can be formed.

5A and 5B are graphs for comparing presence or absence of first plasma doping.

Referring to FIG. 5A, it can be seen that the plasma is shaken due to the outgassing of the photoresist pattern when the first plasma doping is not performed.

On the contrary, as shown in FIG. 5B, when the first plasma doping is performed for 3 seconds to 5 seconds, the outgassing of the photoresist pattern may be reduced, thereby preventing the plasma from shaking.
6 is a graph showing after the second plasma doping.

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Referring to FIG. 6, it can be seen that more impurities are distributed in the polysilicon layer after the second plasma doping than the first plasma doping.

Meanwhile, although the embodiment of the present invention has been described with respect to the dual polysilicon gate forming process, the present process for stabilizing plasma, preventing outgassing of the photoresist pattern, and preventing dopant loss when removing the photoresist pattern is performed in addition to the dual polysilicon gate formation process. It is also applicable to shallow junctions or P-type implantation.

As such, although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a graph showing a problem caused by the plasma is not stabilized,

2 is a graph showing the concentration distribution according to the change and depth of the dose amount;

3 is a view showing a chamber in which plasma doping is performed;

4A to 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention;

5a and 5b is a graph for comparing the presence or absence of the first plasma doping,

6 is a graph showing after the second plasma doping.

* Explanation of symbols for the main parts of the drawings

11: substrate 13: N-type polysilicon layer

14 photosensitive film pattern 15 deposition layer

100: gate insulating film

Claims (12)

Preparing a substrate having a doped region; Forming a photoresist pattern on the doped region; Applying a first plasma doping to the doped region using the photoresist pattern as a barrier, starting from a dose lower than the desired dose and gradually increasing the dose to the required dose; And Applying a second plasma doping to the doped region with a higher dose than the first plasma doping; Plasma doping method comprising a. The method of claim 1, The first and second plasma doping are always performed in a chamber maintaining a plasma atmosphere, wherein the plasma atmosphere is formed by using a plasma using a mixed gas of Ar or Ar / H ₂ . The method of claim 1, Wherein the first plasma doping is performed for 3 to 5 seconds, starting at a dose two to three times lower than the desired dose and gradually increasing to the desired dose. The method of claim 1, The second plasma doping method is performed by dividing the doping dose and energy differently twice or three times. The method of claim 4, wherein The second plasma doping, Performing primary plasma doping with an energy of 1-7 KV and 30% -50% of the total doping dose; Performing secondary and tertiary plasma doping with energy of 8-20KV and 50% -70% of total doping dose Plasma doping method comprising a. The method of claim 5, Wherein the total doping dose is 1.0E15 to 1.0E17 atoms / cm ² . The method of claim 5, And performing a first plasma doping to form a deposition layer having a thickness of 20 GPa to 100 GPa on the doped region. The method of claim 1, Wherein said first and second plasma doping are performed to form dual polysilicon gates of shallow junction or converted structure. The method of claim 1, After the step of performing the second plasma doping, Removing the photoresist pattern; And Activation annealing step for activation of impurities Plasma doping method further comprising. The method of claim 1, Wherein said substrate is a PMOS region and said doped region comprises an N-type polysilicon layer. The method of claim 1, Wherein the doped region includes an N-type polysilicon layer, and the first and second plasma doping dopants to form a P-type impurity. The method of claim 11, The P-type impurity is a plasma doping method using BF ₃ and B ₂ H ₆ .

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