KR100703835B1 - Semiconductor device with dual polysilicon gate to prevent polysilicon depletion effect and method for manufacturing the same - Google Patents

Abstract

To provide a method of manufacturing a semiconductor device that can prevent the diffusion of the dopant doped to the polysilicon used as the gate electrode in the subsequent gate reoxidation process, the semiconductor device of the present invention is characterized in that the NMOSFET region and PMOSFET region A semiconductor substrate, a gate oxide film on the semiconductor substrate, an n + polysilicon electrode formed in the NMOSFET region on the gate oxide film and a p + polysilicon electrode formed on the PMOSFET region, the n + polysilicon electrode and the p + polysilicon electrode, respectively The stacked metal electrode and the gate hard mask, a nitride layer formed on the exposed sidewalls of the metal electrode, and an oxide layer formed on the exposed sidewalls of the n + polysilicon electrode and the p + polysilicon electrode, the present invention The nitride layer can prevent the metal electrode from being oxidized during the gate reoxidation process.

Gate reoxidation, metal electrode, nitride layer, polysilicon electrode

Description

Semiconductor device having dual polysilicon gate which prevents polysilicon depletion phenomenon and method of manufacturing thereof {SEMICONDUCTOR DEVICE WITH DUAL POLYSILICON GATE TO PREVENT POLYSILICON DEPLETION EFFECT AND METHOD FOR MANUFACTURING THE SAME}

1 is a view showing a C-V curve (Capacitance-Voltage Curve) of a PMOSFET according to the prior art,

FIG. 2 is a view illustrating a profile of boron depending on whether or not tungsten silicide (WSix) is deposited on boron-doped polysilicon.

3 is a cross-sectional view illustrating a structure of a semiconductor device according to an embodiment of the present invention.

4A to 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 field oxide film

33: gate oxide film 34a: p + polysilicon electrode

34b: n + polysilicon electrode 37: metal electrode

38: gate hard mask 40: nitride layer

41: oxide layer 42: gate bird's beak

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a semiconductor device capable of preventing PDE (Poly Silicon Depletion Effect).

As the degree of integration of semiconductor devices increases, the channel length of the transistors also becomes very short. As the channel length decreases, there is a problem in the general transistor structure that the so-called short channel effect (SCE), in which the threshold voltage of the transistor is sharply lowered, becomes worse. In particular, in a PMOSFET having an n + polysilicon gate, a short channel effect occurs more seriously because a buried channel is formed.

To overcome this problem, a dual polysilicon gate formed of n + polysilicon having a low work function (4.14eV) in NMOSFET and p + polysilicon having a high work function (˜5.3eV) in PMOSFET is studied. There is. In other words, by controlling the work function of polysilicon, both NMOSFETs and PMOSFETs form a surface channel.

In order to control the work function of polysilicon, a certain dopant is ion implanted into polysilicon. Ph or As is ion implanted to form n + polysilicon, and B or BF ₂ is ion implanted to form p + polysilicon. .

However, the general dual polysilicon gate has several disadvantages, one of which is that polysilicon doped dopants are out-diffused in a subsequent process, causing polysilicon depletion, or poly silicon depletion effect (PDE). Is that.

FIG. 1 is a diagram illustrating a C-V curve of a PMOSFET according to the prior art.

When the dopant is externally diffused from polysilicon, the capacitance value of the inversion region compared to the accumulation in the C-V curve is reduced to 65% as shown in FIG. 1. That is, since the operation speed in the inversion region in which the transistor is operated decreases rapidly, the device reliability deteriorates.

The biggest cause of external diffusion of the dopant is that the oxide material is formed while the electrode material deposited on the polysilicon is oxidized in a gate-reoxidation process. This is because when the oxide film is formed in a high temperature oxidizing atmosphere, dopants are easily piled up on the oxide film through the interface of the electrode material / polysilicon or the grain boundary of the electrode material.

FIG. 2 illustrates a profile of boron with or without tungsten silicide (WSix) deposition on boron-doped polysilicon.

In the WSix / polysilicon structure, as SiO ₂ is formed on the WSix, dopants are externally diffused through the WSix, thereby lowering the boron concentration in the polysilicon. In the case of using WSix ('Y') as compared to the case of using only the polysilicon gate ('X') in Figure 2 is a significantly lower boron concentration.

The present invention has been proposed to solve the above problems of the prior art, a semiconductor device capable of preventing the PDE phenomenon caused by the external diffusion of the dopant doped in the polysilicon used as the gate electrode in the subsequent gate regeneration process And a method for producing the same.

The semiconductor device of the present invention for achieving the above object is a semiconductor substrate, a gate oxide film on the semiconductor substrate, a silicon electrode implanted with a dopant on the gate oxide film, a metal electrode and a gate hard mask stacked on the silicon electrode, the metal electrode And an oxide layer formed on the exposed sidewall of the silicon electrode, and an oxide layer formed on the exposed sidewall of the silicon electrode, wherein the antioxidant layer is formed by nitriding the exposed sidewall of the metal electrode.

In addition, the semiconductor device of the present invention includes a semiconductor substrate having an NMOSFET region and a PMOSFET region, a gate oxide film on the semiconductor substrate, an n + polysilicon electrode formed on the NMOSFET region on the gate oxide film and a p + polysilicon electrode formed on the PMOSFET region, A metal electrode and a gate hard mask stacked on the n + polysilicon electrode and the p + polysilicon electrode, a nitride layer formed on exposed sidewalls of the metal electrode, and the n + polysilicon electrode and the p + polysilicon electrode; It characterized in that it comprises an oxide layer formed on the side wall.

The method of manufacturing a semiconductor device of the present invention includes forming a gate insulating film on a semiconductor substrate having an NMOSFET region and a PMOSFET region, forming a silicon electrode implanted with a dopant on the gate insulating layer, and Forming a metal electrode on the metal electrode; forming a gate hard mask on the metal electrode; patterning the gate hard mask and the metal electrode; forming a gate electrode on the exposed sidewalls of the first patterned metal electrode; Forming an anti-oxidation layer and performing secondary gate patterning to pattern the silicon electrode using the gate hard mask patterned by the primary patterning as an etching barrier to form gate structures in the NMOSFET region and the PMOSFET region, respectively. And the gate reoxidation process to selectively expose the exposed sidewall of the silicon electrode. And oxidizing.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

3 is a cross-sectional view illustrating a structure of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 3, the semiconductor substrate 31 in which the NMOSFET region and the PMOSFET region are separated by the field oxide film 32, the gate oxide film 33 on the semiconductor substrate 31, and the NMOSFET region on the gate oxide film 33 are formed. N + polysilicon electrode 34b formed on the substrate, p + polysilicon electrode 34a formed on the PMOSFET region on the gate oxide film 33, metal electrodes formed on the n + polysilicon electrode 34b and the p + polysilicon electrode 34a, respectively. (37), gate hard mask 38 on metal electrode 37, nitride layer 40 formed on exposed sidewalls of metal electrode 37, and n + polysilicon electrode 34b and p + polysilicon electrode 34a Oxide layer 41 formed on the exposed sidewalls of the substrate.

In the semiconductor device having the above structure, the stacked structure of the n ⁺ polysilicon electrode 34b, the metal electrode 37, and the gate hard mask 38 formed in the NMOSFET region constitutes the first gate 100. The stacked structure of the p ⁺ polysilicon electrode 34a, the metal electrode 37, and the gate hard mask 38 formed in the PMOSFET region forms the second gate 200. A gate bird's beak 42 is formed at the lower edges of the first gate 100 and the second gate 200.

In FIG. 3, the nitride layer 40 formed on the exposed sidewall of the metal electrode 37 prevents the metal electrode 37 from being oxidized during the gate reoxidation process for forming the gate buzz big 42 and the oxide layer 41. It is to.

As such, since the nitride layer 40 is formed on the exposed sidewall of the metal electrode 37, the diffusion of the dopant injected into the n + polysilicon electrode 34b and the p ⁺ polysilicon electrode 34a during the gate reoxidation process. To prevent. For example, phosphorus or arsenic is injected into the n + polysilicon electrode 34b, and a dopant selected from boron (B), boron fluoride (BF) or boron difluoride (BF ₂ ) is injected into the p + polysilicon electrode 34a. Since the dopants are prevented from oxidizing the metal electrode 37 by the nitride layer 40, external diffusion is suppressed during the gate reoxidation process.

4A through 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 4A, the field oxide layer 32 is formed in a predetermined region of the semiconductor substrate 31 through a shallow trench isolation (STI) process. This field oxide film 32 separates the NMOSFET and the PMOSFET. Hereinafter, it is assumed that the silicon substrate 31 is divided into an NMOSFET region and a PMOSFET region for convenience of description.

Subsequently, a gate oxide film 33 is formed on the surface of the silicon substrate 31 on which the field oxide film 32 is formed to have a thickness of 5 kPa to 100 kPa through a gate oxidation process.

Next, after depositing the polysilicon layer 34 on the gate oxide layer 33, a photoresist is applied on the polysilicon layer 34 and patterned by exposure and development to open the PMOSFET region and cover the NMOSFET region. The mask pattern 35 is formed.

Next, the dopant (or p-type dopant) of the Group 3 element is ion-implanted using the first mask pattern 35 as an ion implantation barrier. At this time, the dopant of the Group 3 element is selected from boron (B), boron fluoride (BF) or boron difluoride (BF ₂ ), the energy at the time of ion implantation is 2keV ~ 30keV, the dose amount is 1E15 ~ 1E16 / cm ² .

The ion implantation of the dopant of the Group 3 element proceeds to the polysilicon layer 34 of the PMOSFET region, and the polysilicon layer 34 of the PMOSFET region is p ⁺ doped with a dopant (p type dopant) of the Group 3 element. It is changed to the polysilicon electrode 34a. Thus, the polysilicon layer 34 in the NMOSFET region covered by the first mask pattern 35 still remains without any dopant implanted.

As shown in FIG. 4B, after the first mask pattern 35 is removed, a photoresist film is applied to the entire surface and patterned by exposure and development to form a second mask pattern 36 covering the PMOSFET region and opening the remaining NMOSFET region. do.

Next, a dopant (or n-type dopant) of a Group 5 element is implanted into the polysilicon layer 34 of the NMOSFET region opened by the second mask pattern 36. At this time, the dopant of the Group 5 element is selected from phosphorus (Ph) or arsenic (As), the energy at the time of ion implantation is 3keV ~ 50keV, the dose amount is 1E15 ~ 1E16 / cm ² .

The ion implantation of the dopant of the Group 5 element proceeds to the polysilicon layer 34 above the NMOSFET region except for the PMOSFET region, and the polysilicon layer 34 of the NMOSFET region is a dopant (n-type dopant) of the Group 5 element. Is changed to the ion implanted n ⁺ polysilicon electrode 34b.

As described above, after dopant ion implantation for forming the p + polysilicon electrode 34a and the n + polysilicon electrode 34b, a thermal process may be performed for uniform distribution of the dopant.

As shown in FIG. 4C, after the second photoresist layer pattern 36 is removed, the metal electrode 37 and the gate hard mask 38 are sequentially formed on the entire surface. At this time, the metal electrode 37 is for lowering the resistance of the gate and is formed of a metal such as tungsten or a metal silicide such as tungsten silicide, and the gate hard mask 38 is formed of a silicon nitride film.

Next, a photoresist film is coated on the gate hard mask 38 and patterned by exposure and development to form a third photoresist pattern 39. In this case, the third photoresist pattern 39 serves as a gate mask for gate patterning.

Subsequently, primary gate patterning is performed to etch the gate hard mask 38 and the metal electrode 37 using the third photoresist pattern 39 as an etch barrier.

As shown in FIG. 4D, after removing the third photoresist pattern 39, a nitriding process is performed.

In this case, the nitriding process applies a plasma nitridation process capable of low temperature nitriding or a thermal nitridation process capable of high temperature nitriding.

First, the plasma nitridation process uses microwave or high frequency plasma, and is selected from among N ₂ , NH ₃ , N ₂ O or NO as a source gas, and in order to inject a mixture of these source gases or increase plasma efficiency, Rare gas selected from, Kr or Xe may be added. The power for forming the plasma is 100 W to 5 kW, and the process pressure is 1 tor to 100 tor.

Next, the thermal nitriding process is a nitriding process in a furnace, and proceeds using a gas selected from N ₂ , NH ₃ , N ₂ O or NO as an atmosphere gas at a high temperature of 600 ° C. to 1300 ° C.

The nitriding process as described above does not nitride the gate hard mask 38 and selectively nitrides only the exposed sidewall portion of the metal electrode 37. The nitriding process causes the exposed sidewall portion of the metal electrode 37 to be nitrided. The nitride layer 40 is formed on the exposed sidewall of the metal electrode 37.

For example, if the metal electrode 37 is tungsten, the nitride layer 40 will be a tungsten nitride film, and if the metal electrode 37 is tungsten silicide, the nitride layer 40 will be WSiN.

As shown in FIG. 4E, secondary gate patterning is performed to etch the n + polysilicon electrode 34b and the p + polysilicon electrode 34a under the metal electrode 37 using the gate hard mask 38 as an etch barrier. Thus, the first and second gates 100 and 200 are completed on the NMOSFET region and the PMOSFET region, respectively. That is, the first gate 100 is formed in the NMOSFET region, and the second gate 200 is formed in the PMOSFET region.

Looking at the structure of the first gate 100 and the second gate (100, 200) as described above, the first gate 100 formed in the NMOSFET region is n ⁺ polysilicon electrode 34b, the metal electrode 37 and the gate The second gate 200 having the structure stacked in the order of the hard mask 38 and the second gate 200 formed in the PMOSFET region is stacked in the order of p ⁺ polysilicon electrode 34a, the metal electrode 37, and the gate hard mask 38. Has a structure.

The nitride layer 40 is formed on both side surfaces of the metal electrode 37 in both the first gate 100 and the second gate 200.

As shown in FIG. 4F, a gate re-oxidation process is performed. Here, the gate reoxidation process is for selectively oxidizing only the n + / p + polysilicon electrodes 34b / 34a, and the exposed side of the n + / p + polysilicon electrodes 34b / 34a is oxidized by the gate reoxidation process. Thus, an oxide layer 41 is formed, and gate bird's beaks 42 are formed at the lower edges of the first gate 100 and the second gate 200. The gate bird's beak 42 serves to prevent the electric field from being concentrated at the lower edges of the first and second gates 100 and 200.

Since the nitride layer 40 is formed on the sidewall of the metal electrode 37 in the gate reoxidation process as described above, the metal electrode 37 is not oxidized by the nitride layer 40.

Subsequently, although not shown, a gate spacer in contact with both side walls of the first gate 100 and the second gate 200 is formed in a subsequent process, and a source / drain region is formed through ion implantation of the dopant to form an NMOSFET and a PMOSFET. Complete

According to the above-described embodiment, the gate buzz during the gate reoxidation process is performed by performing the nitriding process of forming the nitride layer 40 on the side of the metal electrode 37 before the n + / p + polysilicon electrodes 34b / 34a are patterned. While the formation of the big 42 and the formation of the oxide layer 42 on the side of the n + / p + polysilicon electrodes 34b / 34a are performed as in the related art, the formation of the oxide layer on the sidewall of the metal electrode 37 can be prevented.

As a result, by forming the nitride layer 40 on the surface of the metal electrode 37 through the nitriding process, the dopants injected into the n + / p + polysilicon electrodes 34b / 34a are oxidized while the metal electrode 37 is oxidized during the gate reoxidation process. The decrease in the dopant concentration in the n + / p + polysilicon electrodes 34b / 34a generated by external diffusion can be suppressed.

In the above-described embodiment, the polysilicon layer having no dopant implanted into the n + / p + polysilicon electrodes 34b / 34a was formed and then the dopant was implanted in a subsequent process, but the silicon electrode formed amorphous silicon without dopant implantation. After the dopant is injected, a polysilicon layer doped in situ or an amorphous silicon layer doped in situ is also applicable. Here, the polysilicon layer or amorphous silicon layer doped in situ does not need to be implanted with subsequent dopants, and may further inject dopants as necessary.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the nitride layer is formed on the exposed sidewall of the metal electrode through the nitriding process before patterning the silicon electrode, thereby preventing the external diffusion of dopants injected into the silicon electrode during the subsequent gate reoxidation process, thereby improving reliability of the semiconductor device. There is an effect that can be improved.

Claims (26)

Semiconductor substrates; A gate oxide film on the semiconductor substrate; A silicon electrode implanted with a dopant on the gate oxide film; A metal electrode and a gate hard mask stacked on the silicon electrode; An antioxidant layer formed on the exposed sidewall of the metal electrode; And An oxide layer formed on the exposed sidewalls of the silicon electrode A semiconductor device comprising a. The method of claim 1, The antioxidant layer, And nitriding the exposed sidewalls of the metal electrode. The method according to claim 1 or 2, And said metal electrode is tungsten and said antioxidant layer is a tungsten nitride film. The method according to claim 1 or 2, And said metal electrode is tungsten silicide and said antioxidant layer is WSiN. The method of claim 1, And said silicon electrode is a p + silicon electrode implanted with a p-type dopant. The method of claim 5, And the p-type dopant is selected from B, BF ₂ or BF. The method of claim 1, And the silicon electrode is an n + silicon electrode into which an n-type dopant is implanted. The method of claim 7, wherein And said n-type dopant is Ph or As. The method of claim 1, And said silicon electrode is a polysilicon layer or an amorphous silicon layer. A semiconductor substrate in which an NMOSFET region and a PMOSFET region are divided; A gate oxide film on the semiconductor substrate; An n + polysilicon electrode formed in the NMOSFET region on the gate oxide film and a p + polysilicon electrode formed in the PMOSFET region; A metal electrode and a gate hard mask stacked on the n + polysilicon electrode and the p + polysilicon electrode, respectively; A nitride layer formed on the exposed sidewall of the metal electrode; And An oxide layer formed on exposed sidewalls of the n + polysilicon electrode and the p + polysilicon electrode A semiconductor device comprising a. The method of claim 10, Wherein said metal electrode is tungsten and said nitride layer is a tungsten nitride film. The method of claim 10, And said metal electrode is tungsten silicide and said nitride layer is WSiN. The method of claim 10, The p + polysilicon electrode is a semiconductor device, characterized in that any one dopant selected from B, BF ₂ or BF is injected. The method of claim 10, The n + polysilicon electrode is a semiconductor device, characterized in that any one dopant selected from Ph or As is injected. Forming a gate insulating film on a semiconductor substrate in which an NMOSFET region and a PMOSFET region are divided; Forming a silicon electrode implanted with a dopant on the gate insulating film; Forming a metal electrode on the silicon electrode; Forming a gate hard mask on the metal electrode; A first gate patterning step of patterning the gate hard mask and the metal electrode; Forming an antioxidant layer on exposed sidewalls of the first patterned metal electrode; Performing second gate patterning to pattern the silicon electrode using the gate hard mask patterned by the first patterning as an etch barrier to form a gate structure in the NMOSFET region and the PMOSFET region, respectively; And Selectively oxidizing exposed sidewalls of the silicon electrode by performing a gate reoxidation process; Method for manufacturing a semiconductor device comprising a. The method of claim 15, Forming the antioxidant layer, A method of manufacturing a semiconductor device, characterized in that it proceeds through a nitriding process. The method of claim 16, The nitriding process, A method of manufacturing a semiconductor device, characterized in that it proceeds by plasma nitriding. The method of claim 17, The plasma nitridation, A method of manufacturing a semiconductor device, characterized by using microwave or high frequency plasma, and using a single gas or a mixed gas selected from N ₂ , NH ₃ , N ₂ O or NO as a source gas. The method of claim 18, A method of manufacturing a semiconductor device, comprising adding a rare gas selected from Ar, Kr or Xe to increase the efficacy of the plasma. The method of claim 18, In the plasma nitridation, A method for manufacturing a semiconductor device, wherein the power for forming plasma is 100 W to 5 kW, and the pressure is 1 tortor to 100 torr. The method of claim 16, The nitriding process, A method of manufacturing a semiconductor device, characterized in that it proceeds by thermal nitriding. The method of claim 21, The thermal nitriding, A method of manufacturing a semiconductor device, characterized by advancing using a gas selected from N ₂ , NH ₃ , N ₂ O, or NO as an atmospheric gas at a high temperature of 600 ° C. to 1300 ° C. The method of claim 15, The silicon electrode formed in the PMOSFET region A p-type polysilicon electrode implanted with a p-type dopant selected from B, BF ₂ or BF is a manufacturing method of a semiconductor device. The method of claim 15, The silicon electrode formed in the NMOSFET region, A method of manufacturing a semiconductor device, characterized by forming a polysilicon electrode into which an n-type dopant selected from Ph or As is implanted. The method of claim 15, And the metal electrode is formed of tungsten, and the antioxidant layer is formed of a tungsten nitride film. The method of claim 15, And the metal electrode is formed of tungsten silicide and the antioxidant layer is formed of WSiN.

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