KR100904000B1 - Method for monitoring solder of FBGA-type FPGA onto PCB - Google Patents

Abstract

The present invention relates to a method and apparatus for inspecting a solder contact state between an FPGA and a printed circuit board in a printed circuit board having a plurality of FPGAs mounted thereon.

Method and apparatus for checking the soldering contact state of an FBGA type FPGA and a printed circuit board according to the present invention reads and reads data written to another FPGA in one FPGA selected from a plurality of FPGAs mounted on the printed circuit board By comparing the test data with the test data, the solder contact state between the FPGA and the printed circuit board can be determined, and thus the solder contact state between the FBGA type FPGA and the printed circuit board can be determined accurately.

FPGA, FBGA, BGA, soldering

Description

Method for monitoring solder of FBGA-type FPGA onto PCB {Method for monitoring solder of FBGA-type FPGA onto PCB}

1 shows a cross section of a typical FBGA package.

FIG. 2 illustrates an example of solder that is in poor contact when a plurality of small and minute shoulder balls are soldered and contacted to a printed circuit board.

3 shows a functional block diagram of an apparatus for inspecting a solder contact state in accordance with one embodiment of the present invention.

4 illustrates an example of a time flow diagram of signals input and output from a plurality of FPGAs under control of a controller.

5 illustrates another example of a time flow diagram of signals input and output from a plurality of FPGAs under control of a controller.

6 shows a flowchart illustrating a method of inspecting a solder contact state according to an embodiment of the present invention.

Description of the main parts of the drawing

10: FPGA 12: PCB

13: shoulder ball 21: control unit

23: PCB 25: comparison unit

27: determination unit 29: output unit

The present invention relates to a method and apparatus for inspecting a solder contact state between an FPGA and a printed circuit board in a printed circuit board having a plurality of FPGAs mounted thereon.

Field Programmable Gate Array (FPGA) refers to the design and use of arbitrary logic circuits in circuits to operate as intended by the user. If the design changes during use, the new logic circuit is input to the FPGA device to operate with the changed logic circuit.

The trend in today's electronics industry is to make products that are lighter, smaller, faster, more versatile, more efficient and more reliable. One of the important technologies that enables the achievement of this product design goal is package assembly technology, and one of the recently developed packages is a ball grid array (BGA) package. Unlike conventional plastic packages, BGA packages use printed circuit boards instead of lead frames. The printed circuit board is advantageous in terms of mounting density because it can provide an area for placing shoulder balls on the front surface opposite to the surface to which the semiconductor chip is bonded. In addition, since the BGA package is electrically connected to the external circuit by the shoulder ball, the BGA package has improved electrical characteristics by minimizing the electrical signal transmission path. In addition, there is a fine pitch ball grid array (FBGA) package as a semiconductor package recently developed as a form to increase the mounting density.

FIG. 1 shows a cross section of a conventional FBGA package, as shown, wherein a conventional FBGA package has a window 5 such that the semiconductor chip 1 is directed down by an adhesive tape 7 so that its bonding pads 3 face down. It is attached on the board | substrate 2 provided with). In addition, the bonding pad 3 of the semiconductor chip 1 and the circuit pattern 4 of the substrate 2 are connected to each other by a bonding wire 6 passing through the window 5. In addition, the upper surface of the substrate 2 including the semiconductor chip 1 and the window 5 of the substrate 2 including the bonding wire 6 are molded with an encapsulant 8 such as an epoxy molding compound (EMC). The circuit pattern 4 on the bottom surface of the substrate 2 has a structure in which a plurality of small and minute shoulder balls 9 for mounting the substrate 2 are attached.

In the case where a plurality of small and fine shoulder balls 9 are soldered and contacted with a printed circuit board, soldering contact is poor as shown in FIG. 2A or the shoulder balls 9 as shown in FIG. 2B. It happens that these are shorted to each other.

Since the FPGA is in contact with the printed circuit board through the soldering of a plurality of fine shoulder balls 9, when writing or reading data to the FPGA in contact with the actual printed circuit board, It is difficult to check which of the shoulder balls 9 has a poor solder contact or a short circuit.

Accordingly, an object of the present invention is to provide a method and apparatus for accurately and simply inspecting a solder contact state between an FPGA and a printed circuit board in a printed circuit board having a plurality of FPGAs mounted thereon.

The method for inspecting a solder contact state for achieving the object of the present invention is a first step of controlling to write a predetermined test data to a first FPGA of a plurality of FPGA, the data recorded in the first FPGA a plurality of FPGA Control to write to another FPGA except the first FPGA, and compare the test data with the data recorded in the other FPGA except the first FPGA, and the plurality of FPGAs and the printing based on the comparison result. And a third step of determining a solder connection state of the circuit board. In this case, the first FPGA of the plurality of FPGAs is sequentially changed, and the first and second steps are repeatedly executed, and the solder connection state of the plurality of FPGAs and the printed circuit board is determined based on the result of the repeated execution. do.

Hereinafter, a method and an apparatus for inspecting a solder contact state between an FPGA and a printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings.

3 shows a functional block diagram of an apparatus for inspecting a solder contact state in accordance with one embodiment of the present invention.

Referring to FIG. 3, a plurality of FPGAs are mounted on the printed circuit board 23, and the plurality of FPGAs are connected to each other through circuit wiring of the printed circuit board 23. For convenience of description, an example in which four FPGAs are mounted on the printed circuit board 23 will be described.

When an inspection command for inspecting the solder contact state between the FPGAs and the printed circuit board 23 is input to the controller 21, the controller 21 controls to write / read predetermined test data to four FPGAs. . For example, the controller 21 selects one of four FPGAs, FPGA1, and controls to record test data, and controls to record the data recorded in the selected FPGA1 to the remaining FPGAs (FPGA2, FPGA3, and FPGA4). In addition, the controller 21 controls the comparator 25 to read the data recorded in the remaining FPGAs FPGA2, FPGA3, and FPGA4. The comparison unit 25 compares the read data with the test data and provides a comparison result to the determination unit 27.

The determination unit 27 determines that there is no abnormality in the solder contact state with the printed circuit board when the read data and the test data are the same based on the comparison result of the comparison unit 25, and the read data and the test data are In the case of different FPGAs, it is determined that a soldering contact with a printed circuit board or a circuit wiring with FPGA1 is abnormal. The determination result of the determination unit 27 is output through the output unit 29 such as a speaker, a display, and the like.

Preferably, the controller 21 alternately selects three FPGAs (FPGA2, FPGA3, FPGA4) that are not selected among the four FPGAs (FPGA1, FPGA2, FPGA3, and FPGA4) to control to repeat the same operation as described above. The determination unit 27 determines the soldering contact state of the plurality of FPGAs and the printed circuit board based on the repeated comparison result of selecting four FPGAs alternately.

 4 illustrates an example of a time flow diagram of signals input and output from a plurality of FPGAs under control of a controller.

Referring to FIG. 4, a control signal WC1 for selecting FPGA1 among four FPGAs FPGA1, FPGA2, FPGA3, and FPGA4, recording predetermined test data in the selected FPGA1, and writing the recorded data back into FPGA2. Are input to four FPGAs (FPGA1, FPGA2, FPGA3, FPGA4), respectively. The four FPGAs FPGA1, FPGA2, FPGA3, and FPGA4 determine whether they are selected based on the input control signal WC1. FPGA1 confirms that it has been selected, writes test data to FPGA1, and writes data (w1) written to FPGA1 back to FPGA2. When the FPGA2 receives the control signal RC1 to read the data w1 recorded in the FPGA2 from the controller, the FPGA2 reads the data r1 recorded therein and provides it to the comparator.

The control signal WC2 selects FPGA1 among the four FPGAs FPGA1, FPGA2, FPGA3, and FPGA4, writes predetermined test data to the selected FPGA1, and writes the recorded data back to FPGA3. , FPGA2, FPGA3, FPGA4). The four FPGAs FPGA1, FPGA2, FPGA3, and FPGA4 determine whether they are selected based on the input control signal WC2. FPGA1 confirms that it has been selected, writes test data to FPGA1, and writes data (w1) written to FPGA1 back to FPGA3. When the FPGA3 receives the control signal RC2 to read the data recorded in the FPGA3 from the controller, the FPGA3 reads the data r2 recorded therein and provides it to the comparator.

The control signal WC3 to select FPGA1 among the four FPGAs FPGA1, FPGA2, FPGA3, and FPGA4, write predetermined test data to the selected FPGA1, and write the recorded data back to the FPGA4, the four FPGAs (FPGA1). , FPGA2, FPGA3, FPGA4). The four FPGAs FPGA1, FPGA2, FPGA3, and FPGA4 determine whether they are selected based on the input control signal WC3. FPGA1 confirms that it has been selected, writes test data to FPGA1, and writes data (w1) written to FPGA1 back to FPGA4. When the FPGA4 receives the control signal RC3 for reading the data recorded in the FPGA4 from the controller, the FPGA4 reads the data r3 recorded in the FPGA4 and provides it to the comparator.

4 illustrates an example in which FPGA1 is selected from among four FPGAs (FPGA1, FPGA2, FPGA3, and FPGA4), but an unselected FPGA among four FPGAs (FPGA1, FPGA2, FPGA3, and FPGA4) is sequentially selected. The same control is repeated as when FPGA1 is selected above.

5 illustrates another example of a time flow diagram of signals input and output from a plurality of FPGAs under control of a controller.

Select FPGA1 out of the four FPGAs (FPGA1, FPGA2, FPGA3, FPGA4), write some test data to the selected FPGA1, and write the recorded data back to the other unselected FPGAs (FPGA2, FPGA3, FPGA4). The control signal WC1 is input to the four FPGAs FPGA1, FPGA2, FPGA3, and FPGA4, respectively. The four FPGAs FPGA1, FPGA2, FPGA3, and FPGA4 determine whether they are selected based on the input control signal WC1. FPGA1 confirms that it has been selected, writes test data to FPGA1, and writes data (w1) written to FPGA1 back to FPGA2, FPGA3, and FPGA4. When receiving the control signals RC1, RC2, and RC3 to read the data recorded in each of the FPGA2, FPGA3, and FPGA4, the FPGA2, FPGA3, and FPGA4 read the data (r1, r2, r3) recorded therein and provide them to the comparator.

FIG. 5 illustrates an example in which FPGA1 is selected among four FPGAs (FPGA1, FPGA2, FPGA3, and FPGA4), but an unselected FPGA among four FPGAs (FPGA1, FPGA2, FPGA3, and FPGA4) is sequentially selected. The same control is repeated as when FPGA1 is selected above.

The comparison unit 25 compares the test data and the read data provided in the manner described with reference to FIG. 4 or FIG. 5 to provide a comparison result to the determination unit 27, and the determination unit 27 based on four comparison results. Determine if the soldering contact between the FPGAs and the printed circuit board is abnormal.

For example, as a result of reading the data recorded from the FPGA1 to the remaining FPGAs (FPGA2, FPGA3, FPGA3) and comparing the test data, the data read from the FPGA2 and the test data are different from each other as shown in Table 1 below. If the data read from the FPGA3 and the FPGA4 and the test data are the same, it is determined that there is a fault in the circuit wiring connecting the FPGA1, the FPGA2, or the FPGA1 and the FPGA2.

TABLE 1

record Reading Comparison result FPGA1 ----> FPGA2 FPGA2 disparity FPGA1 ----> FPGA3 FPGA3 same FPGA1 ----> FPGA4 FPGA4 same

In addition, among the four FPGAs (FPGA1, FPGA2, FPGA3, and FPGA4), the unselected FPGAs are selected in turn, and the data recorded by the unselected FPGAs in the selected FPGA are read and compared with the test data. In the case of 2), it is finally judged that there is an abnormal soldering contact between FPGA1 and the printed circuit board.

TABLE 2

record Reading Comparison result FPGA2 -----> FPGA1 FPGA1 More than FPGA2 -----> FPGA3 FPGA3 normal FPGA2 -----> FPGA4 FPGA4 normal FPGA3 -----> FPGA1 FPGA1 More than FPGA3 -----> FPGA2 FPGA2 normal FPGA3 -----> FPGA4 FPGA4 normal FPGA4 -----> FPGA1 FPGA1 More than FPGA4 -----> FPGA2 FPGA2 normal FPGA4 -----> FPGA3 FPGA3 normal

On the other hand, among the four FPGAs (FPGA1, FPGA2, FPGA3, FPGA4) to select the non-selected FPGA in order to read the data recorded on the non-selected FPGAs in the selected FPGA compared to the test data is shown in Table 3 ), It is finally determined that there is an error in the data line connecting FPGA1 and FPGA2.

TABLE 3

record Reading Comparison result FPGA2 -----> FPGA1 FPGA1 More than FPGA2 -----> FPGA3 FPGA3 normal FPGA2 -----> FPGA4 FPGA4 normal FPGA3 -----> FPGA1 FPGA1 normal FPGA3 -----> FPGA2 FPGA2 normal FPGA3 -----> FPGA4 FPGA4 normal FPGA4 -----> FPGA1 FPGA1 normal FPGA4 -----> FPGA2 FPGA2 normal FPGA4 -----> FPGA3 FPGA3 normal

On the other hand, among the four FPGAs (FPGA1, FPGA2, FPGA3, FPGA4) to select the non-selected FPGA in order to read the data recorded on the non-selected FPGAs in the selected FPGA compared to the test data is shown in Table 4 ), It is finally determined that the solder contact between the FPGA2 and the printed circuit board is abnormal.

record Reading Comparison result FPGA2 -----> FPGA1 FPGA1 More than FPGA2 -----> FPGA3 FPGA3 More than FPGA2 -----> FPGA4 FPGA4 More than FPGA3 -----> FPGA1 FPGA1 normal FPGA3 -----> FPGA2 FPGA2 More than FPGA3 -----> FPGA4 FPGA4 normal FPGA4 -----> FPGA1 FPGA1 normal FPGA4 -----> FPGA2 FPGA2 More than FPGA4 -----> FPGA3 FPGA3 normal

6 shows a flowchart illustrating a method of inspecting a solder contact state according to an embodiment of the present invention.

Referring to FIG. 6, one FPGA is selected from among a plurality of FPGAs mounted on a printed circuit board (step 1). Hereinafter, a case where four FPGAs (FPGA1, FPGA2, FPGA3, and FPGA4) are mounted on a printed circuit board will be described as an example. A control signal for selecting one of the four FPGAs (FPGA1, FPGA2, FPGA3, and FPGA4) is input to each of the FPGAs, and based on the control signal, each of the FPGAs confirms whether it is selected.

When FPGA1 is selected from four FPGAs (FPGA1, FPGA2, FPGA3, and FPGA4), control is performed to write predetermined test data to the selected FPGA1 (step 2). For example, the test data may be 0X00, 0XFF, 0X55, or 0XAA. The data recorded in the selected FPGA1 is controlled to be sequentially or simultaneously recorded to the unselected FPGAs FPGA2, FPGA3, and FPGA4 (step 3). Preferably, the control signal includes a command for selecting one of a plurality of FPGAs, a command for indicating a type of test data to be recorded, and a command for selecting an FPGA to rewrite data recorded in the selected FPGA. This is included.

Data recorded in the non-selected FPGAs (FPGA2, FPGA3, FPGA4) is read (step 4), and the read data is compared with the test data to provide a comparison result to the determination unit (step 5).

When reading the data recorded by the non-selected FPGAs (FPGA2, FPGA3, FPGA4) from the selected FPGA1 and comparing it with the test data, the non-selected FPGAs (FPGA2, FPGA3, FPGA4) are changed and selected in sequence (step 6) It is determined whether all FPGAs (FPGA1, FPGA2, FPGA3, FPGA4) mounted on the printed circuit board are changed in sequence and are all selected (step 7). If all the FPGAs (FPGA1, FPGA2, FPGA3, FPGA4) are changed in sequence and not all selected, the above steps 1 to 6 are repeated. On the other hand, when all the FPGAs (FPGA1, FPGA2, FPGA3, FPGA4) are changed in sequence, and all selected, based on the comparison result for each FPGA (FPGA1, FPGA2, FPGA3, FPGA4), a plurality of FPGAs (FPGA1, FPGA2, The solder contact state between the FPGA3 and the FPGA4) and the printed circuit board is determined (step 8).

Meanwhile, the above-described embodiments of the present invention can be written as a program that can be executed in a computer, and can be implemented in a general-purpose digital computer that operates the program using a computer-readable recording medium.

The computer-readable recording medium may be a magnetic storage medium (for example, a ROM, a floppy disk, a hard disk, etc.), an optical reading medium (for example, a CD-ROM, DVD, etc.) and a carrier wave (for example, the Internet). Storage medium).

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The method and apparatus for determining a solder contact state between an FBGA type FPGA and a printed circuit board according to the present invention read and read data written to another FPGA from one FPGA selected from among a plurality of FPGAs mounted on the printed circuit board. By comparing the solder contact state between the FPGA and the printed circuit board by comparing the data with the test data, it is possible to accurately and easily determine the solder contact state between the FBGA type FPGA and the printed circuit board.

Claims (7)

In a method for checking the solder connection state of the FPGA and the printed circuit board in a printed circuit board mounted with a plurality of FPGA, (a) selecting one of the plurality of FPGAs and writing test data to the selected FPGA; (b) recording the data recorded in the selected FPGA to the remaining FPGAs other than the selected FPGA; (c) comparing the test data with the data recorded in the remaining FPGA; And (d) determining a solder connection state of the plurality of FPGAs mounted on the printed circuit board based on the comparison result. The method of claim 1, The steps of (a) and (b) are repeated by sequentially changing the selected FPGA, And a solder connection state of the plurality of FPGAs and the printed circuit board is determined based on the result of the repeated execution. In a method for checking the solder connection state of the FPGA and the printed circuit board in a printed circuit board mounted with a plurality of FPGA, (a) selecting a first FPGA among the plurality of FPGAs and writing test data to the selected first FPGA; (b) writing data recorded on the selected first FPGA to a second FPGA; (c) comparing the test data with data written to the second FPGA; (d) repeating steps (b) and (c) while modifying the second FPGA, Determining a solder connection state of the plurality of FPGAs mounted on the printed circuit board based on the comparison result. The method of claim 3, wherein Repeating steps (a) and (d) while sequentially changing the selected first FPGA, And a solder connection state of the plurality of FPGAs and the printed circuit board is determined based on the result of the repeated execution. The method of claim 1 or 3, wherein the FPGA A method for inspecting a soldering connection state, which is mounted on the printed circuit board according to a ball grid array (BGA) or fine fitch ball grid array (FBGA) method. An apparatus for inspecting a solder connection state between a plurality of FPGAs and a printed circuit board in a printed circuit board on which a plurality of FPGAs are mounted, A control unit which selects one of the plurality of FPGAs to record test data with the selected FPGA, writes the data recorded in the selected FPGA to another FPGA except the selected FPGA, and reads the data recorded in the other FPGA; A comparator for comparing the read data with the test data to generate a comparison result; And And a determination unit that determines a solder connection state of the plurality of FPGAs and the printed circuit board based on the comparison result. delete

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