KR100898870B1 - Liquid Cystal Display - Google Patents

Abstract

According to an exemplary embodiment of the present invention, a liquid crystal display includes a timing controller configured to receive odd and even data and a data clock from an external source, and output continuous data and one or more source sampling clocks without separation of odd and even numbers, and connected to the timing controller. And a driver circuit including a plurality of driver integrated circuits driving the liquid crystal panel by the continuous data output from the timing controller and one or more source sampling clocks, and a liquid crystal panel displaying an image by the data output from the driving circuit. Characterized in that it is included.

According to the present invention, it is possible to reduce the number of input pins of the driver integrated circuit, thereby reducing the size of the printed circuit board (PCB) and the driver integrated circuit, it is also possible to obtain the effect of reducing the material cost by reducing the number of lines. .

Description

Liquid Crystal Display {Liquid Cystal Display}

1 is a block diagram of a conventional liquid crystal display device.

FIG. 2 is a timing diagram illustrating a concept of frequency division of the data clock frequency of FIG. 1. FIG.

3 is an operation timing diagram according to a driving method of a conventional liquid crystal display shown in FIG. 1.

4 is a block diagram of a liquid crystal display device according to the present invention;

5 is an operation timing diagram according to a driving method of a liquid crystal display according to the present invention shown in FIG.

<Explanation of symbols for the main parts of the drawings>

10, 40: timing controller 11, 41: data clock

12: cardinal data 13: excellent data

14: Left source sampling clock 15: Right source sampling clock

16, 46 left driver integrated circuit 17, 47 right driver integrated circuit

18, 48: data driver integrated circuit 19, 49: data driver circuit

20, 50: gate driver integrated circuit 21, 51: gate driver circuit

22, 52: liquid crystal panel 42, 42 ': radix and storm data

44: Radix Source Sampling Clock 45: Excellent Source Sampling Clock

The present invention relates to a liquid crystal display device in which the number of data lines input to a driver integrated circuit (D-IC) is reduced.

 The liquid crystal display has an inherent resolution corresponding to the number of pixels, and as the size of the liquid crystal display increases, the resolution increases.

In general, the frequency of the allowable input data clock of the driver integrated circuits applying data to the liquid crystal panel is approximately 45 MHz to 60 MHz, but the frequency of the data clock DCLK transmitted to the liquid crystal display in a system having a video card is determined at XGA resolution. 65 MHz, 108 MHz at SXGA resolution and 160 MHz at UXGA resolution.

Therefore, in order to reduce the frequency of a high data clock, a recent liquid crystal display device divides input and output data in parallel and simultaneously transmits data through a plurality of transmission lines to drive frequency of driver integrated circuits (D-ICs). Is reducing.

FIG. 1 is a block diagram of a conventional liquid crystal display device, and shows a liquid crystal display device having XGA resolution.

In the conventional liquid crystal display shown in FIG. 1, in order to reduce the driving clock frequency of the liquid crystal display as described above, for example, two pixels of data divided into odd and even pixel data are first divided from the system through an interface. At the same time, the data clock frequency is 32.5MHz, which is lower than the 65MHz data clock frequency of the original video signal. This is explained in more detail with reference to FIG. 2.

FIG. 2 is a timing diagram illustrating a concept of frequency division of the data clock frequency of FIG. 1. Referring to FIG. 2, in the conventional case, data of each pixel (b) were output in synchronization with a conventional data clock (a) that is not divided, that is, a clock having a frequency of 65 MHz. The two-pixel data divided into odd and even pixel data (d, e) are simultaneously inputted, and the frequency is 32.5 MHz, which is half the frequency of the conventional data clock (a). Two divided data clocks c are input.

Such a driving method is referred to as a two-port driving method or a six-bus driving method because two pixels of data 2d and 2e are simultaneously output.

As described above, this reduces the frequency of the high data clock, divides the input and output data in synchronization with each other in parallel, and transmits the data simultaneously through a plurality of transmission lines to drive the driver integrated circuits (D-ICs). This is to reduce the frequency.

Referring to FIG. 1, a timing controller 10 receives input odd and even data 12 and 13 and a data clock 11 in synchronization with the data clock 11. The odd and even data 12 and 13 are supplied to a data driving circuit 19 including ten data driver integrated circuits 18 (D1 to D10), and then the data driving circuit 19 receives the input data. The liquid crystal panel 22 is driven together with the gate driving circuit 21 including the m gate driver integrated circuits 20 (G1 to Gm) to display an image.

In addition, the data driver integrated circuit 18 (D1 to D10) receives a source sampling clock from the timing controller 10 to latch the odd and even data 12 and 13, wherein the data driver integrated circuit (18) It is not necessary to make 10 (D1-D10) ten, but only 10 is made for convenience in FIG.

When the ten data driver integrated circuits 10 (D1 to D10) are referred to as D1, D2 to D9, and D10 from the left side, D1 to D5 are responsible for driving the left side of the liquid crystal panel 22, and D6 to D10 are liquid crystal panels. It is responsible for driving the right side of 22, and two source sampling clocks are required for driving the left and right liquid crystal panels.

3 is an operation timing diagram according to a driving method of the conventional liquid crystal display shown in FIG. 1.

Referring to FIG. 3, a driving method of the conventional liquid crystal display shown in FIG. 1 will be described in more detail.

In the odd and even data (12, 13) output from the timing controller (10), D1 is located on the leftmost side of the left driver integrated circuit (16) D1-D5 that is responsible for driving the left side of the liquid crystal panel (22). The first data input to the data, that is, the data corresponding to the first radix and the even data (1-P0, 1-P1) are output first, and then the right part responsible for driving the right side of the liquid crystal panel 22 successively. The first data input to the leftmost D6 of the driver integrated circuits D6 to D10, that is, the data 6-P0 and 6-P1 corresponding to the first odd and even data, are next output.                         

The odd and even data 12 and 13 outputted from the timing controller 10 are located at the leftmost side of the left and right driver integrated circuits 16 and 17 of the liquid crystal panel 22 by the method described above. When the input is sequentially input to the channels of D6, and is input to all of the channels of D1 and D6, the output is sequentially input to the data driver integrated circuits to the right of the D1 and D6, that is, D2 and D7. As a result, the data is output to the channels of D5 and D10, and eventually, the image data of one line of the liquid crystal panel is input.

In this case, the data output from the timing controller 10 is not directly input to the data driver integrated circuit, but is latched by the source sampling clock.

In FIG. 3, 1-P0 denotes the first radix data of the data driver integrated circuit D1, 6-P0 denotes the first radix data of the data driver integrated circuit D6, and similarly, 1-P1 denotes the data driver integrated circuit. The first even data of D1, and 6-P1 means the first even data of the data driver integrated circuit D6.

As can be seen from the timing diagram, respective odd and even data are simultaneously input to the data driver integrated circuit, and the odd and even data are sequentially inputted from the data driver integrated circuits D1 and D6 to D5 and D10. .

As described above, the odd and even data 12 and 13 output from the timing controller 10 are left source sampling clock 14 (Left_Source Sampling Clock: SSCL) or right source sampling clock 15 (Right_Source Sampling Clock: SSCR). Is latched and input to the data driver integrated circuit 18.

That is, the odd and even data input to the left driver integrated circuits 16 D1 to D5 that are responsible for driving the left side of the liquid crystal panel 22 are generated by the rising edge of the left source sampling clock 14 (SSCL). The odd and even data inputted to the right side driver integrated circuit 17 D6 to D10 simultaneously and simultaneously inputted to the right side of the liquid crystal panel 22 are connected to the right source sampling clock 15 (SSCR). It is synchronized with the rising edge and input at the same time.

As a result, the outputs of the two ports from the timing controller 10, that is, the respective odd and even data 12 and 13, must all be input to the ten data driver integrated circuits 18.

However, the above-described conventional liquid crystal display device and driving method can reduce the driving frequency in the liquid crystal display device, but as the data output increases, the amount of data simultaneously output increases. For example, in a liquid crystal display device using 8-bit data, in the case of the two-port driving method as described above, a 48-bit line (48 bit line = 2 ports * 3 (R, G, B) * 8 bits) is simultaneously received from the timing controller. The data is output through. At this time, the transient current is generated in the timing controller during the data-to-data switching process (high-low), and the increase in the number of lines increases the material cost and the size of the PCB and the data driver integrated circuit. have.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display that can reduce the size of a printed circuit board (PCB) and the driver integrated circuit by reducing the number of data lines from the output of the timing controller to the driver integrated circuit input.

In order to achieve the above object, a liquid crystal display according to the present invention includes a timing controller for receiving odd and even data and a data clock from outside, and outputting continuous data and one or more source sampling clocks without separation of odd and even numbers; ,

A driving circuit connected to the timing controller and including a plurality of driver integrated circuits driving the liquid crystal panel by the continuous data and the one or more source sampling clocks output from the timing controller;

And a liquid crystal panel for displaying an image by data output from the driving circuit.

In addition, the source sampling clock output from the timing controller is an odd source sampling clock and even source sampling clock for separating continuous data of the odd and even numbers separately, respectively, and the odd source sampling clock and the even source sampling clock. The clock is characterized in that the clock is out of phase with each other.

In addition, the plurality of driver integrated circuits may be divided into a left driver integrated circuit and a right driver integrated circuit to perform left and right driving of the liquid crystal panel.                     

In addition, continuous data without separation of odd and even numbers outputted from the timing controller are separately input into the left driver integrated circuit and the right driver integrated circuit, respectively, and the odd source sampling clock and the even source sampling clock are respectively inputted to each other. It is input to both the left driver integrated circuit and the right driver integrated circuit.

According to the present invention, it is possible to reduce the number of input pins of the driver integrated circuit, thereby reducing the size of the printed circuit board (PCB) and the driver integrated circuit, it is also possible to obtain the effect of reducing the material cost by reducing the number of lines. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a liquid crystal display device according to the present invention, and shows a liquid crystal display device having XGA-class resolution.

Also in the liquid crystal display according to the present invention shown in FIG. 4, as in the prior art, in order to reduce the driving clock frequency of the liquid crystal display, for example, two pixels divided into odd and even pixel data are first divided from the system through an interface. The data is simultaneously input, and the frequency of the data clock at this time is 32.5 MHz, which is lower than the 65 MHz data clock frequency of the original video signal.

However, the point of distinction from the conventional technology is that the data clock 11 divided into two divided data of odd data 12 and even data 13, that is, the frequency is halved as shown in FIG. In synchronization with the data clock, the timing controller 10 does not divide and output the data simultaneously, and the odd and even data are not continuously divided and outputted. That is, the data output from the timing controller 40 of the present invention is continuous data 42, 42 'without separation of odd and even. .

This overcomes the need for a plurality of transmission lines, which is a disadvantage of the two-port driving method or the six-bus driving method, in which data of two pixels are simultaneously output. The configuration of the liquid crystal display according to the present invention will be described with reference to FIG. 4.

The timing controller 40 receives the inputted odd and even data 12 and 13 and the data clock 41 and outputs the odd and even data in synchronization with the data clock 41. In the embodiment of the present invention, the output is successively performed without dividing it.

The continuous data 42 and 42 'without separation of odd and even numbers are supplied to a data driving circuit 49 including ten data driver integrated circuits 48 (D1 to D10). The furnace 49 displays an image by driving the liquid crystal panel 52 together with the gate driving circuit 51 including the input data of m gate driver integrated circuits 50 (G1 to Gm).

In addition, the data driver integrated circuit 48 (D1 to D10) receives a source sampling clock (SSC) from the timing controller 40 and performs continuous data 42 without separation of the odd and even numbers. 42 '). For this purpose, the timing controller 40 separates the radix source sampling clock 44 (Odd_) so that the continuous data 42 and 42' without separation of the odd and even numbers are separated and corresponded, respectively. The source sampling clock (SSCO) and the even source sampling clock 45 (Even_Source Sampling Clock: SSCE) are respectively output.

That is, when the continuous data 42, 42 'without separation of odd and even is input to the data driver integrated circuit 48, the odd source sampling clock 44 (SSCO) and even source sampling clock 45 (SSCE) separates and synchronizes the odd data and the even data 42 and 42 ', respectively.

Here, the odd source sampling clock 44 and the even source sampling clock 45 are clocks that are out of phase with each other. The odd and even data are synchronized at the rising edge of the source sampling clock. The odd and even data 42, 42 'are continuously outputted in order to separately synchronize and synchronize the odd and even data. This is because a constant time difference must be maintained at the rising edge of the sampling clock 44 and the even source sampling clock 45.

Therefore, if a certain time difference is maintained at the rising edge of the odd source sampling clock 44 and the even source sampling clock 45, the odd source sampling clock 44 and the even source sampling clock 45 must be out of phase with each other. The opposite clock need not be limited to being used.

 In addition, although the data driver integrated circuits 48 (D1 to D10) are 10 in FIG. 4, the data driver integrated circuits 48 (D1 to D10) are not necessarily 10, but only 10 are shown in FIG. 4 for convenience.                     

When the ten data driver integrated circuits 48 (D1 to D10) are referred to as D1, D2 to D9, and D10 from the left side, D1 to D5 are responsible for driving the left side of the liquid crystal panel 52, and D6 to D10 are liquid crystal panels. The right side driving of 52 is performed, and therefore, the left side driver integrated circuit 46 is referred to as D1 through D5, and the right side driver integrated circuit 47 is referred to as D6 through D10.

Here, the continuous odd and even data 42, 42 ′ output from the timing controller 40 are separately inputted into the left driver integrated circuit 46 and the right driver integrated circuit 47, respectively. The odd source sampling clock 44 and the even source sampling clock 45 are input to both the left driver integrated circuit 46 and the right driver integrated circuit 47.

That is, the left side driver integrated circuit 46 receives continuous odd and even data 42, the odd source sampling clock 44, and the even source sampling clock 45 input to the left side, and the right side driver integrated circuit 47. ), Continuous odd and even data 42 ', odd source sampling clock 44, and even source sampling clock 45 inputted to the right side are input.

Assuming that 1024 pieces of data are input to the data driver integrated circuit 48, consecutive radix numbers 1 to 512 and even data 42 are input to the left side, and continuous radix numbers 513 to 1024 are input. And the even data 42 'are input to the right side, and the odd and even data 42 and 42' which are respectively inputted are the odd data and the even source sampling clock 44 and the even source sampling clock 45, respectively. Even data 42 and 42 'are divided and synchronized. 5 is an operation timing diagram according to the driving method of the liquid crystal display according to the present invention shown in FIG.

Referring to FIG. 5, the driving method of the liquid crystal display according to the present invention shown in FIG. 4 will be described in more detail.

In the continuous data 42, 42 ′ without separation of odd and even outputs output from the timing controller 40, left driver integrated circuits 46 D1 to D5 that are responsible for driving the left side of the liquid crystal panel 52. The first data input to D1 positioned at the leftmost of the data, that is, the data corresponding to the first radix data (1-P0) is first outputted, and subsequently, the data corresponding to the first even-numbered data (1-P1) Will be output.

In addition, the first cardinal data (1-P0) input to D1 positioned on the leftmost side of the left driver integrated circuit 46 is output, and the right driver integrated circuit responsible for driving the right side of the liquid crystal panel 52 is output. (47) The first data input to D6 located at the leftmost of D6 to D10, that is, the data corresponding to the first radix data (6-P0) is output, and next to the first storm data inputted at the right side. The corresponding data 6-P1 is output.

Continuous data without separation of odd and even numbers outputted from the timing controller 40 can be stored in the leftmost and leftmost portions of the driver integrated circuits 46 and 47 of the liquid crystal panel by the method described above. When the input is sequentially input to the channels, the inputs are sequentially input to the channels of the D1 and D6, and are sequentially output to the data driver integrated circuits on the right side of the D1 and D6, that is, the D2 and D7 in the same manner as described above. The data is output to the channels of D5 and D10, and eventually output to input all the image data of one line of the liquid crystal panel.

That is, assuming that 1024 data are input to the data driver integrated circuit 48, consecutive odd and even data 42 from 1 to 512 are sequentially input to the left driver integrated circuit 46. Continuous odd and even data 42 'from No. 513 to No. 1024 are sequentially input to the right side driver integrated circuit 47.

Here, the data output from the timing controller 40 is not directly input to the data driver integrated circuit 48 but is latched by the source sampling clock.

This means that successive radix and even data 42 and 42 'which are respectively inputted are divided and synchronized with radix and even data by the radix source sampling clock 44 and even source sampling clock 45, respectively. .

In FIG. 5, 1-P0 denotes the first radix data of the data driver integrated circuit D1, 6-P0 denotes the first radix data of the data driver integrated circuit D6, and similarly, 1-P1 denotes the data driver integrated circuit. The first even data of D1, and 6-P1 means the first even data of the data driver integrated circuit D6.

As can be seen from the timing diagram, continuous odd and even data 42, 42 'input to the left and right driver integrated circuits 46 and 47 are simultaneously input to the data driver integrated circuits D1 and D6. The continuous radix and storm data are sequentially inputted to D5 and D10.

In addition, successive radix and even data 42 and 42 'which are sequentially input to the left and right portions as described above are radix source sampling clock 44 (Odd_Source Sampling Clock: SSCO) and even source sampling clock 45 The latch is latched by the Even Source Source Clock (SSCE) and input to the data driver IC 48.

That is, the odd data input to the left driver integrated circuits D1 to D5 which are responsible for driving the left side of the liquid crystal panel are sequentially input in synchronization with a rising edge of the odd source sampling clock SSCO. At the same time, the odd data input to the right side driver integrated circuits D6 to D10 which are responsible for the right driving of the liquid crystal panel are also sequentially input in synchronization with the rising edge of the odd source sampling clock SSCO.

Similarly, the even data input to the left driver integrated circuits D1 to D5 are sequentially inputted in synchronization with a rising edge of the even source sampling clock SSCE, and at the same time, the right driver driver integrated circuit D6. The even data input to D10 is also sequentially input in synchronization with the rising edge of the even source sampling clock SSCE.

As a result, continuous odd and even data 42 and 42 'from the timing controller 40 are inputted into the ten data driver integrated circuits in the left and right parts, and the data are the odd and even source sampling. It is latched by the clocks 44 and 45.

Therefore, according to the present invention, not only the driving frequency in the liquid crystal display device can be reduced, but also the amount of data to be output can be prevented from increasing. For example, in the liquid crystal display device using 8-bit data, in the case of the driving method according to the present invention as described above, a 24-bit line (24 bit line = 1 port * 3 (R, G, B) * 8 bit) from the timing controller simultaneously. ) Is outputted. In this case, the transient current is prevented from occurring in the timing controller during the high-low data switching process, and the increase in the number of lines increases the material cost and the size of the PCB and the data driver integrated circuit. Will overcome.

According to the liquid crystal display and the driving method according to the present invention as described above, the number of driver integrated circuit input pins can be reduced, thereby reducing the size of the printed circuit board (PCB) and the driver integrated circuit, and also the number of lines The reduction of material cost can be achieved.

Claims (5)

A timing controller that receives odd and even data and data clocks from the outside and outputs continuous data and one or more source sampling clocks without separation of odd and even numbers; A driving circuit connected to the timing controller and including a plurality of driver integrated circuits driving the liquid crystal panel by the continuous data and the one or more source sampling clocks output from the timing controller; It includes a liquid crystal panel for displaying an image by the data output from the drive circuit, The source sampling clock output from the timing controller is an odd source sampling clock and an even source sampling clock for separating continuous data without separation of odd and even numbers, respectively. The plurality of driver integrated circuits may be divided into a left driver integrated circuit and a right driver integrated circuit to perform left and right driving of the liquid crystal panel. delete The method of claim 1, And the odd source sampling clock and the even source sampling clock are clocks of opposite phases to each other. delete The method of claim 1, Continuous data without separation of odd and even numbers outputted from the timing controller are separately input into the left driver integrated circuit and the right driver integrated circuit, and the odd source sampling clock and the even source sampling clock are respectively input to the left driver. The liquid crystal display device, which is input to both an integrated circuit and a right side driver integrated circuit.

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