KR100894370B1 - Display device - Google Patents

Abstract

A liquid crystal display device corresponding to high frequency is realized. A plurality of drain electrode lines and a plurality of gate electrode lines are arranged in a matrix shape, and have a pixel region formed by being surrounded by two adjacent two drain electrode lines and two adjacent ones of the gate electrode lines, each pixel region having a TFT element, A display device in which a display area is set as a set, wherein the direction in which the TFT elements are disposed with respect to the drain electrode line is reversed every time the gate electrode line is crossed in the extending direction of the drain electrode line, and the gate electrode line is placed outside the display area. Every two crossings has an area in which TFT elements are arranged.

Liquid crystal display device, drain electrode line, gate electrode line, pixel area, TFT element, pixel electrode, dummy pixel, effective display area

Description

Display device {DISPLAY DEVICE}

BRIEF DESCRIPTION OF THE DRAWINGS The front view which shows the structural example of a liquid crystal display panel as a schematic diagram which shows an example of schematic structure of the display panel which the display apparatus to which this invention is applied has.

2 is a cross-sectional view taken along the line AA ′ of FIG. 1.

3 is a schematic diagram showing a circuit configuration of a TFT substrate of one embodiment according to the present invention;

4 is a diagram showing an example of a time chart of a signal applied to the drain electrode line DL ₁ of the display panel of this embodiment.

FIG. 5 is a diagram showing an example of a time chart of signals applied to the drain electrode line DL _{3m + 1} of the display panel of this embodiment.

FIG. 6 is a diagram illustrating another example of a time chart of a signal applied to the drain electrode line DL ₁ of the display panel of this embodiment.

FIG. 7 is a diagram showing another example of a time chart of a signal applied to the drain electrode line DL _{3m + 1} of the display panel of this embodiment.

Fig. 8 is a schematic diagram showing a configuration example of a TFT substrate to which the circuit configuration of this embodiment is applied, and an enlarged plan view of the end of the effective display area.

FIG. 9 is a cross-sectional view taken along the line BB ′ of FIG. 8. FIG.

Fig. 10 is a schematic diagram for explaining a first modification of the embodiment, showing a circuit configuration of a TFT substrate.

Fig. 11 is a schematic diagram for explaining a second modification of the embodiment, showing a circuit configuration of a TFT substrate.

FIG. 12 is an enlarged plan view showing a configuration example of a TFT substrate to which the circuit configuration of FIG. 11 is applied;

FIG. 13 is a cross-sectional view taken along the line CC ′ in FIG. 12. FIG.

Fig. 14 is a schematic diagram for explaining a third modification of the embodiment, showing a circuit configuration of a TFT substrate.

Fig. 15 is a schematic diagram for explaining a third modification of the above embodiment, showing another example of the circuit configuration of the TFT substrate.

Fig. 16 is a schematic diagram for explaining a third modification of the above embodiment, showing another example of the circuit configuration of the TFT substrate.

FIG. 17 is an enlarged plan view showing a configuration example of a TFT substrate to which the circuit configuration of FIG. 15 is applied;

18 is a cross-sectional view taken along the line D-D 'of FIG. 17;

Fig. 19 is a schematic diagram for explaining a fourth modification of the embodiment, showing a circuit configuration of a TFT substrate.

Fig. 20 is a schematic diagram for explaining a fourth modification of the embodiment, showing another example of the circuit configuration of the TFT substrate.

Fig. 21 is a schematic diagram for explaining a fourth modification of the embodiment, showing another example of the circuit configuration of the TFT substrate.

Fig. 22 is an enlarged plan view showing a configuration example of a TFT substrate to which the circuit configuration of Fig. 20 is applied.

FIG. 23 is a cross-sectional view taken along the line E-E 'of FIG. 22;

24 is an enlarged plan view showing another configuration example of a TFT substrate to which the circuit configuration of FIG. 20 is applied.

25 is a cross-sectional view taken along the line FF ′ in FIG. 24.

Fig. 26 is a schematic diagram for explaining a fifth modification of the embodiment, which shows a circuit configuration of a TFT substrate.

Fig. 27 is a schematic diagram for explaining a fifth modification of the embodiment, showing another example of the circuit configuration of the TFT substrate.

Fig. 28 is a schematic diagram for explaining a fifth modification of the embodiment, showing another example of the circuit configuration of the TFT substrate.

29 is an enlarged plan view showing a configuration example of a TFT substrate to which the circuit configuration of FIG. 27 is applied;

30 is a cross-sectional view taken along the line G-G 'of FIG. 29;

Fig. 31 shows the circuit configuration of a conventional TFT substrate.

<Explanation of symbols for the main parts of the drawings>

1: substrate

101: glass substrate

102: first interlayer insulating film

103: semiconductor layer

104: a second interlayer insulating film

2: CF substrate

3: sealing material

4: liquid crystal material

GL: Gate electrode wire

DL: drain electrode wire

CL: Common signal line

PX: pixel electrode

PXd: dummy pixel electrode

CT: common electrode

SL: source electrode

BR: Bridge wiring

DP1: First dummy pixel

DP2: second dummy pixel

DP3: Third dummy pixel

[Patent Document 1] Japanese Patent Application Laid-Open No. 10-90712

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a technology effective by applying to a display device having a display panel in which TFT elements are arranged pixel by pixel.

BACKGROUND ART Conventionally, display devices such as televisions have a liquid crystal display device using a liquid crystal display panel.

The liquid crystal display panel is a display panel in which a liquid crystal material is sealed between a pair of substrates. At this time, for example, TFT elements or pixel electrodes are arranged in pixel units on one substrate. Further, on the other substrate, for example, a color filter is disposed at a position facing the pixel electrode.

In this case, the circuit configuration on the substrate on which the TFT elements and the like are arranged is, for example, as shown in FIG. One drain electrode line DL and n + 1 gate electrode line GL are disposed. 31 shows a case where one dot is composed of three pixels of R pixels, G pixels, and B pixels. In FIG. 31, the drain electrode line DL _{3m + 1} at the right end of the page and the gate electrode line GL _{n + 1} at the bottom of the page are dummy.

In this liquid crystal display panel, for example, as shown in FIG. 31, the TFT elements of each pixel arranged along the extending direction of the drain electrode line DL are all connected to the same drain electrode line. For example, in the TFT element of the pixel R is listed along with the drain electrode line (DL ₁₎ are all connected to the drain electrode line (DL _1).

On the other hand, Patent Document 1 describes an example in which TFTs are alternately arranged on adjacent drain electrode lines.

Background Art [0002] In the liquid crystal display devices such as televisions, high refresh rates have been developed to suppress flickering of screens and to improve display performance of moving images.

However, when the circuit configuration on the display panel is the configuration as shown in Fig. 31, there is a problem that the writing shortage of the TFT elements occurs as the high refresh rate progresses and the image quality deteriorates.

An object of the present invention is to provide a technique capable of reducing the deterioration of image quality due to, for example, high frequency operation of a liquid crystal display device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

The outline of the invention disclosed in the present application is as follows.

(1) A display device having a display panel in which TFT elements and pixel electrodes are arranged in units of pixels, wherein the display panel has an extension direction of the drain electrode line outside one end of the extension direction of the gate electrode line among the ends of the effective display area. A first dummy pixel having a TFT element connected to an even numbered gate electrode line from one end thereof is disposed, and in the extension direction of the drain electrode line outside the other end of the effective direction of the gate electrode line in the extending direction of the gate electrode line. Second dummy pixels having TFT elements connected to the odd-numbered gate electrode lines are arranged from the one end portion, and in each drain electrode line, TFT elements of each pixel arranged on both sides are alternately connected along the extension direction. Each of the drain electrode lines at an end portion of the gate electrode line in the extending direction includes a TFT element disposed in an effective display area and a first or second dummy. It is a display device in which pixels are alternately connected along the extension direction.

(2) In the above (1), an end where the first dummy pixel is disposed is a display device on the input end side of the gate electrode line.

(3) In the above (1) or (2), the first and second dummy pixels are the display devices having the same configuration as the pixels in the effective display area.

(4) In the above (1) or (2), the first and second dummy pixels are display devices having only TFT elements.

(5) The display device according to any one of (1) to (4), having a dummy drain electrode line outside the first or second dummy pixel.

(6) The display device according to any one of (1) to (5), wherein a third dummy pixel is disposed between the first dummy pixel or between the second dummy pixel.

(7) In (6), the third dummy pixel is a display device having a dummy electrode layer on the same conductive layer as the pixel electrode of a pixel in the effective display area.

(8) In (7), the third dummy pixel is a display device having a TFT element connected to the dummy drain electrode line and the dummy electrode layer.

(9) A plurality of drain electrode lines and a plurality of gate electrode lines are arranged in a matrix, and have pixel regions formed by being surrounded by two adjacent two drain electrodes and two adjacent ones of the gate electrode lines, each pixel region comprising a TFT element. In the display device in which the display area is set as the set of the pixel areas, the direction in which the TFT elements are disposed with respect to the drain electrode line is inverted every time the gate electrode line is crossed in the extending direction of the drain electrode line. A display device having a region in which TFT elements are arranged each time the two gate electrode lines cross each other outward.

(10) The display device according to (9), wherein a region where TFT elements are arranged is shielded every time two gate electrode lines are crossed.

(11) In the above (9) or (10), each time the two gate electrode lines are crossed, the region where the TFT elements are arranged is deviated by one gate electrode line from the left outer side and the right outer side of the display area. It is a display device.

(12) The display device according to any one of (9) to (11), wherein a signal having the same polarity is applied to the drain electrode line in one frame period.

(13) The display device according to (12), wherein signals of opposite polarities are applied to two adjacent drain electrode lines.

(14) A plurality of drain electrode lines and a plurality of gate electrode lines are arranged in a matrix shape, each pixel region having a pixel region formed by being surrounded by two adjacent two drain electrodes and two adjacent ones of the gate electrode lines. In a display device in which a display region is set as a set of pixel regions, the direction in which the TFT elements are disposed with respect to the drain electrode line is inverted every time the gate electrode line is crossed in the extending direction of the drain electrode line. Is a display device to which signals of the same polarity are applied during one frame period, and signals of opposite polarities are applied to two adjacent ones.

The display device of the present invention can be driven to give signals of opposite polarities to common potentials over one frame to adjacent drain electrode lines. At this time, the TFT elements are alternately connected to the drain electrode line, thereby making the same polarity of the video signal line for one frame, and converting the signals written to the pixel electrodes of the matrix-shaped pixels into dot inversion in which mutual polarities are inverted in adjacent pixels. can do. Thereby, flicker which was a drawback of the conventional frame inversion can be eliminated. In addition, the number of charge-discharges to the drain signal line decreases significantly compared to dot inversion due to the long intervals in which the polarity is switched, which is a characteristic of frame inversion, and at a high refresh rate, for example, at a frame rate of 100 Hz or more, specifically 120 Hz Can be driven.

On the other hand, in such an arrangement, it has been found that, unless special consideration is given to the outermost line of the drain electrode line used for display, the difference in luminance and the other line occurs in the outermost display pixel, unlike the lines of the outermost line having a large capacity.

According to the present invention, in the display device capable of realizing dot inversion as a display while being a frame inversion as the potential of such a drain electrode line, occurrence of luminance unevenness of the outermost display line in the display line in a direction orthogonal to the gate line can be avoided. Unique and remarkable effects can be realized.

For this purpose, for example, the first and second dummy pixels are arranged outside the effective display area as in the above means (1). Each of the drain electrode lines is alternately connected to, for example, a TFT element of a pixel disposed on the right side facing the drain electrode line, and a TFT element of a pixel disposed on the left side facing the drain electrode line. In this case, the first and second dummy pixels are arranged, for example, on the input terminal side of the gate electrode line as in the means (2), with the first dummy pixel having the TFT elements connected to the even-numbered gate electrode lines. In this case, the first and second dummy pixels may have the same configuration as the pixels in the effective display area as in the above means 3, or may be provided with only the TFT elements as in the above means 4.

When the first and second dummy pixels are disposed, the drain electrode line to which the TFT elements of each dummy pixel are connected, for example, applies a black display signal at a timing of applying a write signal to each dummy pixel. In addition, the same signal as that applied to the pixel in the display area before the first dummy pixel is applied, and the same signal as the signal applied to the pixel in the display area after the second dummy pixel is applied. do.

At this time, for example, a dummy drain electrode line may be added as in the means (5). At this time, for example, a common signal is applied to the dummy drain electrode line. In this case, the dummy drain electrode line may be added only to the outside of the first dummy pixel or only to the outside of the second dummy pixel, or may be added to both the outside of the first dummy pixel and the outside of the second dummy pixel.

When the first and second dummy pixels are disposed, the dummy pixels are arranged at one pixel intervals. Therefore, there is a possibility that a step is generated between the dummy pixels, and a variation in rubbing intensity due to the step is generated in a lapping step when forming an alignment film, for example. Thus, for example, it is preferable to provide a third dummy pixel as in the means 6 to reduce the step difference. At this time, the third dummy pixel may be provided with only a dummy electrode layer as in the above means 7, for example, and may be provided with a dummy electrode layer and a TFT element as in the above means 8.

In addition, if the structure of the said means 1 is made into another expression, it can also say like the said means 9 and the means 11, for example. Each time the two gate electrode lines in the means 9 intersect, the region where the TFT elements are arranged corresponds to the region where the first dummy pixels and the second dummy pixels are arranged. Therefore, it is preferable to shield the area | region in which TFT element was arrange | positioned whenever it crosses two said gate electrode lines like the said means (10).

In the display device having the same configuration as the means 9 to 11, a signal is applied to the drain electrode line in the same manner as the means 12, 13, or 14, for example.

<Example>

EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated in detail with embodiment (Example) with reference to drawings.

In addition, in all the drawings for demonstrating an Example, the thing with the same function is attached | subjected with the same code | symbol, and the repeated description is abbreviate | omitted.

1 and 2 are schematic diagrams showing an example of a schematic configuration of a display panel of the display device to which the present invention is applied. FIG. 1 is a front view showing a configuration example of a liquid crystal display panel, and FIG. 2 is A-A of FIG. It is a line cross section.

The display device to which the present invention is applied is, for example, a liquid crystal display device having a liquid crystal display panel in which TFT elements are arranged in pixel units. In the liquid crystal display panel, for example, as shown in Figs. 1 and 2, a pair of substrates 1 and 2 are bonded by an annular sealant 3, and each of the substrates 1 and 2 and the sealant ( It is a display panel in which the liquid crystal material 4 is enclosed in a space surrounded by 3). At this time, the TFT element or the pixel electrode is disposed on one substrate 1, and the color filter is disposed on the other substrate 2 at a position opposite to the pixel electrode.

In addition, a liquid crystal display device having a liquid crystal display panel as shown in FIGS. 1 and 2 has a pair of polarizing plates disposed so as to sandwich the liquid crystal display panel therebetween, or a backlight disposed behind the liquid crystal display panel sandwiched between the polarizing plates. Unit or the like. In addition, since these basic structures may be the same as the conventional liquid crystal display device, detailed description is abbreviate | omitted.

Hereinafter, the circuit configuration of the substrate 1 (hereinafter referred to as TFT substrate) in which the TFT element and the pixel electrode are disposed in the display device having the liquid crystal display panel as shown in FIGS. 1 and 2 is described. Explain.

3 is a schematic diagram showing a circuit configuration of a TFT substrate of one embodiment according to the present invention.

The TFT substrate 1 of this embodiment is, for example, n + 1 gate electrode lines GL extending in the horizontal direction and arranged side by side in the vertical direction as shown in FIG. 3, and extending in the vertical direction and arranged in the horizontal direction. 3 m + 1 drain electrode line DL and a common signal line CL extending in the horizontal direction and arranged side by side in the vertical direction. In addition, although the following description is given by the example which has the common signal line CL, it is applicable also as it is to the example which does not have.

At the intersection of each gate electrode line GL and each drain electrode line DL, a TFT element connected to the gate electrode line GL and the drain electrode line is disposed. At this time, the source electrode of the TFT element is connected to the pixel electrode PX. A capacitor is formed between the pixel electrode PX and a common electrode (not shown) connected to the common signal line CL. As an example without a common electrode connected to the common signal line CL, a so-called common electrode is formed on the substrate 2 facing the TFT substrate 1, and a capacitor is formed between the common electrode and the pixel electrode PX. The structure of the longitudinal electric field system is mentioned as an example.

3 is a TFT substrate used for a color liquid crystal display panel, and has three pixels arranged in a horizontal direction, that is, an R pixel having a pixel electrode PX described as R, and a pixel electrode PX described as G. One dot on the effective display area L is composed of the B pixels having the G pixels and the pixel electrodes PX described as B. FIG.

In the effective display area L, the TFT elements are alternately connected to the drain electrode line DL. That is, the TFT element of the pixel controlled by the odd-numbered gate electrode line GL is connected to the drain electrode line DL on the left side constituting the pixel, and the TFT element of the pixel controlled by the even-numbered gate electrode line GL. Is connected to the drain electrode line DL on the right side of the pixel.

In the TFT substrate 1 of the present embodiment, dummy pixels are disposed outside the end portions of the effective display region L in the extending direction of the gate electrode lines GL. At this time, the first dummy pixel DP1 having the TFT element connected to the even-numbered gate electrode line GL is disposed outside the end portion on the side where the drain electrode line DL ₁ is disposed. The second dummy pixel DP2 having a TFT element connected to the odd-numbered gate electrode line GL is disposed outside the end portion on the side where the drain electrode line DL _{3m + 1} is arranged. In this case, the first and second dummy pixels DP1 and DP2 have the same configuration as that of each pixel in the effective display area L. FIG.

Further, a TFT element connected to each drain electrode line DL from the right side and a TFT element connected to the drain electrode line DL from the left side are alternately arranged along the extending direction of the drain electrode line DL.

When the numbers of the drain electrode lines DL are arranged from the left side, dummy pixels controlled by the even-numbered gate signal lines GL are placed in the left line closest to the effective display area L so that the order in which the TFTs are connected is the effective display area ( L) It arranges same as inside. As a result, the number of TFT elements connected to the drain signal line DL _{1 on the} leftmost side of the effective display area matches the other drain electrode line in the effective display area L, so that the load of the drain electrode line different from the load of DL ₁ is reduced. In accordance with this, it is possible to avoid occurrence of luminance fluctuation with respect to the pixel connected to another line to the display pixel connected to DL ₁ .

Similarly, a dummy pixel controlled by an odd number of gate signal lines is arranged on the rightmost line closest to the effective display area L so that the connection order of the TFT elements is the same as in the effective display area L. FIG. As a result, the number of TFTs connected to the rightmost drain signal line DL _{3m + 1 of} the effective display area L coincides with the other drain signal lines in the effective display area, and therefore the drain electrode line different from the load of DL _{3m + 1} . The loads of s match and the luminance fluctuations can be avoided for the pixels connected to other lines to the display pixels connected to the DL _{3m + 1} .

4 is a diagram illustrating an example of a time chart of signals applied to the drain electrode line DL ₁ of the display panel of this embodiment. 5 is a figure which shows an example of the time chart of the signal applied to the drain electrode line DL3m _{+ 1} of the display panel of this embodiment.

When the circuit having the configuration as shown in Fig. 3 is provided in the TFT substrate 1, the drain electrode line DL ₁ at the end side on which the first dummy pixel DP1 is disposed is formed of the drain electrode line DL ₁ . The TFT element of the R pixel in the effective display area L is connected from one side (right side), and the TFT element of the first dummy pixel DP1 is connected from the other side (left side) of the drain electrode line DL ₁ . It is. The TFT elements of the R pixels and the TFT elements of the first dummy pixel DP1 are alternately arranged along the extending direction of the drain electrode line DL ₁ . At this time, if a write signal is applied to the drain electrode line DL ₁ from the upper side of the paper, the applied signal is gated to the odd-numbered gate electrode lines GL ₁ , GL ₃ , GL ₅ , for example, as shown in FIG. 4. A signal for writing to the R pixel is applied at the timing when the signal is applied, and a signal for black display of the dummy pixel DP1 is applied at the timing at which the gate signal is applied to the even-numbered gate electrode lines GL ₂ and GL ₄ . .

On the other hand, in the drain electrode line DL _{3m + 1} at the end side where the second dummy pixel DP2 is disposed, the TFT element of the second dummy pixel DP2 and the TFT element of the B pixel in the effective display area L extend in the extending direction. Are alternately connected along. At this time, if a signal is applied to the drain electrode line DL _{3m + 1} from the upper side of the ground, the applied signal is applied to the odd-numbered gate electrode lines GL ₁ , GL ₃ , GL ₅ , for example, as shown in FIG. 5. A signal for black display of the dummy pixel DP2 is applied at a timing at which the gate signal is applied, and a signal for writing to pixel B is applied at a timing at which the gate signal is applied to the even-numbered gate electrode lines GL ₂ and GL ₄ . do.

For example, as a signal applied to the drain electrode line DL ₂ , a signal to be written to the G pixel is applied at the timing when the gate signal is applied to the odd-numbered gate electrode lines GL ₁ , GL ₃ , and GL ₅ . The signal to be written to the R pixel is applied at the timing when the gate signal is applied to the gate electrode lines GL ₂ and GL ₄ .

The dummy pixel outside the effective display area L is usually shielded in the light shielding layer. For this reason, the potential applied to the dummy pixel is not particularly limited. However, since black data can be reliably turned black by writing black data, it is preferable in that the potential can always be stabilized.

FIG. 6 is a diagram illustrating another example of a time chart of a signal applied to the drain electrode line DL ₁ of the display panel of this embodiment. 7 is a diagram showing another example of a time chart of a signal applied to the drain electrode line DL _{3m + 1} of the display panel of this embodiment.

In the present embodiment, when a signal is applied to the drain electrode line DL ₁ , not only the first dummy pixel DP1 is black displayed as shown in FIG. 4 but also various methods can be considered. That is, for example, as shown in Fig. 5, the same signal as that written to the previous R pixel may be applied. Similarly, when a signal is applied to the drain electrode line DL _{3m + 1} , the same signal as that of the signal written to the one B pixel behind one may be applied as shown in FIG.

6 and 7 may be used for explanation as an example of a general signal applied to other drain electrode lines of the effective display area. The characteristic is that the polarity is constant for one frame period. Furthermore, between any two pixels adjacent to the drain electrode line extending direction, the drain electrode lines connected by the TFT elements in the pixels are different from each other, that is, the TFT elements of one pixel are connected to the drain electrode line on the right side, and the other pixel is connected. By inverting the TFT elements on the left side to the drain electrode line, dot inversion is realized as a display. Thus, since the polarity inversion of the signal itself is performed once in a frame, the number of times of polarity inversion of the signal can be reduced by one hundredth, for example, one in 768 by XGA, compared with the conventional dot inversion which inverts line by line. have. When the signal of the drain electrode line is reversed in polarity, since the time is required until the potential of the drain electrode line stabilizes with charging and discharging of the drain electrode line, the effective writing time is reduced by this time. For this reason, in the conventional dot inversion, writing at a high frequency of 100 Hz or more was difficult. In contrast, in the present application, since the polarity inversion is eliminated in the frame, the charge / discharge time can contribute to the writing as it is, so that the driving speed is doubled for a high frequency of 100 Hz or more, for example, an input signal 60 Hz such as 120 Hz. And since the dot inversion is maintained as a display image at that time, it does not generate | occur | produce also the trouble like a flicker.

8 and 9 are schematic diagrams showing a structural example of a TFT substrate to which the circuit configuration of this embodiment is applied. FIG. 8 is an enlarged plan view of an end portion of an effective display area, and FIG. 9 is a sectional view taken along the line B-B 'of FIG. 8, the number n of gate electrode lines is an even number.

The TFT substrate 1 having the circuit configuration of this embodiment, that is, the circuit configuration as shown in Fig. 3, has the configuration as shown in Figs. 8 and 9, for example. 8, the area enclosed by the dashed-dotted line is the dummy pixel DP1 on the left side. In the square in FIG. 8, the portion marked with x indicates a contact hole.

At this time, the TFT substrate 1 is provided with, for example, a gate electrode line GL and a common signal line CL, and a common electrode CT connected to the common signal line CL on the glass substrate 101. The semiconductor layer 103, the drain electrode line DL, and the source electrode SL are provided on the upper layer of the gate electrode line GL with the first interlayer insulating film 102 interposed therebetween. At this time, each drain electrode line DL is branched so as to alternately connect to the semiconductor layer 103 disposed on the right side of the pixel and the semiconductor layer 103 disposed on the left side of the pixel as shown in FIG.

In the left region of the drain electrode line DL ₁ , the gate electrode lines GL _{n -1} and GL _n There is no TFT element therebetween, and the planar electrode of the common signal line CL of a common electric potential is formed. This results in black display, and potential stabilization of the region is realized. Further, a dummy pixel electrode to which a signal is supplied from a TFT element connected to the drain electrode line DL _{1 is} formed between the gate electrode lines GL _n and GL _{n +1} . For example, this pixel becomes black when black data is added as shown in FIG. 4 or FIG.

In addition, a bridge wiring BR for connecting the pixel electrode PX or the common electrode CT of adjacent pixels above and below is interposed between the second interlayer insulating film 104 in the upper layer such as the drain electrode line DL and the like. This is arranged. Further, in the dummy region, the electrode UC at the common potential and the bridge wiring BR for connecting the common electrode CT of the pixels adjacent up and down are provided. In this case, the pixel electrode PX is connected to the source electrode SL by a through hole. Further, for example, slits are formed in the pixel electrode PX. In addition, the electrode UC of the common potential is connected to the common signal line CL by a through hole. This serves as a pass line of the common signal line. The bridge wiring BR is connected to the common electrode CT of each pixel by a through hole.

8 and 9 show an example of the configuration of the TFT substrate 1, and the configuration of the TFT element, the pixel electrode PX, the common electrode CT, and the like can be changed as appropriate.

As described above, according to the liquid crystal display panel of the present embodiment, deterioration of image quality due to high refresh rate can be reduced.

Fig. 10 is a schematic diagram for explaining a first modification of the above embodiment, which shows a circuit configuration of a TFT substrate.

In the above embodiment, as shown in FIG. 3, the drain electrode lines DL are 3m + 1, but the present invention is not limited thereto. For example, as shown in FIG. 10, the drain electrode lines DL are located outside the second dummy pixel DP ₂ . The dummy drain electrode line DL _{3m + 2} may be provided again.

11 to 13 are schematic views for explaining a second modification of the above embodiment, in which FIG. 1 shows a circuit configuration of a TFT substrate, and FIG. 12 shows an enlarged example of a configuration of a TFT substrate to which the circuit configuration of FIG. 11 is applied. 13 is a cross-sectional view taken along the line CC 'of FIG.

In the above embodiment, as shown in Fig. 3, as the first and second dummy pixels DP1 and DP2, dummy pixels having the same configuration as the pixels in the effective display area L are arranged, but not limited thereto. For example, as shown in Fig. 11, only the TFT element may be disposed. This is because the main load capacity of the drain electrode line is that of the TFT element. The circuit configuration shown in Fig. 11 is the same as the circuit configuration shown in Fig. 3 except that the first and second dummy pixels DP1 and DP2 are made of only TFT elements.

The TFT substrate 1 to which the circuit configuration as shown in Fig. 11 is applied has a configuration as shown in Figs. 12 and 13, for example. 12, the area enclosed by the dashed-dotted line is a TFT element of the first dummy pixel DP1. In addition, the structure of the TFT substrate 1 shown in FIG. 12 and FIG. 13 is only the TFT element of 1st dummy pixel DP1 enclosed by the 2-dot chain line in FIG. 8, and the other structure is shown in FIG. 8 and FIG. Same as the configuration shown. 12 and 13 show an example of the configuration of the TFT substrate 1, and of course, the configuration of the TFT element, the pixel electrode PX, the common electrode CT and the like can be changed as appropriate.

14 to 18 are schematic diagrams for explaining a third modification of the above embodiment, in which FIGS. 14 to 16 each show a circuit configuration of a TFT substrate, and FIG. 17 shows a TFT substrate to which the circuit configuration of FIG. 15 is applied. An enlarged plan view showing an example, and FIG. 18 is a cross-sectional view taken along the line D-D 'of FIG.

In the above description, for example, as illustrated in FIG. 3, the dummy pixels DP1 and DP2 are arranged in even or odd numbers. However, in the display device of the present invention, for example, as shown in FIG. 14, the third dummy pixel DP3 may be disposed between the second dummy pixels DP2. In this case, unlike the second dummy pixel DP2, the third dummy pixel DP3 includes only a dummy electrode connected to the common signal line CL, for example. In this case, for example, the third dummy pixel DP3 may be disposed between the first dummy pixels DP1 as shown in FIG. 15, and between the first dummy pixels DP1 as shown in FIG. 16. You may arrange | position both in between 2nd dummy pixel DP2.

17 and 18 show an example of such a configuration, for example, a circuit configuration as shown in FIG. For example, as shown in FIGS. 17 and 18, the third dummy pixel DP3 is integrally formed with the electrode UC of the common potential, and is dummy on the same layer as the pixel electrode PX of the pixel in the effective display area. Pixel electrodes can be provided. As a result, the pixel electrode and the common electrode are alternately arranged in the uppermost layer of the column in which the first dummy pixel DP1 and the third pixel DP3 on the left side of the effective display area are alternately side by side.

With such a configuration, for example, the difference in the stepped structure between the first dummy pixels DP1 arranged every other and the third dummy pixels DP3 therebetween can be reduced. Therefore, for example, in the rubbing process at the time of providing the alignment film on the TFT substrate 1, the occurrence of fluctuations in the rubbing strength due to the step can be avoided.

19 to 25 are schematic diagrams for explaining a fourth modification of the above embodiment, wherein FIGS. 19 to 21 show circuit configurations of a TFT substrate, and FIG. 22 shows a TFT substrate to which the circuit configuration of FIG. 20 is applied. 23 is an enlarged plan view showing a configuration example, FIG. 23 is an sectional view taken along the line E-E 'of FIG. 22, FIG. 24 is an enlarged plan view showing another configuration example of the TFT substrate to which the circuit configuration of FIG. 20 is applied, and FIG. 25 is an F-F of FIG. It is a line cross section.

14 to 18 are circuits in which the third dummy pixel DP3 is disposed between the first dummy pixel DP1, the second dummy pixel DP2, or both of them, based on the circuit configuration shown in FIG. 3. The configuration is shown. However, when the third dummy pixel DP3 is disposed, for example, as shown in FIG. 19, the third dummy pixel DP3 is disposed only between the second dummy pixel DP2, and again, the dummy drain electrode line outside the second dummy pixel DP3. You may arrange | position (DL _{3m + 2} ). For example, as shown in FIG. 20, the third dummy pixel DP3 may be disposed only between the first dummy pixels DP1, and the dummy drain electrode line DL ₀ may be disposed outside the third dummy pixel DP3. In combination of these, for example, as shown in FIG. 21, disposed between both of the first dummy pixel DP1 and the second dummy pixel DP2, and the drain electrode lines DL ₀ and DL _{3m +} are respectively located on the outside thereof. _You may arrange ₂ ).

22 and 23 show an example of such a configuration, for example, a circuit configuration as shown in FIG. For example, as shown in FIGS. 22 and 23, the third dummy pixel DP3 is integrated with the electrode UC of the common potential, and the dummy pixel is on the same layer as the pixel electrode PX of the pixel in the effective area. The electrode PXd is provided. With such a configuration, for example, the difference between the stepped structures between the first dummy pixels arranged every other and the third dummy pixels therebetween can be reduced. Therefore, for example, in the rubbing process at the time of providing the alignment film on the TFT substrate 1, the occurrence of the variation in the lapping strength due to the step can be avoided.

In the circuit configuration shown in Fig. 20, the dummy pixel electrode PXd provided in the third dummy pixel DP3 is integrated with the bridge wiring BR as shown in Fig. 24, for example. By connecting to the common electrode CT of the first dummy pixel DP1, the common potential can be set.

26 to 30 are schematic diagrams for explaining a fifth modification of the above embodiment, in which FIGS. 26 to 28 show circuit configurations of a TFT substrate, and FIG. 29 shows a TFT substrate to which the circuit configuration of FIG. 27 is applied. An enlarged plan view showing a configuration example, and FIG. 30 is a cross-sectional view taken along the line G-G 'of FIG.

In the third and fourth modifications, the pixel electrode PXd at the common potential is provided as the third dummy pixel DP3. However, the third dummy pixel DP3 is not limited to this. For example, as shown in FIG. 26, only the TFT element and the pixel electrode may be disposed between the second dummy pixels DP2. At this time, the dummy drain electrode line DL _{3m + 2} is disposed outside the second dummy pixel DP2, and the TFT elements of the third dummy pixel DP3 are connected. For example, as shown in FIG. 27, the third dummy pixel DP3 may be disposed only between the first dummy pixels DP1, and the dummy drain electrode line DL ₀ may be further disposed outside thereof. In combination of these, for example, as shown in FIG. 28, the first dummy pixel DP1 and the second dummy pixel DP2 are disposed on both sides thereof, and the drain electrode lines DL ₀ and DL _{3m +} are respectively located on the outside thereof. _You may arrange ₂ ).

29 and 30 show an example of such a configuration, for example, a circuit configuration as shown in FIG. 27. For example, as illustrated in FIGS. 29 and 30, the dummy pixel electrode PXd is provided on the same layer as the pixel electrode PX of the pixel in the effective area as shown in FIGS. 29 and 30. At this time, the common electrode CT overlapping the dummy pixel electrode PXd is not provided. With such a configuration, for example, the difference in the stepped structure between the first dummy pixels DP1 arranged every other and the third dummy pixels DP3 therebetween can be reduced. Therefore, in the lapping process at the time of providing an oriented film on the TFT substrate 1, for example, the occurrence of fluctuation in lapping strength due to the step can be avoided.

As mentioned above, although this invention was demonstrated concretely based on the said Example, this invention is not limited to the said Example, Of course, various changes are possible in the range which does not deviate from the summary.

For example, in the above embodiment and its modification, the TFT substrate 1 of the liquid crystal display panel as shown in Figs. 1 and 2 is taken as an example. However, the present invention is not limited to the above liquid crystal display panel, and of course, the TFT element can be applied to various display panels in which pixel units are arranged.

The display device of the present invention can be driven to give signals of opposite polarities to common potentials over one frame to adjacent drain electrode lines. At this time, the TFT elements are alternately connected to the drain electrode line, thereby making the same polarity of the video signal line for one frame, and converting the signals written to the pixel electrodes of the matrix-shaped pixels into dot inversion in which mutual polarities are inverted in adjacent pixels. can do. Thereby, flicker which was a drawback of the conventional frame inversion can be eliminated. In addition, the number of charge-discharges to the drain signal line decreases significantly compared to dot inversion due to the long intervals in which the polarity is switched, which is a characteristic of frame inversion, and at a high refresh rate, for example, at a frame rate of 100 Hz or more, specifically 120 Hz Can be driven.

Claims (17)

As a display value having TFTs and pixel electrodes having display panels arranged for each pixel region defined by the drain electrode line and the gate electrode line, The display panel includes TFTs connected to even-numbered gate electrode lines from one end portion in the extension direction of the drain electrode line in a drain electrode line positioned outside the one end portion in the extending direction of the gate electrode line among the end portions of the effective display area. A first dummy pixel having an element is disposed, A TFT element connected to an odd-numbered gate electrode line from one end in the extending direction of the drain electrode line in a drain electrode line located outside the other end in the extending direction of the gate electrode line among the ends of the effective display area. A second dummy pixel having In each drain electrode line, TFT elements of each pixel connected to the drain electrode line are alternately arranged along the extension direction, Each drain electrode line at an end in the extending direction of the gate electrode line is connected to a plurality of TFT elements arranged in the effective display area and a plurality of first or second dummy pixels arranged outside the effective display area, The plurality of TFT elements and the plurality of first or second dummy pixels connected to the respective drain electrode lines are alternately arranged along the extending direction of the respective drain electrode lines, A third dummy pixel is disposed between the plurality of first dummy pixels or between the plurality of second dummy pixels. The method of claim 1, And an end portion at which the first dummy pixel is disposed is an input end side of the gate electrode line. The method according to claim 1 or 2, And the first and second dummy pixels have the same configuration as the pixels in the effective display area. The method according to claim 1 or 2, And the first and second dummy pixels have only TFT elements. The method of claim 1, And a dummy drain electrode line outside the first or second dummy pixel. delete The method of claim 1, And the third dummy pixel has a dummy electrode layer on the same conductive layer as the pixel electrode of the pixel in the effective display area. The method of claim 7, wherein And the third dummy pixel has a dummy drain electrode line and a TFT element connected to the dummy electrode layer. delete The method of claim 1, The formation area of the dummy pixel is shielded from light. delete delete delete delete The method of claim 1, An opposite electrode is formed in the pixel area where the dummy pixel is not formed; The counter electrode has a planar electrode shape having sides along the drain electrode line and the gate electrode line surrounding the pixel region, The pixel electrode has a slit overlapping the counter electrode and formed in two directions. delete The method of claim 15, The third dummy pixel does not include a TFT element, and the pixel electrode in the third dummy pixel is electrically connected to the counter electrode.

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