WO2018061094A1

WO2018061094A1 - Display device

Info

Publication number: WO2018061094A1
Application number: PCT/JP2016/078503
Authority: WO
Inventors: 松田　成裕; 琢也大石
Original assignee: 堺ディスプレイプロダクト株式会社
Priority date: 2016-09-27
Filing date: 2016-09-27
Publication date: 2018-04-05

Abstract

The present invention relates to a display device characterized by being provided with: a display panel having a display area and a non-display area; a plurality of sub-pixel switching elements corresponding to a plurality of sub-pixels of the display panel; a control switching element connected to one of the sub-pixel switching elements, and controlling gray level differences between the sub-pixels; a gate terminal unit located in the non-display area; a plurality of gate lines connected to the gate terminal unit and the plurality of sub-pixel switching elements, and extending in a first direction; an auxiliary gate line which extends in the first direction from between the gate lines, and is connected to a control terminal of the control switching element, and which, in the non-display area, is not connected to the gate terminal unit; a first signal line and a second signal line that extend in a second direction; a first switching element for controlling the connection of the auxiliary gate line and a first gate line on the basis of a signal from the first signal line; and a second switching element for controlling the connection of the auxiliary gate line and a second gate line on the basis of a signal from the second signal line.

Description

Display device

This technology relates to a display device that displays video.

Thin display devices, such as liquid crystal display devices, are generally widespread because they have a larger display area than the installation area. The liquid crystal display device includes a liquid crystal panel and a backlight disposed on the back side of the liquid crystal panel. The liquid crystal panel includes two substrates on which pixel electrodes and common electrodes are formed, and a liquid crystal layer sealed between the two substrates. A voltage is applied to the pixel electrode and the common electrode to change the orientation of liquid crystal molecules in the liquid crystal layer, thereby controlling the polarization of incident light.

Generally, liquid crystal panels have narrow viewing angle characteristics. In order to improve this viewing angle characteristic, it has been conventionally proposed to configure a pixel of a liquid crystal panel with a plurality of sub-pixels (see, for example, Patent Document 1).

US Patent Publication No. 2009-0027578

However, in order to realize the viewing angle improvement based on Patent Document 1, it is necessary to additionally route a control wiring for controlling the potential of the subpixel. In Patent Document 1, the display area of the liquid crystal panel is used. The detailed structure in the non-display area located around is not specified.

The present embodiment has been made in view of such circumstances, and an object thereof is to provide a display device capable of smoothly driving the display panel by the configuration of the non-display area of the display panel.

A display device according to the present embodiment includes a display panel having a display area and a non-display area positioned around the display area, and a plurality of subpixel switching elements corresponding to a plurality of subpixels constituting pixels of the display panel A control switching element that is connected to one of the sub-pixel switching elements and controls a potential difference between the sub-pixels, a gate terminal portion located in the non-display area, the gate terminal portion, and a plurality of sub-pixels A plurality of gate lines connected to the switching element and extending in the first direction, and an auxiliary line extending in the first direction between the plurality of gate lines and connected to a control terminal of the control switching element In the display device including a gate line, in the non-display area, the auxiliary gate line is not connected to the gate terminal portion, and in the non-display area, in the first direction. A first signal line and a second signal line extending along a second direction, and the non-display area, and the auxiliary gate line and the first signal line are arranged based on a signal from the first signal line. A first switching element that controls connection of the gate line, and a connection between the auxiliary gate line and the second gate line, which is arranged in the non-display region and based on a signal from the second signal line And a second switching element for controlling.

In the display device according to the present embodiment, the auxiliary gate line is not connected to the gate terminal portion in the non-display area, so that an increase in the number of wirings connected to the gate terminal portion can be suppressed. Further, based on the signals from the first signal line and the second signal line, the driving of the first switching element and the second switching element is controlled, and the gate line is scanned in the forward direction and the reverse direction, thereby smoothing the display panel. It can be driven.

3 is a front view schematically showing a display panel of the display device according to Embodiment 1. FIG. It is an equivalent circuit diagram of the display panel in the vicinity of the boundary between the display area and the non-display area. It is a table | surface explaining the drive system of the display apparatus by a control part. FIG. 6 is a timing diagram schematically showing respective voltages of each gate line, first signal line to third signal line, auxiliary gate line, and drain electrode of each thin film transistor in the first driving method. FIG. 10 is a timing diagram schematically showing voltages of a gate line, a first signal line to a third signal line, an auxiliary gate line, and a drain electrode of each thin film transistor in the second driving method. FIG. 10 is a timing diagram schematically showing voltages of a gate line, first signal line to third signal line, auxiliary gate line, and drain electrode of each thin film transistor in a third driving method when the gate line is scanned in the forward direction. FIG. 10 is a timing diagram schematically showing the voltages of the gate line, the first signal line to the third signal line, the auxiliary gate line, and the drain electrode of each thin film transistor in the third driving method when the gate line is scanned in the reverse direction. 10 is an equivalent circuit diagram of a display panel in the vicinity of a boundary between a display area and a non-display area according to Embodiment 2. FIG. It is an example of the equivalent circuit schematic of the display panel which concerns on a 1st reference display apparatus. It is an example of the equivalent circuit schematic of the display panel which concerns on a 2nd reference display apparatus.

(Embodiment 1)
A display device according to Embodiment 1 will be described with reference to the drawings. FIG. 1 is a front view schematically showing a display panel. In FIG. 1, one gate line Gn and one data signal line 4 are representatively shown. The display device includes a horizontally long display panel 1 in which a liquid crystal layer is sealed between two substrates. The central portion of the display panel 1 is a display area 1a for displaying a horizontally long rectangular image. In the display panel 1, the periphery of the display area 1 a is a horizontally long rectangular frame, and is a non-display area 1 b where no video is displayed. The horizontal direction of the display panel 1 corresponds to the first direction, and the vertical direction corresponds to the second direction.

A plurality of gate terminal portions 33, 3,..., 3 are juxtaposed in the vertical direction on each short side (right side or left side in FIG. 1) of the display panel 1. The gate terminal portion 3 is provided in the non-display area 1b. A film such as COF (Chip On Film) is provided outside the non-display area 1b, and the film and the gate terminal 3 are connected to input a driving signal from the outside to the panel. Gate lines extend in the lateral direction from the

gate terminal portions

3 and 3 respectively. In the display area 1a, a plurality of data signal lines 4 extending in the vertical direction are arranged in parallel in the horizontal direction. The data signal lines 4 and the gate lines are orthogonal to each other and arranged on the display panel 1 in a matrix.

A thin film transistor and a pixel electrode connected to the thin film transistor are provided near the intersection of the data signal line 4 and the gate line. The thin film transistor is ON / OFF controlled by the gate line, a signal potential is applied from the data signal line 4 to each pixel electrode, the alignment state of the liquid crystal changes, and information is displayed.

FIG. 2 is an equivalent circuit diagram of the display panel 1 near the boundary between the display area 1a and the non-display area 1b. In FIG. 2, A indicates the boundary between the display area 1a and the non-display area 1b, the right side of the boundary A is the display area 1a, and the left side of the boundary A is the non-display area 1b.

A plurality of gate lines G _n (n is an integer) are juxtaposed in the vertical direction and are connected to the gate terminal portion 3, respectively. A plurality of auxiliary gate lines SG _n (n is an integer) corresponding to each gate line G _n and extending in the longitudinal direction are provided on the display panel 1. The auxiliary gate line SG _n is located between the adjacent gate line G _n (third gate line) and the gate line G _{n + 1} (first gate line). The auxiliary gate line SG _n is provided over the display area 1 a and the non-display area 1 b, but is not directly connected to the gate terminal portion 3. The gate line G _n-1 constitutes a second gate line.

A plurality of first voltage supply lines 21 corresponding to each gate line G _n and extending in the longitudinal direction are provided on the display panel 1. A plurality of second voltage supply lines 22 corresponding to each gate line G _n and extending in the longitudinal direction are provided on the display panel 1. An arbitrary voltage can be applied to the first voltage supply line 21 and the second voltage supply line 22.

A pixel electrode 40 (pixel) is formed in the vicinity of the intersection of each data signal line 4 and each gate line _Gn . The pixel electrode 40 includes a first subpixel 41 and a second subpixel 42.

The first subpixel 41 includes a thin film transistor T1 (subpixel switching element), a first capacitor C1, and a second capacitor C2. The thin film transistor T1 has a gate electrode connected to the gate line _Gn , a source electrode connected to the data signal line 4, and a drain electrode connected to one end of each of the first capacitor C1 and the second capacitor C2. The other end of the first capacitor C 1 is connected to the common electrode, and the other end of the second capacitor C 2 is connected to the first voltage supply line 21.

The second subpixel 42 includes a thin film transistor T2 (subpixel switching element), a third capacitor C3, and a fourth capacitor C4. The thin film transistor T2 has a gate electrode connected to the gate line _Gn , a source electrode connected to the data signal line 4, and a drain electrode connected to one end of each of the third capacitor C3 and the fourth capacitor C4. The other end of the third capacitor C3 is connected to the common electrode, and the other end of the fourth capacitor C4 is connected to the second voltage supply line 22.

A thin film transistor T3 (control switching element) and a fifth capacitor C5 are connected to the second subpixel 42. The gate electrode of the thin film transistor T3 is connected to the auxiliary gate line SG _n, the source electrode is connected to the drain electrode of the second TFT T2, the drain electrode is connected to one end of the fifth capacitor C5. The other end of the fifth capacitor C5 is connected to the second voltage supply line 22.

In the non-display area 1b, the first signal line 11, the second signal line 12, and the third signal line 13 extending in the vertical direction are juxtaposed in the horizontal direction. A signal for controlling forward scanning is input to the first signal line 11. A signal for controlling scanning in the reverse direction is input to the second signal line 12. A signal for setting the presence / absence of a gradation difference between the first sub-pixel 41 and the second sub-pixel 42 is input to the third signal line 13.

Note that the forward direction indicates the ascending order of n, that is, the direction of scanning the gate line G _n in the order of n−1, n, n + 1, and the reverse direction indicates the descending order of n, that is, n + 1, n, n−. The direction of scanning the gate line G _n in the order of 1 is shown.

A first switching element S <b> 1 is provided between the first signal line 11 and the second signal line 12. The first switching element S1 includes a thin film transistor. The gate electrode of the first switching element S1 is connected to the first signal line 11, a source electrode connected to the gate line G _{n + 1,} the drain electrode is connected to the auxiliary gate line SG _n.

A second switching element S <b> 2 is provided between the second signal line 12 and the third signal line 13. The second switching element S2 includes a thin film transistor. The gate electrode of the second switching element S2 is connected to the second signal line 12, the source electrode is connected to the gate line G _n-1 (second gate line), and the drain electrode is connected to the auxiliary gate line SG _n . It is connected.

The third switching element S3 is provided in the non-display area 1b. The third switching element S3 includes a thin film transistor. The gate electrode of the third switching element S3, is connected to the third signal line 13, a source electrode connected to the gate line G _n, a drain electrode is connected to the auxiliary gate line SG _n.

As shown in FIG. 1, the display device includes a control unit 70 (a first control unit, a second control unit, and a third control unit) having a CPU, a ROM, a RAM, a nonvolatile memory, an input / output interface, and the like. A data signal is input from the control unit 70 to the data signal line 4 via the source substrate 2, and a signal is input to the gate line via the gate terminal unit 3.

FIG. 3 is a table for explaining a driving method of the display device by the control unit 70. In FIG. 3, the first driving method indicates a driving method in which the gate line G _n is scanned in the forward direction and a gradation difference is provided between the first sub-pixel 41 and the second sub-pixel 42. A driving method in which the gate line G _n is scanned in the reverse direction and a gradation difference is provided between the first sub-pixel 41 and the second sub-pixel 42 is shown. The third driving method is a gate line G _{n in the} forward direction or the reverse direction. And a driving method in which no gradation difference is provided between the first sub-pixel 41 and the second sub-pixel 42.

FIG. 4 shows the gate lines G _n−1 , G _n , G _{n + 1} , the first signal line 11 to the third signal line 13, the auxiliary gate line SG _n , and the thin film transistors T1, T2 in the first driving method. It is a timing diagram which shows each voltage of a drain electrode schematically. In FIG. 4, T1 and T2 indicate the voltage of the drain electrode of the thin film transistor T1 and the voltage of the drain electrode of the thin film transistor T2, respectively. In FIG. 4, the pull-in (or kickback) phenomenon due to the parasitic capacitance between the gate and drain of each transistor is omitted with respect to the voltages of the drain electrodes of T1 and T2.

In the first driving method, an “H” signal (High signal) is input to the first signal line 11, and an “L” signal (Low signal) is input to the second signal line 12 and the third signal line 13. The

In this case, as shown in FIG. 4, an “H” signal is inputted in the forward direction to the gate line G _n−1 , the gate line G _n and the gate line G _{n + 1} . 4, an input start time of the "H" signal to the gate lines G _n and P _1, an input start of the "H" signal to the input end and the gate line G _{n + 1} "H" signal to the gate line G _n The time point is P _2, and the input end point of the “H” signal to the gate line G _{n + 1} is P ₃ .

When the “H” signal is input to the first signal line 11, the first switching element S1 is turned on, and the gate line G _{n + 1} and the auxiliary gate line SG _n are connected. Therefore, the “H” signal is also input to the auxiliary gate line SG _n at the timing (time point P ₂ ) when the “H” signal is input to the gate line G _{n + 1} .

As shown in FIG. 4, when the “H” signal is input to the gate line G _n (time point P ₁ ), the thin film transistor T1 is turned on, the data signal is input from the data signal line 4, and the thin film transistor T1 is turned on. During the period (between P _{1 and} P ₂ ), the voltage on the drain electrode side of the thin film transistor T1 changes from Low to High. In addition, while the thin film transistor T2 is turned on and a data signal is input from the data signal line 4 and the thin film transistor T2 is turned on (between P _{1 and} P ₂ ), the voltage on the drain electrode side of the thin film transistor T2 changes from low to high. Transition to.

When the “H” signal is input to the gate line G _{n + 1} (time point P ₂ ), the thin film transistor T3 is turned on, the charge is shared between the capacitors C3 and C4, and the capacitor C5, and the gate line G _{n + 1.} The voltage on the drain electrode side of the thin film transistor T2 slightly drops while the “H” signal is being input to (between P ₂ P ₃ ). Usually, since the polarity of the voltage applied to each pixel is inverted every frame, the charge remaining in the capacitor C5 before the thin film transistor T3 is turned on is charged to the capacitors C3 and C4 when the thin film transistor T2 is turned on. When the thin film transistor T3 is turned on, the charges of the capacitors C3 and C4 and the charge of the capacitor C5 having the opposite polarity cancel each other, and the voltage on the drain electrode side of the thin film transistor T2 drops. To do. As a result, a potential difference is generated between the first subpixel 41 and the second subpixel 42, resulting in a gradation difference.

FIG. 5 shows the gate lines G _n−1 , G _n , G _{n + 1} , the first signal line 11 to the third signal line 13, the auxiliary gate line SG _n , and the thin film transistors T1, T2 in the second driving method. It is a timing diagram which shows each voltage of a drain electrode schematically. In FIG. 5, T1 and T2 indicate the voltage of the drain electrode of the thin film transistor T1 and the voltage of the drain electrode of the thin film transistor T2, respectively.

In the second driving method, the “H” signal is input to the second signal line 12, and the “L” signal is input to the first signal line 11 and the third signal line 13.

In this case, as shown in FIG. 5, the “H” signal is inputted in the reverse direction to the gate line G _n−1 , the gate line G _n , and the gate line G _{n + 1} . 5, an input start time of the "H" signal to the gate lines G _n and P _1, an input start of the "H" signal to the input end and the gate lines G _n-1 "H" signal to the gate line G _n The time point is P _2, and the input end time point of the “H” signal to the gate line G _n−1 is P ₃ .

When the “H” signal is input to the second signal line 12, the second switching element S2 is turned on, and the gate line G _n−1 and the auxiliary gate line SG _n are connected. Therefore, the “H” signal is also input to the auxiliary gate line SG _n at the timing when the “H” signal is input to the gate line G _n−1 (time point P ₂ ).

As shown in FIG. 5, when the “H” signal is input to the gate line G _n (time point P ₁ ), the thin film transistor T1 is turned on, the data signal is input from the data signal line 4, and the thin film transistor T1 is turned on. During the period (between P _{1 and} P ₂ ), the voltage on the drain electrode side of the thin film transistor T1 changes from Low to High. In addition, while the thin film transistor T2 is turned on and a data signal is input from the data signal line 4 and the thin film transistor T2 is turned on (between P _{1 and} P ₂ ), the voltage on the drain electrode side of the thin film transistor T2 changes from low to high. Transition to.

When the “H” signal is input to the gate line G _n−1 (time point P ₂ ), the thin film transistor T3 is turned on, and the charge is shared between the capacitors C3 and C4 and the capacitor C5, and the gate line G _n−1. The voltage on the drain electrode side of the thin film transistor T2 slightly drops while the “H” signal is being input to (between P ₂ P ₃ ). Usually, since the polarity of the voltage applied to each pixel is inverted every frame, the charge remaining in the capacitor C5 before the thin film transistor T3 is turned on is charged to the capacitors C3 and C4 when the thin film transistor T2 is turned on. When the thin film transistor T3 is turned on, the charges of the capacitors C3 and C4 and the charge of the capacitor C5 having the opposite polarity cancel each other, and the voltage on the drain electrode side of the thin film transistor T2 drops. To do. As a result, a potential difference is generated between the first subpixel 41 and the second subpixel 42, resulting in a gradation difference.

FIG. 6A shows the gate lines G _n−1 , G _n , G _{n + 1} , the first signal line 11 to the third signal line 13, and the auxiliary gate line in the third driving method when the gate line is scanned in the forward direction. FIG. 6 is a timing diagram schematically showing SG _n and voltages of drain electrodes of the thin film transistors T1 and T2. In FIG. 6A, T1 and T2 indicate the voltage of the drain electrode of the thin film transistor T1 and the voltage of the drain electrode of the thin film transistor T2, respectively.

FIG. 6B shows the gate lines G _n−1 , G _n , G _{n + 1} , the first signal line 11 to the third signal line 13, and the auxiliary gate line in the third driving method when the gate line is scanned in the reverse direction. FIG. 6 is a timing diagram schematically showing SG _n and voltages of drain electrodes of the thin film transistors T1 and T2. In FIG. 6B, T1 and T2 indicate the voltage of the drain electrode of the thin film transistor T1 and the voltage of the drain electrode of the thin film transistor T2, respectively.

As shown in FIG. 6A and FIG. 6B, when the display panel 1 is driven by the third driving method, regardless of whether the scanning direction of the gate line is the forward direction or the reverse direction, The “H” signal is input, and the “L” signal is input to the first signal line 11 and the second signal line 12.

A case where the scanning direction of the gate line is the forward direction will be described. As shown in FIG. 6A, when an “H” signal is input in the forward direction to the gate line G _n−1 , the gate line G _n, and the gate line G _{n + 1} , the “H” signal to the gate line G _n an input start time of the P _1, has an input start time of the "H" signal to the input end and the gate line G _{n + 1} "H" signal to the gate lines G _n and P _2.

When the “H” signal is input to the third signal line 13, the third switching element S3 is turned on, and the gate line G _n and the auxiliary gate line SG _n are connected. Therefore, at the timing when the “H” signal is input to the gate line G _n (time point P ₁ ), the “H” signal is also input to the auxiliary gate line SG _n .

As shown in FIG. 6A, when the “H” signal is input to the gate line G _n (time point P ₁ ), the thin film transistor T1 is turned on, the data signal is input from the data signal line 4, and the thin film transistor T1 is turned on. During the period (between P _{1 and} P ₂ ), the voltage on the drain electrode side of the thin film transistor T1 changes from Low to High. In addition, while the thin film transistor T2 is turned on and a data signal is input from the data signal line 4 and the thin film transistor T2 is turned on (between P _{1 and} P ₂ ), the voltage on the drain electrode side of the thin film transistor T2 changes from low to high. Transition to.

When the “H” signal is input to the gate line G _n (time point P ₁ ), the “H” signal is also input to the auxiliary gate line SG _n , so that the thin film transistor T3 is turned on, and the capacitor C5 includes a capacitor Charging is performed so that charges having the same polarity as C3 and C4 have substantially the same potential. As a result, the potentials of the capacitors C1 and C3 become substantially the same, and there is almost no gradation difference between the first subpixel 41 and the second subpixel 42.

A case where the scanning direction of the gate line is the reverse direction will be described. As shown in FIG. 6B, when an “H” signal is input in the reverse direction to the gate line G _n−1 , the gate line G _n, and the gate line G _{n + 1} , the “H” signal to the gate line G _n Is set to P _1, and the input end time of the “H” signal to the gate line G _n and the input start time of the “H” signal to the gate line G _n−1 are P ₂ .

As shown in FIG. 6B, when the “H” signal is input to the gate line G _n (time point P ₁ ), the thin film transistor T1 is turned on, the data signal is input from the data signal line 4, and the thin film transistor T1 is turned on. During the period (between P _{1 and} P ₂ ), the voltage on the drain electrode side of the thin film transistor T1 changes from Low to High. In addition, while the thin film transistor T2 is turned on and a data signal is input from the data signal line 4 and the thin film transistor T2 is turned on (between P _{1 and} P ₂ ), the voltage on the drain electrode side of the thin film transistor T2 changes from low to high. Transition to.

In the display device according to the first embodiment, since the auxiliary gate lines are not individually connected to the gate terminal portion 3 in the non-display region 1b, an increase in the number of wirings connected to the gate terminal portion 3 is suppressed. can do. Further, the driving of the first switching element S1 and the second switching element S2 can be controlled based on the signals from the first signal line 11 and the second signal line 12, and the gate lines can be scanned in the forward direction and the reverse direction. .

For example, when the first switching element S1 is turned on, the second switching element S2 is turned off to realize a gradation difference between the first subpixel 41 and the second subpixel 42 in the scanning of the gate line in the forward direction. be able to. Further, when the second switching element S2 is on, the first switching element S1 is turned off, and, for example, in the scanning of the gate line in the reverse direction, a gradation difference between the first subpixel 41 and the second subpixel 42 is realized. can do.

Further, based on the signal from the third signal line 13, the driving of the third switching element S3 can be controlled to change the gradation difference between the sub-pixels. In addition, when the third switching element S3 is turned on, the first switching element S1 and the second switching element S2 can be turned off so that the gradation difference between the sub-pixels hardly occurs.

(Embodiment 2)
A display device according to Embodiment 2 will be described below with reference to the drawings. Among the configurations of the display device according to the second embodiment, the same configurations as those of the first embodiment are denoted by the same reference numerals unless detailed description is necessary, and detailed descriptions thereof are omitted. FIG. 7 is an equivalent circuit diagram of the display panel 1 in the vicinity of the boundary between the display area 1a and the non-display area 1b. In FIG. 7, A indicates the boundary between the display area 1a and the non-display area 1b. The right side of the boundary A is the display area 1a, and the left side of the boundary A is the non-display area 1b.

In FIG. 7, the gate line G _{n + 2} constitutes a first gate line, the gate line G _n-2 constitutes a second gate line, and the gate line G _n constitutes a third gate line.

The gate electrode of the first switching element S1 is connected to the first signal line 11, the source electrode is connected to the gate line G _{n + 2} (first gate line), and the drain electrode is connected to the auxiliary gate line SG _n . It is connected. The gate electrode of the second switching element S2 is connected to the second signal line 12, the source electrode is connected to the gate line G _n-2 (second gate line), and the drain electrode is connected to the auxiliary gate line SG _n . It is connected. Even in this case, the above-described first to third driving methods (see FIG. 3) can be executed.

Specifically, when the first driving method is executed, an “H” signal is input to the first signal line 11, the first switching element S1 is turned on, and the gate line G _{n + 2} and the auxiliary gate line SG _n are turned on. And are connected. Therefore, the “H” signal is also input to the auxiliary gate line SG _n at the timing when the “H” signal is input to the gate line G _{n + 2} .

When the “H” signal is input to the gate line G _n , the thin film transistor T1 is turned on. While the data signal is input from the data signal line 4 and the thin film transistor T1 is turned on, the drain electrode side of the thin film transistor T1 The voltage changes from Low to High. Further, while the thin film transistor T2 is turned on, a data signal is input from the data signal line 4, and the thin film transistor T2 is turned on, the voltage on the drain electrode side of the thin film transistor T2 changes from low to high.

When the “H” signal is input to the gate line G _{n + 2} , the thin film transistor T3 is turned on, the charge is shared between the capacitors C3 and C4 and the capacitor C5, and the “H” signal is applied to the gate line G _{n + 2.} Is inputted, the voltage on the drain electrode side of the thin film transistor T2 slightly drops. Usually, since the polarity of the voltage applied to each pixel is inverted every frame, the charge remaining in the capacitor C5 before the thin film transistor T3 is turned on is charged to the capacitors C3 and C4 when the thin film transistor T2 is turned on. When the thin film transistor T3 is turned on, the charges of the capacitors C3 and C4 and the charge of the capacitor C5 having the opposite polarity cancel each other, and the voltage on the drain electrode side of the thin film transistor T2 drops. To do. As a result, a potential difference is generated between the first subpixel 41 and the second subpixel 42, resulting in a gradation difference.

When the second driving method is executed, an “H” signal is input to the second signal line 12, the second switching element S2 is turned on, and the gate line G _n−2 and the auxiliary gate line SG _n are connected. . Therefore, the “H” signal is also input to the auxiliary gate line SG _n at the timing when the “H” signal is input to the gate line G _n-2 .

When the “H” signal is input to the gate line G _n−2 , the thin film transistor T3 is turned on, the charge is shared between the capacitors C3 and C4 and the capacitor C5, and the “H” signal is input to the gate line G _n−2. Is inputted, the voltage on the drain electrode side of the thin film transistor T2 slightly drops. Usually, since the polarity of the voltage applied to each pixel is inverted every frame, the charge remaining in the capacitor C5 before the thin film transistor T3 is turned on is charged to the capacitors C3 and C4 when the thin film transistor T2 is turned on. When the thin film transistor T3 is turned on, the charges of the capacitors C3 and C4 and the charge of the capacitor C5 having the opposite polarity cancel each other, and the voltage on the drain electrode side of the thin film transistor T2 drops. To do. As a result, a potential difference is generated between the first subpixel 41 and the second subpixel 42, resulting in a gradation difference.

When the third driving method is executed, an “H” signal is input to the gate line G _n and the thin film transistor T1 is turned on. While the data signal is input from the data signal line 4 and the thin film transistor T1 is turned on, the voltage on the drain electrode side of the thin film transistor T1 changes from low to high. Further, while the thin film transistor T2 is turned on, a data signal is input from the data signal line 4, and the thin film transistor T2 is turned on, the voltage on the drain electrode side of the thin film transistor T2 changes from low to high.

When the “H” signal is input to the gate line G _n , the “H” signal is also input to the auxiliary gate line SG _n , so that the thin film transistor T3 is turned on, and the capacitor C5 has the same characteristics as the capacitors C3 and C4. Charging is performed so that polar charges have substantially the same potential. As a result, the potentials of the capacitors C1 and C3 become substantially the same, and there is almost no gradation difference between the first subpixel 41 and the second subpixel 42.

Next, differences between the display device according to

Embodiment

1 or 2 and the first reference display device and the second reference display device having a different configuration from the display device will be described. FIG. 8 is an example of an equivalent circuit diagram of the display panel 1 according to the first reference display device.

As shown in FIG. 8, in the first reference display device, each auxiliary gate line SG _n is connected to the gate terminal portion 3, and the auxiliary gate lines SG _n and the gate lines G _n are densely packed in the non-display region 1b. . Therefore, L / S (Line and Space), that is, the width of the wiring and the gap between the wirings are smaller than those of the display device according to the first or second embodiment, and the yield of the display panel 1 is reduced.

FIG. 9 is an example of an equivalent circuit diagram of the display panel 1 according to the second reference display device. As shown in FIG. 9, in the second reference display device, the auxiliary gate line SG _n is not connected to the gate terminal portion 3, the auxiliary gate line SG _n is connected to the gate line G _{n + 4.}

The “H” signal is input to the gate line G _n , the thin film transistors T1 and T2 are turned on, and the capacitors C1 and C2 and the capacitors C3 and C4 are charged, respectively. Thereafter, the “L” signal is input to the gate line G _n , the “H” signal is input to the auxiliary gate line SG _n , the thin film transistor T3 is turned on, and the charge held in the capacitors C3 and C4 is input to the capacitor C5. Dispersed, the potential of the capacitor C3 slightly decreases. Usually, since the polarity of the voltage applied to each pixel is inverted every frame, the charge remaining in the capacitor C5 before the thin film transistor T3 is turned on is charged to the capacitors C3 and C4 when the thin film transistor T2 is turned on. When the thin film transistor T3 is turned on, the charges of the capacitors C3 and C4 and the charge of the capacitor C5 having the opposite polarity cancel each other, and the voltage on the drain electrode side of the thin film transistor T2 drops. To do. As a result, a difference occurs between the potentials of the capacitors C1 and C3, resulting in a gradation difference.

In the second reference display device, the wiring pattern is fixed, and when the “H” signal is input to the gate line G _{n + 4} , the “H” signal is input to the auxiliary gate line SG _n . Therefore, the scanning direction of the gate line is limited to the forward direction (G _n → G _{n + 1} → G _{n + 2} → G _{n + 3} → G _{n + 4} →...). When the gate line is scanned in the reverse direction (G _{n + 4} → G _{n + 3} → G _{n + 2} → G _{n + 1} → G _n →...), It does not match the circuit structure shown in FIG. Because it does not. The structural, it is impossible to keep the auxiliary gate line SG _n to Low, it is impossible to perform the third driving method described above.

The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The technical features described in each embodiment can be combined with each other, and the scope of the present invention is intended to include all modifications within the scope of the claims and the scope equivalent to the scope of the claims. .

DESCRIPTION OF SYMBOLS 1 Display panel

1a Display area

1b Non-display area 3 Gate terminal part 11 1st signal line 12 2nd signal line 13 3rd signal line 40 Pixel electrode (pixel)
41 1st subpixel 42 2nd subpixel 70 Control part (1st control part, 2nd control part, 3rd control part)
T1, T2 Thin film transistor (sub-pixel switching element)
T3 thin film transistor (control switching element)
G _n gate lines SG _n auxiliary gate line S1 first switching element S2 second switching element S3 third switching element

Claims

A display panel having a display area and a non-display area located around the display area, a plurality of subpixel switching elements corresponding to a plurality of subpixels constituting pixels of the display panel, and one subpixel switching element Connected to the control switching element for controlling the potential difference between the sub-pixels, the gate terminal portion located in the non-display region, the gate terminal portion and the plurality of sub-pixel switching elements, In a display device comprising: a plurality of gate lines extending in one direction; and an auxiliary gate line extending in the first direction between the plurality of gate lines and connected to a control terminal of the control switching element.
In the non-display area, the auxiliary gate line is not connected to the gate terminal portion,
A first signal line and a second signal line extending along a second direction intersecting the first direction in the non-display area;
A first switching element that is disposed in the non-display region and controls connection between the auxiliary gate line and the first gate line based on a signal from the first signal line;
A second switching element that is disposed in the non-display area and controls connection between the auxiliary gate line and the second gate line based on a signal from the second signal line. Display device.
The display device according to claim 1, further comprising: a first control unit that turns off the second switching element when the first switching element is turned on.
The display device according to claim 1, further comprising: a second control unit that turns on the second switching element when the first switching element is turned off.
A third signal line extending along the second direction in the non-display area;
A third switching element that is arranged in the non-display area and controls connection between the auxiliary gate line and the third gate line based on a signal from the third signal line. The display device according to claim 1.
The display device according to claim 4, further comprising: a third control unit that turns off the first switching element and the second switching element when the third switching element is turned on.