KR100892857B1 - Internal memory of system on chip and operation method thereof - Google Patents

Abstract

An internal memory device of an SoC(System on Chip) and an operation method thereof are provided to set up the areas of an instruction memory and data memory dynamically according to the size of an execution file in a microprocessor of the SoC having the Harvard architecture. An internal memory is divided into a plurality of logic blocks(40). According to the first set value, the first MUX(50) is connected to some of the logic blocks. The first MUX forms an instruction memory interface to set up an instruction memory area. According to the second set value, the second MUX(60) is connected to the rest logic blocks. The second MUX forms a data memory interface to set up a data memory area. The first and second set values set up the size obtained by summing the size of RO(Read Only) data and the size of RW(Read Write) data as the size of a logic block.

Description

System-on-chip internal memory device and its operation method {INTERNAL MEMORY OF SYSTEM ON CHIP AND OPERATION METHOD THEREOF}

The present invention relates to an internal memory device of a system-on-chip and a method of operating the same. More specifically, the microprocessor of a system-on-chip having a Harvard architecture is limited by dynamically setting an area of an instruction memory and a data memory according to the size of an executable file. The present invention relates to an internal memory device of a system-on-chip and an operating method thereof capable of efficiently using a conventional memory capacity.

Recent application specific integrated circuit (ASIC) technology is shifting from a chip set based to an embedded core based system on chip (SoC). An SoC is an IC that connects a plurality of VLSI (cores) of a single type to each other to realize all the functions of an intended application. The SoC is composed of pre-designed models with complex functions for realizing various applications called "cores".

These cores are typically provided in the form of soft cores written in high-level description languages (HDL) such as Verilog or VHDL, or in the form of hard cores in transistor-level layouts such as GDSII. Hard cores and soft cores are often combined to realize functions on a chip as a memory array, a voice or video controller, a modem, a two-dimensional or three-dimensional graphics controller, or a DSP.

The use of these SoCs not only reduces the size of the system, but also offers a number of advantages in terms of cost compared to combining all the basic hardware components on the board.

Generally, the Harvard architecture has a separate memory interface for the processor core of the system-on-chip to read instructions and a memory interface for reading and writing the data so that the data can be read or written simultaneously while reading the instructions, and the data can be read while the data is read or written. It is a structure that can process instructions and data simultaneously in one CPI (Clock cycles Per Instruction) of the system and has a fast execution speed.

1 is a block diagram illustrating an internal memory device of a system-on-chip having a Harvard architecture.

As shown here, there is an instruction memory 10 for storing instructions and a data memory 30 for storing general data, and a memory for reading instructions from the instruction memory 10 in the microprocessor 20. It has a separate memory interface for reading and writing data into the interface and the data memory 30, and is configured to read or write data while reading commands.

In general, the ARM-based processor is composed of Instruction Tightly-Coupled Memory (ITCM) and Data Tightly-Coupled Memory (DTCM).

2 is a diagram illustrating a structure in which an executable file is generally stored in an internal memory.

Executable files are divided into RO (Read Only) data, RW (Read Write) data, and ZI (Zero Initial) data according to the data type. RO data is stored in the RO area, and RW data is stored in the RW area. Data is stored in the ZI area.

In this case, the command belongs to the RO area, and data with an initial value belongs to the RW area and, in the case of uninitialized data, to the ZI area, respectively.

The classification of such data is classified by the compiler when generating an executable file, and the linker collects such data to generate an executable file using a scatter loading file.

 After the executable file is loaded into the processor internal memory, the RO data is loaded into the instruction memory and the RW and ZI data are loaded back into the data memory.

The technology described above refers to the background of the technical field to which the present invention belongs, and does not mean the prior art.

As such, regardless of the amount of command memory and data memory required by an executable file, each unused memory exists by using fixed memory, or when the size of the executable file is increased due to the change of the executable file of the software. There is a problem that occurs when the capacity of the command memory or data memory is insufficient.

In addition, if the memory capacity is insufficient when the chip with the built-in instruction memory and data memory is already produced, to solve the problem, the chip which has increased the memory capacity is removed, or the necessary functions of the software are removed or optimization techniques are performed. We used to reduce the size of executables.

However, when the capacity of the memory needs to be increased, the chip needs to be manufactured again, which leads to additional time, chip size, and development cost.

In addition, when reducing the size of the executable file of the software, there is a limit to reduce the size, there is a problem that additional cost is consumed to optimize the execution code, and in the worst case may be missing the software function.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. In the microprocessor of a system-on-chip having a Harvard architecture, a limited memory capacity is set by dynamically setting an area of an instruction memory and a data memory according to an executable file size. An object of the present invention is to provide an internal memory device and a method of operating the same, which can be efficiently used.

An internal memory device of a system on chip according to an aspect of the present invention includes an internal memory device of a system on chip including a microprocessor having a command memory interface and a data memory interface; An internal memory divided into a plurality of logical blocks; A first mux connected to some of the plurality of logical blocks of the internal memory according to the first setting value to form a command memory interface to set a command memory area; And a second mux connected to other portions of the plurality of logical blocks of the internal memory to form a data memory interface according to the second set value to set a data memory region.

In the present invention, the first to second setting values may be set to the size of the logical block by adding the RO data size and the RW data size generated when the execution file is generated.

A memory device operating method of a system-on-chip according to an aspect of the present invention is connected to a part of the internal memory divided into a plurality of logical blocks according to a first or second set value and the other part of the first mux to set an instruction memory area. A method of operating a memory device of a system on a chip, the method comprising: a second mux connected with a second memory to set a data memory area; Loading a size of RO data and a size of RW data when an execution image is loaded into the memory by a boot loader; Calculating the number of logical blocks capable of storing the sum of the size of the RO data and the size of the RW data; And setting the command memory area and the data memory area by setting first to second set values according to the calculated number of logical blocks.

In the present invention, the second predetermined value is set according to the number of calculated logical blocks subtracted from the plurality of logical blocks.

In the present invention, the data memory area is characterized by including at least one logical block.

As described above, the present invention can efficiently use the limited memory capacity by dynamically setting the area of the instruction memory and the data memory in accordance with the size of the executable file in the microprocessor of the system-on-chip having the Harvard architecture. Reduce waste

In addition, the lack of memory can reduce the effort to adjust the function of the software to be loaded into the memory, and reduce the cost incurred to rebuild the chip.

In addition, by efficiently using the capacity of the memory it is possible to reduce the overall size of the chip.

Hereinafter, an embodiment of an internal memory device and a method of operating the same according to the present invention will be described with reference to the accompanying drawings. In this process, the thickness of the lines or the size of the components shown in the drawings may be exaggerated for clarity and convenience of description. In addition, terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to the intention or convention of a user or an operator. Therefore, definitions of these terms should be made based on the contents throughout the specification.

3 is a block diagram illustrating an internal memory device of a system on chip according to an embodiment of the present invention.

As shown here, the internal memory device of the system-on-chip is composed of a microprocessor 10 having an instruction memory interface and a data memory interface, and n first to nth logical blocks (# 1 to #n) by a Harvard architecture. The command memory region is formed by forming the command memory interface by being connected to the internal memory 40 and a part of the first to nth logical blocks # 1 to #n of the internal memory 10 according to the first set value. And a first mux 50 for setting the data and other portions of the first to nth logical blocks # 1 to #n of the internal memory 40 according to the second set value to form a data memory interface. A second mux 60 for setting a memory area is included.

In this case, the first to second setting values of the first mux 50 and the second mux 60 are set to the size of the logical block by adding the RO data size and the RW data size generated when the execution file is generated to the size of the logical block. Set the area and data memory area.

Although the RW data should be loaded into the data memory area when an executable file is generated as shown in FIG. 2, the reason for setting the instruction memory area is that the system is software-restarted and requires data initialization. This is because the memory of the instruction memory must be reserved in case.

Since ZI data is a value initialized to 0, it is not necessary to secure an instruction data area.

As described above, the first mux 50 is connected to the first logical block # 1 and the second logical block # 2 by the first setting value to form a command memory interface, and thus the first mux 50 is connected to the first logical block # 1. The instruction memory area is set by the second logical block # 2.

On the other hand, the second mux 60 is connected to the third to nth logical blocks # 3 to #n by the second setting value to form a data memory interface, thereby forming the third to nth logical blocks ( # 1 to #n) to set the data memory area.

Therefore, when the executable file is generated, the microprocessor 20 copies the executable file to the command memory area and the data memory area dynamically set by the first mux 50 and the second mux 60 according to the size of the executable file. Initialize

4 is a view illustrating an operation method for explaining in detail a method of dynamically setting an instruction memory area and a data memory area according to an executable file size in an internal memory device of a system-on-chip according to the present invention. It is a flow chart.

First, when the execution image is loaded into the internal memory 40 by the boot loader, the size of the RO data and the size of the RW data are loaded (S10).

In this case, the RW data is loaded into the data memory area when an executable file is created, but it is a reference for setting the area of the command memory in case the system is restarted by software and the data needs to be initialized.

As described above, the number of logical blocks capable of storing the sum of the sizes is calculated based on the sum of the sizes of the RO data and the sizes of the RW data (S20).

As the number of logical blocks calculated as described above becomes the size of the instruction memory area, the first set value is set to be connected to the number of logical blocks of the first mux 50 to form an instruction memory interface (S30).

In the above, the size of the instruction memory area does not exceed the size of the entire internal memory 40. In other words, the scatter loading file not only allows the developer to specify the starting location information of RO data, RW data, and ZI data, but also executes a predetermined size or more that the memory allows by inputting the maximum allowable executable file size. You can prevent the file from being created.

In this case, the size of the command memory area is set to ensure a data memory area of at least one logical block size in the entire internal memory 40.

Thereafter, a second set value is set so that the logical block except for the logical block connected by the first mux 50 is connected by the second mux 60 to form a data memory area (S40).

When the size of the instruction memory area and the data memory area is determined as described above, the RW data is copied to the data memory area, the ZI data is initialized to 0, and then the necessary procedure is continued (S50).

As described above, according to the present invention, the entire execution file is loaded into the internal memory 40, and before the RO data, the RW data, and the ZI data are distributed and loaded into the instruction memory area and the data memory area according to the distributed loading file rule. The size of command memory area among all internal memory is set by using size information of RO data, RW data, and ZI data generated at the time of file creation, and the remaining memory area is set as data memory area. Can be used as

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and those skilled in the art to which the art belongs can make various modifications and other equivalent embodiments therefrom. Will understand. Therefore, the technical protection scope of the present invention will be defined by the claims below.

1 is a block diagram illustrating an internal memory device of a system-on-chip having a Harvard architecture.

2 is a diagram illustrating a structure in which an executable file is generally stored in an internal memory.

3 is a block diagram illustrating an internal memory device of a system on chip according to the present invention.

4 is a flowchart illustrating a method of operating an internal memory device of a system on chip according to the present invention.

   -Explanation of symbols for the main parts of the drawings-

10: instruction memory

20 microprocessor

30: data memory

40: internal memory

50: first mux

60: second mux

Claims (5)

An internal memory device of a system-on-chip including a microprocessor having an instruction memory interface and a data memory interface; An internal memory divided into a plurality of logical blocks; A first mux connected to some of the plurality of logical blocks of the internal memory according to a first setting value to form the command memory interface to set a command memory area; And A second mux connected to other portions of the plurality of logical blocks of the internal memory according to a second setting value to form the data memory interface to set a data memory region; and an internal memory of a system-on-chip Device. The internal memory of a system on a chip according to claim 1, wherein the first to second set values are set to a size of the logical block by adding the RO data size and the RW data size generated when the execution file is generated. Device. A first mux connected to a part of the internal memory divided into a plurality of logical blocks according to a first to second set value and a second mux connected to another part to set a data memory area; A memory device operating method of a system on a chip; Loading a size of RO data and a size of RW data when an execution image is loaded into the internal memory by a boot loader; Calculating the number of logical blocks capable of storing the sum of the size of the RO data and the size of the RW data; And And setting the command memory area and the data memory area by setting the first to second setting values according to the calculated number of logical blocks. 4. The method of claim 3, wherein the second set value is set according to the number of the calculated logical blocks subtracted from the plurality of logical blocks. The method of claim 3, wherein the data memory area includes at least one logical block.

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