KR100891412B1 - Method of manufacturing a flash memory device - Google Patents

Abstract

The present invention includes forming a gate insulating film pattern on a region where a word line, a drain selection line, and a source selection line are to be formed on a semiconductor substrate, and including a first opening on the semiconductor substrate, between the word line and the drain selection line, Forming a mask film pattern including a second opening between the word line and the source selection line, performing a first ion implantation process to form a first junction region in the semiconductor substrate according to the mask film pattern, and a mask film Remove the pattern. And forming a gate pattern on the gate insulating layer pattern, and performing a second ion implantation process to form a second junction region on the semiconductor substrate on which the gate pattern is formed.

Flash, select line, word line, ion implantation, disturb, coupling

Description

Method of manufacturing a flash memory device

1A to 1F are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.

2A to 2E are cross-sectional views illustrating a method of manufacturing a flash memory device according to another exemplary embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a flash memory device according to still another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 200, 300: semiconductor substrate 102, 202, 302: gate insulating film

104, 212, 312: first mask film pattern 106, 204, 304: first conductive film

108, 206, 306: dielectric film 110, 208, 308: second conductive film

112, 210, 310: Hard Mask Film Pattern

The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a selection transistor during a manufacturing process of a flash memory device.

Flash memory devices generally have a structure in which a plurality of memory cells are arranged on a semiconductor substrate. Specifically, a gate insulating film, a first conductive film for floating gate, a dielectric film, and a second conductive film for a control gate are formed on a semiconductor substrate on which the device isolation film is formed. An etching process is performed to pattern the gate. Then, a plurality of memory cells are formed and select transistors are formed on both sides of the plurality of cells. The select transistor is a transistor formed in a drain select line (DSL) region and a source select line (SSL) region. After the gate is patterned, an ion implantation process is performed to form a junction region in the exposed semiconductor substrate between the plurality of memory cells and the plurality of select transistors.

The flash memory device may apply a high voltage to the gate and the junction in the program and erase states, or maintain a floating state of the high voltage. When the selected cell is programmed or erased, a case where adjacent information of the same word line and string cells are interchanged may occur. This is called disturb, and if it occurs during program operation, it is called program disturb, and if it occurs during erase operation, it is called erase disturb.

In particular, as integration becomes more sophisticated and design rules become more sophisticated, flash memory devices become more vulnerable to disturbances, and word lines adjacent to the source select transistors have exceptional program disturbs. This is boosted in the channel when the program voltage is applied to the word line of the unselected cell, so that the electric field may be concentrated according to the doping level near the edge of the source select transistor. Accordingly, excessive GIDL (Gate Induced Drain Leakage) phenomenon occurs, which may generate hot carriers, causing program disturb in adjacent word lines.

Accordingly, in the present invention, before forming the gate pattern, an ion implantation process having a different concentration is applied to the selection line region to form a junction region, thereby having different channel concentrations between the word line region and the selection line.

Another aspect of the present invention is to provide a method of manufacturing a flash memory device in which a program disturb is reduced by changing an ion implantation level in one direction selectively to a channel of a selection line.

In the method of manufacturing a flash memory device according to an embodiment of the present invention, a gate insulating layer pattern is formed on a region where a word line, a drain select line, and a source select line are to be formed on a semiconductor substrate. A mask layer pattern including a first opening between the word line and the drain selection line and a second opening between the word line and the source selection line is formed on the semiconductor substrate. According to the mask film pattern, a first ion implantation process for forming a first junction region in a semiconductor substrate is performed. The mask film pattern is removed. A gate pattern is formed on the gate insulating layer pattern. And a second ion implantation process for forming a second junction region on a semiconductor substrate having a gate pattern formed thereon.

The gate pattern is formed by stacking a first conductive film, a dielectric film, a second conductive film, and a hard mask film pattern on the gate insulating film pattern.

The width of the first opening is 1/2 between the word line and the drain selection line, and the width of the second opening is 2/3 between the word line and the source selection line.

The first ion implantation process is carried out with an energy of 2 to 20 KeV using a p type dopant.

The p type dopant is carried out using BF ₂ at a concentration of 2.0E1 to 2.0E12ions / cm 2.

The second ion implantation step is performed at a higher concentration of dopant than the first ion implantation step.

In a method of manufacturing a flash memory device according to another embodiment of the present invention, gate patterns of a word line and a selection line are formed on a semiconductor substrate. A first junction region is formed in the semiconductor substrate between the gate patterns. The second junction region is formed by applying a lower energy to the first junction region between the word line and the selection line than the step of forming the first junction region. A method of manufacturing a flash memory device includes forming a third junction region between a first junction region and a second junction region between gate patterns.

The gate patterns are formed by stacking a gate insulating film, a first conductive film, a dielectric film, and a second conductive film.

The second junction region uses high mass impurities and the third junction region uses any one of As (Arsenic), Sb (Antimony), Bi (Bismuth), or B (Boron).

The second junction region is formed by performing an ion implantation process to apply energy of 10 KeV to 20 KeV.

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The second junction region is formed by performing an ion implantation process for implanting P-type impurities.
In the method of manufacturing a flash memory device according to another embodiment of the present invention, gate patterns of word lines and select lines are formed on a semiconductor substrate. A first junction region is formed between the word line and the selection line, in contact with an edge of the selection line and not in contact with the word line. And forming second junction regions on the semiconductor substrate between the gate patterns.
The first junction region is formed by performing an ion implantation process that gives an inclination angle to the incident angle of impurities. At this time, the ion implantation process is performed by giving an angle of 5 degrees to 45 degrees in the inclination angle.
The first junction region is formed by performing an ion implantation process of 1E11 to 1E13ions / cm 2 dose and is formed by implanting P-type impurities.

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Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1A to 1F are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.

Referring to FIG. 1A, a gate insulating layer 102 is formed on a semiconductor substrate 100 on which an isolation layer is formed.

Referring to FIG. 1B, the gate insulating layer pattern 102a is formed by patterning a portion of the gate insulating layer to remain. In this case, the gate insulating layer is patterned to remain only in the region where the drain select line, the source select line, and the word lines are to be formed.

Meanwhile, a gate pattern is formed by laminating a gate insulating film, a first conductive film for a floating gate, a dielectric film, and a second conductive film for a control gate on a semiconductor substrate. However, as the degree of integration of the flash memory device increases, the spacing between the memory cells in which the word lines are formed decreases, and as the thickness of the dielectric film increases as the spacing between cells decreases, the coupling ratio is increased. Decreases. This slows down the program's operating speed, which in turn increases the boron concentration in the cell region.

However, the threshold voltage of the select transistor is increased and the channel boosting level is reduced by the amount of the increased threshold voltage, thereby degrading program disturb characteristics. In addition, when the channel concentration of the cell region and the channel concentration of the region where the selection transistor is formed are formed at the same concentration, as the integration degree increases, the threshold voltage of the selection transistor increases.

Therefore, the threshold voltage of the selection transistor should be lowered within the range in which leakage current of the selection line does not occur. To compensate for this, a method of performing an ion implantation process after forming the gate electrode is used. However, this is very likely to cause a punch through phenomenon between the drain and the source, which may result in leakage current generation in the unselected block.

Therefore, in the present invention, impurities are implanted into the junction of the selection transistor before the floating gate conductive film is formed over the gate insulating film.

Referring to FIG. 1C, a mask layer pattern 104 having a word line region closed is formed on a semiconductor substrate 100 on which a gate insulating layer pattern 102a is formed. The mask layer is exposed so that a portion A between the drain select line (DSL) region and the word line region is exposed and a portion B between the source select line (SSL) region and the word line region is exposed. Pattern 104 is formed. In this case, the region B in which the semiconductor substrate 100 is exposed between the source selection line SSL and the word line region is larger than the region A in which the semiconductor substrate 100 is exposed between the drain selection line DSL and the word line region. wide. In an exemplary embodiment, the interval A between the drain select line DSL and the word line region exposed may be 1/2 of the interval between the drain select line DSL and the word line region. The interval B between the source selection line SSL and the word line region exposed is two thirds of the interval between the source selection line SSL and the word line region. The reason for this is to minimize the gate induced drain leakage (GIDL) flow leakage current between the drain and the gate when a voltage is applied to the gate.

A first ion implantation process is performed to form the first junction W1 in the semiconductor substrate 100 exposed between the drain and source select line regions DSL and SSL. The first ion implantation process is performed at an energy of 2 to 20 KeV using a P type dopant to form a shallow junction. For example, the P type dopant may be performed at a concentration of 2.0E1 to 2.0E12ions / cm ₂ using BF ₂ . As a result, a first junction W1 is formed between the drain and the source selection line DSL and SSL regions having a concentration lower than that between the channel lines of the word line region. At this time, the ion implantation may also be performed to the semiconductor substrate 100 under the gate insulating layer pattern 102a formed in the selection transistor region, but does not serve as a substantial junction.

In addition, an ion implantation process may be performed using a P type dopant in a word line region at a dopant concentration different from that of the first ion implantation process. In other words, it is important to differentiate the dopant serpent injected into the word line region and the selection line (DSL and SSL) regions, so that ion implantation is selectively performed in the word line region. In this case, the ion implantation process may be performed only on the word line region by using an open mask layer pattern.

Referring to FIG. 1D, the first mask layer pattern is removed. The first conductive layer 106 for the floating gate is formed on the semiconductor substrate 100 including the gate insulating layer pattern 102a, and a device isolation layer (not shown) is formed by a self-aligned STI (SA-STI) process. The dielectric layer 108, the second conductive layer 110 for the control gate 110, and the hard mask layer pattern 112 are sequentially formed on the semiconductor substrate 100 including the device isolation layer (not shown) and the first conductive layer 106. Form. Before the second conductive layer 110 is formed, a predetermined region of the dielectric layer 108 in a region where drain and source select lines DSL and SSL are to be formed is removed.

Referring to FIG. 1E, in order to form the second conductive film pattern 110a, the dielectric film pattern 108a, the first conductive film pattern 106a, and the gate insulating film pattern 102a, the hard mask film pattern 112 may be formed. Perform the etching process. As a result, word lines WL0 to WLn (where n is an integer), a drain select line DSL, and a source select line SSL are formed. The first conductive film pattern 106a and the second conductive film pattern 110a constituting the drain and source selection lines DSL and SSL are in contact with each other to form a transistor.

Referring to FIG. 1F, a second ion implantation process may be performed on a semiconductor substrate 100 including word lines WL0 to WLn, a drain select line DSL, and a source select line SSL. W2) is formed.

A first ion implantation process having a low dopant concentration is performed in the drain and source selection lines DSL and SSL, and a second ion implantation process having a high or similar dopant concentration is performed in the wordline region. The second ion implantation step is carried out using an N type dopant. As a result, the junction concentrations of the word line WL0 to WLn regions and the selection line DSL and SSL regions may be formed differently to lower the threshold voltages of the drain selection line DSL and the source selection line SSL.

2A to 2D are cross-sectional views illustrating a method of manufacturing a flash memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 2A, a gate insulating film 202, a floating gate first conductive film 204, a dielectric film 206, a control gate second conductive film 208, and a hard mask film are formed on a semiconductor substrate 200. The pattern 210 is formed. The dielectric film 206 has a pattern in which a predetermined region is removed.

Referring to FIG. 2B, an etching process is performed to form word lines WL0 to WL2, source select lines SSL, and drain select lines DSL according to the hard mask layer pattern 210. Substantially, a plurality of word lines WL0 to WL2 are formed, but only some of them are shown in the drawings for convenience. The etching process forms the second conductive film pattern 208a, the dielectric film pattern 206a, the first conductive film pattern 204a, and the gate insulating film pattern 202a. In the source selection line SSL, the first conductive layer pattern 204a and the second conductive layer pattern 208a are in contact with each other to form a transistor.

Referring to FIG. 2C, the first junction S1 is formed on the semiconductor substrate 200 including the gate patterns to form a first junction S1. The first ion implantation process implants a P type dopant. Specifically, the first junction S1 is formed in the semiconductor substrate 200 exposed between the word lines WL0 to WLn, the source select line SSL, and the drain select line DSL.

Referring to FIG. 2D, a first mask layer pattern 212 is formed on the semiconductor substrate 200 to expose a junction between the source selection line SSL and the word line WL0. Although not shown in the drawing, the first mask layer pattern 212 simultaneously exposes the junction between the drain select line DSL and the word line adjacent thereto.
Subsequently, a second ion implantation process is performed on the first junction S1 exposed between the source select line SSL and the word line WL0 adjacent thereto, and between the drain select line DSL and the word line adjacent thereto. (S2) is formed (S1 + S2). The second ion implantation process is also performed at a lower energy range than the first ion implantation process using a P type dopant, which is performed in a low energy range of 10 to 20 KeV.

On the other hand, since the ion implantation concentration cannot be increased indefinitely to prevent leakage current when forming junctions between the word lines WL0 to WL2, the source selection line SSL and the word lines WL0 to WL2) It is very difficult to get rid of depletion of the liver. To compensate for this, a high electric field is prevented from occurring between the cell region Cell and the source select line SSL and the drain select line DSL. As a result, the ion implantation concentration is different for each of the regions where the word lines WL0 to WL2, the source selection line SSL, and the drain selection line DSL are formed. Importantly, in order to minimize leakage current generation between the source select line SSL or the drain select line DSL and the adjacent cells, the second ion implantation energy is performed under very low conditions (10 to 20 Kev). In addition, the impurities in the second ion implantation process use a high mass dopant in order to minimize the thermal budget diffused by the subsequent thermal process.

Referring to FIG. 2E, the first mask layer pattern is removed to expose the word line region and the select line region. A third junction S3 is formed in the inter-gate semiconductor substrate 200 by performing an N type third ion implantation process. In this case, the junction between the word lines WL0 to WLn overlaps the first junction S1 and the third junction S3. First to third junctions S1 to S3 are overlapped with the junction between the source select line SSL, the adjacent word line, the drain select line DSL, and the adjacent word line. The third ion implantation process is performed using any one of N type As (Arsenic), Sb (Antimony) or Bi (Bismuth).

As a result, the junction between the source select line SSL and the word line adjacent thereto and the drain select line DSL and the word line adjacent thereto may be formed at an equipotential to improve program disturb.

3A to 3E are cross-sectional views illustrating a method of manufacturing a flash memory device according to still another embodiment of the present invention.

Referring to FIG. 3A, a gate insulating film 302, a first conductive film 304 for a floating gate, a dielectric film 306, a second conductive film 308 for a control gate, and a hard mask film are formed on a semiconductor substrate 300. The pattern 310 is formed. Prior to forming the second conductive film 308, a portion of the dielectric film 306 on the source select line SSL region is removed so that a portion of the first conductive film 304 and the third conductive film 308 contact each other. .

Referring to FIG. 3B, an etching process is performed to form a gate pattern according to the hard mask layer pattern 310.

Referring to FIG. 3C, the first mask layer pattern 312 having an open junction between the source selection line SSL and the word line WL0 adjacent thereto is formed, and the source selection line SSL and the word line adjacent thereto are formed. A first ion implantation process is performed on the semiconductor substrate 300 exposed between WL0. Importantly, the first junction T1 is formed in the semiconductor substrate 300 adjacent to the edge of the source selection line SSL by giving an inclination angle during the first ion implantation process. The angle of inclination forms an angle of 5 to 45 degrees. In the first ion implantation process, the first junction T1 is formed in the semiconductor substrate 300 adjacent to the source select line SSL by using a P type impurity. As a result, the first junction T1 is formed under the edge of the source selection line SSL in the semiconductor substrate 300.

The first ion implantation process is carried out using boron with a dose of 1E11 to 1E13ions / cm 2 and an energy of 1 to 50 KeV.

Referring to FIG. 3D, the first mask layer pattern is removed, and a second ion implantation process is performed on the semiconductor substrate 300 including the gate pattern. An N-type impurity is implanted in the second ion implantation process, and the ion implantation concentration is higher than the impurity concentration in the first ion implantation process to form the second junction T2.

Referring to FIG. 3E, a heat treatment process is performed to remove hot carriers. The heat treatment process may be performed by a rapid thermal annealing process (RTP). Rapid heat treatment process is carried out at a temperature of 500 to 1500 ℃, it is carried out by raising to a temperature of 50 to 300 ℃ per second. In order to suppress the heat treatment oxidation, Ar (Argon), Ne (Neon) and N ₂ (Nitrogen) gas is carried out in a single or mixed atmosphere.

The heat treatment process may be carried out in two stages (first heat treatment and second heat treatment). In the first heat treatment process, activation energy is applied so that the junctions of the P + and N + types are neutral, and are performed at a temperature of 500 to 1000 ° C. The second heat treatment step is carried out at a temperature of 800 to 1500 ° C.

As a result, it is possible to reduce disturbance during operation of the flash memory cell, thereby reducing wafer test time. In addition, the failure is reduced due to the reduction of the disturbance (fail) can be improved yield.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

Effects according to the embodiment of the present invention are as follows.

First, since the selection line is not exposed during the ion implantation process, a stable channel concentration can be formed.

Second, the program speed can be improved by applying a high boron concentration to the word line region.

Third, it is possible to reduce the occurrence of leakage current of blocks not selected during the program operation of the device.

Fourth, the lowering of the threshold voltage of the selection line may improve the decrease of the channel boosting level.

Fifth, yield can be improved by reducing disturbance between word lines.

Claims (23)

Forming a gate insulating layer pattern on a region where a word line, a drain select line, and a source select line are to be formed on the semiconductor substrate; Forming a mask layer pattern on the semiconductor substrate, the mask layer pattern including a first opening between the word line and the drain selection line and a second opening between the word line and the source selection line; Performing a first ion implantation process to form a first junction region in the semiconductor substrate according to the mask film pattern; Removing the mask layer pattern; Forming a gate pattern on the gate insulating layer pattern; And And performing a second ion implantation process to form a second junction region in the semiconductor substrate on which the gate pattern is formed. The method of claim 1, And the gate pattern is formed by stacking a first conductive film, a dielectric film, a second conductive film, and a hard mask film pattern on the gate insulating film pattern. The method of claim 1, The mask layer pattern is a method of manufacturing a flash memory device, the width of the first opening is formed narrower than the width of the second opening. The method of claim 1, The width of the first opening is 1/2 between the word line and the drain select line. The method of claim 1, And a width of the second opening is two thirds between the word line and the source select line. The method of claim 1, The first ion implantation process is a flash memory device manufacturing method using a type P dopant (dopant) at a energy of 2 to 20 KeV. The method of claim 6, The P-type dopant is a method of manufacturing a flash memory device used by applying BF ₂ in a concentration of 2.0E1 to 2.0E12ions / ㎠. The method of claim 1, And the second ion implantation step is performed at a higher concentration of the N-type dopant than the first ion implantation step. Forming gate patterns of word lines and select lines on the semiconductor substrate; Forming a first junction region in the semiconductor substrate between the gate patterns; Applying a lower energy to the first junction region between the word line and the selection line than forming the first junction region to form a second junction region; Forming a third junction region in the first junction region and the second junction region between the gate patterns. The method of claim 9, The gate patterns may be formed by stacking a gate insulating film, a first conductive film, a dielectric film, and a second conductive film. The method of claim 9, And the second junction region is formed using a high mass of impurities. The method of claim 11, And the third junction region uses an impurity of any one of N type As (Arsenic), Sb (Antimony), Bi (Bismuth), or B (Boron). The method of claim 9, The second junction region is formed by performing an ion implantation step of applying energy of 10 KeV to 20 KeV. delete delete delete delete The method of claim 9, The second junction region is formed by performing an ion implantation process of implanting the P-type impurities. Forming gate patterns of word lines and select lines on the semiconductor substrate; Forming a first junction region between the word line and the selection line, the first junction region being in contact with an edge of the selection line and not in contact with the word line; And Forming second junction regions in the semiconductor substrate between the gate patterns. The method of claim 19, The first junction region is formed by performing an ion implantation process of giving an inclination angle to the incident angle of the impurity. The method of claim 20, And the ion implantation step is performed at an angle of 5 degrees to 45 degrees with the inclination angle. The method of claim 19, The first junction region is formed by performing an ion implantation step of 1E11 to 1E13ions / ㎠ dose. The method of claim 19, The first junction region is formed by implanting a P-type impurities.

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