KR100503366B1 - Fabrication method of semiconductor device - Google Patents

Abstract

In order to provide a method of not reducing the length of the channel while solving the SAS resistance problem occurs when applying the SAS technology, the present invention comprises a first step of continuously forming a linear trench line on the semiconductor substrate; Forming a gate oxide film line on the semiconductor substrate other than the trench line; A third step of continuously forming gate lines perpendicular to the trench lines on the trench lines and the gate oxide film line; Etching a gate oxide line and a trench line between the gate lines; Implanting impurity ions into the etched region to form a self aligned source (SAS) region; Forming a spacer on sidewalls of the gate lines; A semiconductor device is manufactured by including a seventh step of further implanting impurity ions into a SAS region using the spacer as a mask.

Description

Fabrication method of semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for reducing SAS resistance in a cell region.

Recently, as the use of flash memory is becoming more popular and the price competition is fierce, the development of technology to reduce the size of the device becomes more active. One of the techniques for reducing the size of the device is a self aligned source (SAS) technology.

SAS technology is a technique for reducing cell size in the bit line direction, which is known from US Pat. No. 5,120,671. Such a SAS technology can reduce the gap between the gate and the source, which is an essential process in a technology having a line width of 0.25 μm or less, and the introduction of the SAS technology can reduce the cell size by about 20%.

Since the SAS region is formed along the trench profile, the junction resistance of the source per cell is rapidly increased.

On the other hand, most semiconductors use a shallow trench isolation (STI) technique as an isolation technique at 0.25 µm or 0.18 µm or less.

That is, the STI isolation technique is an essential technique for reducing the cell size in the word line direction and the SAS technique in the bit line direction. When the two techniques are simultaneously applied, there is a problem in that the source resistance is greatly increased.

Flash memory, in particular, uses an internal high voltage, and as the cell size shrinks, the depth of the trench deepens, adversely affecting the source resistance.

1 is a graph illustrating a simulation result of a change in source resistance according to a depth of a trench. As shown in this graph, when the depth of the trench is 2400 mW, the resistance per cell is about 400 Ohm, whereas when the depth of the trench is 3600 mW, the resistance per cell increases to about 780 Ohm.

In the case of embedded flash, the source resistance is required to be 400 Ohm or less in order not to affect read and programming operations. However, in the case of implanting As ions, the trench depth of the logic transistor is 3500Å in a 0.18µm flash memory cell, so the resistance per cell is about 700-900 Ohm, which is about twice the required resistance, resulting in a decrease in cell program characteristics and read speed. Fatal adverse effects on the product.

In order to solve this problem, ion implantation was performed in addition to P or As. However, when P or As is additionally implanted after the gate formation, the channel length is shortened to about 0.24 μm, resulting in a punch through.

In addition, further ion implantation has a problem of causing difficulty in miniaturization of the device in the future.

The present invention is to solve the problems as described above, the object is to solve the problem of increased resistance that occurs when applying SAS technology.

Another object of the present invention is to provide a method for solving the SAS resistance problem while not reducing the length of the channel.

In order to achieve the object as described above, the present invention comprises a first step of continuously forming linear trench lines in the semiconductor substrate; Forming a gate oxide film line on the semiconductor substrate other than the trench line; A third step of continuously forming gate lines perpendicular to the trench lines on the trench lines and the gate oxide film line; Etching a gate oxide line and a trench line between the gate lines; Implanting impurity ions into the etched region to form a self aligned source (SAS) region; Forming a spacer on sidewalls of the gate lines; A semiconductor device is manufactured by including a seventh step of further implanting impurity ions into a SAS region using the spacer as a mask.

Here, the method may further include forming a thermal oxide film on sidewalls of the gate lines between the fifth and sixth steps.

In the sixth step of forming the spacer, it is preferable to form the spacer film on the upper entire surface of the gate lines, and to etch back or chemical mechanically polish the spacer film until the top surface of the gate lines is exposed to leave the spacer film on the sidewalls of the gate lines.

The spacer is preferably formed of any one of nitride, oxide, and oxynitride.

It is preferable that the spacer has a width of 100-1500 GPa.

In the fifth and seventh steps, As ions are preferably implanted by 1 × 10 ¹⁴ -5 × 10 ¹⁵ / cm ³ .

In the fifth and seventh steps, As ions are preferably implanted at an energy of 5-40 keV.

The trench line is preferably parallel to the bit line direction and the gate line is parallel to the word line direction.

In the fourth step of etching, etching is performed using a mask including a portion of the gate line to expose the gate lines.

In the fourth step of etching, the etching rate of the insulating material forming the trench line is preferably higher than that of the semiconductor substrate.

The insulating material forming the trench line is preferably an oxide film.

The gate line preferably comprises a first polycrystalline silicon layer, a dielectric layer, and a second polycrystalline silicon layer.

Hereinafter, the present invention will be described in detail.

SAS technology is a technology that reduces the cell size in the bit line direction, and is used as an essential process in a technology having a line width of 0.25 μm or less because the gap between the gate and the source can be reduced.

In general, NOR type flash memory uses a common source method, and one contact is formed every 16 cells.

FIG. 2A is a plan view showing a conventional memory cell without SAS technology, FIG. 2B is a plan view showing a memory cell with SAS technology, and FIG. 2C is a cutaway view of FIG. This is a cross-sectional view.

In FIG. 2A, a field oxide region 10, which is a device isolation region, is formed in a bit line BL direction, and an adjacent region of the field oxide region 10 is defined as an active region 20 in which a device is formed. Drain contacts 30 are formed in each cell formed at 20.

A gate line 40 is formed in the word line WL direction, and the common source line 50 is formed in parallel with the gate line 40 while being spaced apart from the gate line 40 by a predetermined interval.

When the SAS technology is introduced into such a memory cell, as shown in FIGS. 2B and 2C, the field oxide region 60 formed in a portion corresponding to the conventional common source line 50 is etched and impurities are implanted into the SAS. Area 70 is formed.

Since the formed SAS region 70 is formed along the trench profile, the junction resistance of the source per cell is rapidly increased. The reason for the large resistance is because the resistance is formed along the trench profile, so the actual sheet resistance length becomes longer, and the specific resistance of the trench sidewalls increases.

In order to solve the problem that the length of the channel is shortened when applying the ion implantation method to solve this problem, in the present invention after forming a spacer on the sidewall of the gate line additionally implanted ions.

Next, a method of manufacturing a semiconductor device according to the present invention will be described in detail.

3A to 3D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present invention, which are cut along the bit line direction.

First, as shown in FIG. 3A, linear trench lines are continuously formed in the semiconductor substrate 100. At this time, the trench lines are formed parallel to the bit line direction.

Next, the gate oxide layer 110 is formed on the semiconductor substrate 100 except for the trench lines.

Next, gate lines are continuously formed on the trench line and the gate oxide line 110 in a direction perpendicular to the trench line, that is, in a direction parallel to the word line.

It is preferable to form a polysilicon layer as a gate line, and at this time, the first polycrystalline silicon layer 120, the composite dielectric layer 130 such as an oxide film-nitride-oxide film (ONO), and the second polysilicon layer 140 are formed. It may be formed to form a flash memory.

Next, the gate oxide film line and the trench line located between the gate lines are etched. In this case, etching may be performed using a mask including a portion of the gate line to expose the gate lines.

In this case, the etching rate of the insulating material, for example, the oxide layer forming the trench line, is preferably etched under a condition faster than that of the semiconductor substrate. In other words, high selective oxide etching conditions are used.

Next, as illustrated in FIG. 3B, impurity ions are implanted into the etched region to form a self aligned source (SAS) region 150.

As impurities, As or P may be ion implanted, and when As is ion is inclinedly implanted, an amount of 1 × 10 ¹⁴ -5 × 10 ¹⁵ / cm ³ dose may be injected at an energy of 5-40 keV.

Next, as shown in FIG. 3C, spacers 160 are formed on sidewalls of the gate lines. In this case, a thermal oxide film may be formed on the sidewalls of the gate lines in order to recover damage caused by ion implantation before forming the spacer and to prevent charge loss of the floating gate (first polysilicon layer) 120.

To form the spacer, a spacer layer is formed on the entire upper surface of the gate lines, and the spacer layer is etched back or chemically mechanically polished until the top surface of the gate lines is exposed, leaving the spacer layer only on the sidewalls of the gate lines.

Nitride, oxide and oxynitride can be formed as the spacer film.

In addition, the spacer is preferably formed to have a width of 100-1500 GPa.

Next, as shown in FIG. 3D, the impurity ions are further implanted using the spacer 160 as a mask to form the second impurity region 170.

Adding an impurity is implanted at 1 × 10 ¹⁴ If you can implanting As or P, tilt implanting As ion-implanting the dose may be 5 × 10 ¹⁵ / cm ³ in the amount of 5-40 keV energy .

In this manner, additional ion implantation after forming the spacer does not affect the length of the channel, thereby preventing punchthrough.

However, in the case of a NOR type flash cell, since programming is performed by hot carrier injection, a lightly doped drain (LDD) or a DDD is applied to the source and drain junctions of the cell. Does not form. However, if spacers are formed and additional As or P is injected, a step junction may be formed, which may interfere with programming efficiency. Therefore, in order to prevent this, a spacer having a sufficient thickness is formed and ion implantation energy and dose amount in accordance with the spacer. It is important to regulate it.

As described above, in the present invention, in the method of additionally performing impurity ion implantation for reducing the SAS resistance, by forming a spacer on the sidewall of the gate line after the primary ion implantation, and then further secondary ion implantation, In addition to reducing the SAS resistance, additionally implanted impurity ions due to the spacers do not affect the length of the channel.

Therefore, shortening of the channel length due to additional ion implantation is prevented, and thus punchthrough is prevented.

1 is a graph illustrating a simulation result of a change in source resistance according to a depth of a trench.

FIG. 2A is a plan view showing a conventional memory cell without SAS technology, FIG. 2B is a plan view showing a memory cell with SAS technology, FIG. 2C is a cross-sectional view taken along the line II ′ of FIG. 2B,

3A to 3D are cross-sectional views showing the semiconductor device manufacturing method according to the present invention according to the process procedure, cut in the bit line direction.

Claims (9)

A first step of continuously forming linear trench lines in the semiconductor substrate; Forming a gate oxide film line on the semiconductor substrate other than the trench line; A third step of continuously forming gate lines perpendicular to the trench lines on the trench lines and the gate oxide film line; Etching a gate oxide film line and a trench line between the gate lines; Implanting impurity ions into the etched region to form a self aligned source (SAS) region; Forming a spacer on sidewalls of the gate lines; A seventh step of further implanting impurity ions into the SAS region using the spacers as a mask; Semiconductor device manufacturing method comprising a. The method of claim 1, And forming a thermal oxide film on sidewalls of the gate lines between the fifth and sixth steps. The method of claim 1, In the sixth step of forming the spacer, after forming a spacer film on the upper front surface of the gate lines, the spacer film is etched back or chemical mechanical polishing until the upper surface of the gate lines are exposed to leave the spacer film on the sidewalls of the gate lines. Semiconductor device manufacturing method. The method of claim 1, The spacer is a semiconductor device manufacturing method for forming any one of nitride, oxide, and oxynitride. The method of claim 1, The trench line is parallel to the bit line direction, the gate line is parallel to the word line direction. The method of claim 1, In the etching of the fourth step, a method of manufacturing a semiconductor device is performed using a mask including a portion of the gate line to expose the gate lines. The method of claim 1, In the etching of the fourth step, the etching rate of the insulating material constituting the trench line is faster than the etching rate of the semiconductor substrate. The method of claim 7, wherein The insulating material constituting the trench line is an oxide film. The method of claim 1, The gate line comprises a first polysilicon layer, a dielectric layer, and a second polycrystalline silicon layer.