KR100890842B1 - A low energy adc - Google Patents

Abstract

The present invention relates to two or more A / D channels having an input and an output in which analog input signals are converted to digital output signals, each input of the A / D channel being coupled to a sample and hold unit, each input being A / D A multiplexing unit comprising two or more inputs coupled to an output of a channel, a parallel analog / digital converter (ADC) comprising a time control unit for clocking an A / D channel and controlling the multiplexing unit, wherein the analog / digital converter The digital converter is provided with means for switching between the so-called idle mode and the so-called normal mode. The invention also relates to a method for saving energy in parallel analog / digital conversion.

Parallel A / D converters, A / D channels, multiplexing units, time control units, sample and hold units.

Description

Low Energy Analog / Digital Converters {A LOW ENERGY ADC}

The present invention relates to a parallel analog-to-digital converter, and to a method of parallel analog-to-digital conversion according to the full text of claims 1 and 7.

Parallel analog / digital converters in accordance with the prior art, known in the art, are described in patent publications (“A 10-b, 100-MS / s CMOS A / D Converter, Kwang Young Kim, Student Member, IEEE, Naoya Kusayanagi, and Asad A. Abidi, Fellow, IEEE Journal of Solid State Circuits, Vol. 32, No. 3, March 1997 ".

One problem with this type of analog / digital converter is that it unnecessarily consumes high levels of energy.

It is an object of the present invention to reduce the power consumption of a parallel analog / digital converter.

This problem is addressed according to the invention using the apparatus and method according to the respective features of claims 1 and 7.

The environment in which parallel analog-to-digital converters are expected to be used is a system whose activity changes, for example, as used in digital subscriber loop (DSL) modems or mobile phone systems. They are not necessarily identical to each other, but are two equivalent systems that communicate with each other, for example, via a communication channel consisting of a cable or radio waves. If the communication takes place over radio waves, it is possible for many units to share one and the same communication channel.

One advantage of the present invention is that energy can be saved by adapting the A / D converter to universal requirements, instead of using only the on / off mode as in the conventional case.

Another advantage of the present invention is that the method can be easily implemented in a parallel A / D converter.

The invention is explained in more detail with reference to the preferred embodiments and the accompanying drawings.

1 illustrates an embodiment of a parallel analog / digital converter in which the power saving function of the present invention may be implemented.

2 shows another embodiment of a parallel analog / digital converter in which the power saving function of the present invention may be implemented.

In the illustrated embodiment of the parallel analog / digital converter according to FIG. 1, the analog input signal 5 has four A / D channels 20 each comprising a respective sample and hold unit 21, 23, 25 and 27. , 22, 24 and 26). The A / D channel has a signal input and a signal output. The sample and hold units 21, 23, 25 and 27 are monitored and controlled by the time control unit 10. In the case shown, the A / D channels 20, 22, 24 and 26 are connected to a power supply voltage source 50 which is an external power source. The power supply voltage switches 30, 32, 34 and 36 are arranged between the power supply voltage source 50 and the respective A / D channels. Signals 40, 42, 44 and 46 adjust the A / D channel between steady state and idle state under the control of vitality control 15. The vitality control 15 is in turn controlled by a system control unit (not shown). The outputs 40, 42, 44 and 46 on the A / D channel are multiplexed together in the multiplexing unit 17. The output signal from the multiplexing unit 17 is a digital representation of the analog input signal.

Since the parallel A / D converter has an operating cycle that extends for several clock cycles, it is necessary to determine the start time. In practice, the A / D channels are independent of each other. The time control unit 10 informs when each channel should be started. The time control unit 10 can also be used to reduce power consumption. If the operating sequence consumes more energy than in the idle state, energy can be saved by starting the A / D channel less frequently. A more obvious way to save energy is to switch off the supply voltage 50 via switches 30, 32, 34 and 36. For example, the power supply voltage 50 may be + 5V.

In the case of the embodiment of the parallel analog / digital converter shown in FIG. 2, the analog input signal 5 is excited to four A / D channels 20, 22, 24 and 26 via a common sample and hold unit 21. do. The A / D channel includes a signal input and a signal output. The sample and hold unit 21 is monitored and controlled by the time control unit 10. The power supply voltage source 50 is connected to the A / D channels 20, 22, 24 and 26, and in this case this power supply is an external power supply. The power supply voltage switches 30, 32, 34 and 36 are arranged between the power supply voltage source 50 and the respective A / D channels. Signals 40, 42, 44 and 46 adjust the A / D channel between steady state and idle state, under the control of vitality control 15. The vitality control 15 is in turn controlled by a system control unit (not shown). The outputs 40, 42, 44 and 46 on the A / D channel are multiplexed together in the multiplexing unit 17. The output signal from the multiplexing unit 17 is a digital representation of the analog input signal.

The practice of FIG. 2 in that a practical signal (input signal) is sampled and A / D converted using each period at a specific selected time instead of being sampled and A / D converted alone at a typical selection time. The example is different from the embodiment of FIG. The main difference is that it may be practical for some reason that only part of the A / D converter is cut off and the rest of the converter can be operated as usual. In this case the savings in energy become smaller, but this may be the procedure required when problems arise with routine initiation. S / H units 21, 23, 25 and 27 are examples of portions of A / D converters that may always be active.

In some cases, several A / D channels can be switched off in parallel analog / digital converters to save energy. Wake-up tones and alert tones may be detected using one or a few A / D channels. The frequency cannot be determined clearly. However, if a signal occurs that can be an accurate signal, the other A / D channels are alerted and scrutinized.

Standby mode often requires lower performance. For example, low performance can be achieved by lowering the clock frequency or changing the current of op amps and comparators, which are the building blocks of the A / D channels.

Pipelined or successive approximation type A / D converters operate using algorithms to find the digital representation of the analog input signal. The algorithm starts with the most significant bit and gets a sub-result. The accuracy of the sub result increases as the bits are calculated. If the required precision of the digital output signal is low, energy can be saved by terminating the conversion after achieving the desired accuracy.

In general, high power input is required to achieve high performance. Not much precision or energy consumption is needed to detect the presence of an active signal. Several situations can be considered about this. The first situation is that the communication channel is idle when not in use. The signal is sent when the system is activated. This is sufficient to detect the presence of a signal. The second situation is when noise and other traffic appear on the communication channel when the channel is not used. It is then necessary to detect the specific tone and group of tones. However, detecting the presence of tone (s) is sufficient. The third situation is when the incoming activation signal includes an address start or message at which a unit is activated. In this case it is necessary to decode the message first. According to the invention, an analog / digital conversion is used to detect the presence of a signal in the first situation. This detection is performed by analyzing the received data. The active signal is assumed to contain less information than the actual message signal. Thus, even if it is sufficient to detect a signal, the reception request may be low. This can be accomplished using a few A / D channels or one A / D channel. As mentioned above, the precision of the A / D channel can also be reduced.

According to the invention, the analog / digital converter must be used intelligently in the second situation. Specifications available for signal and noise are used as a reference for the number of channels that should be used. It is assumed that the demand is lower in this respect than in terms of the overall operation. When more than one tone is detected, it will be impossible to detect the tone in a single way. Aliasing changes the frequency display on the output of the A / D converter. The parallel analog / digital converter takes samples at time points n / fs, where n is an integer and fs is the effective sampling frequency for the parallel analog / digital converter. Each channel takes a sample at time spacing m / fs, where m is the number of channels. Thus, the sampling frequency for each channel is fs / m. The time control unit determines when several channels take their respective samples. If the sample is assumed to spread evenly in time, the first channel takes its sample at time m × n / fs and the second channel takes its sample at time (m × n + m-1) / fs. Take it. Depending on Nyquist, the analog frequency is unique in the time discrete representation arriving from the analog / digital converter for up to a half sampling frequency. The frequency indication is not unique when a channel is switched off, but the analog frequency at which the digital indication is obtained is known.

In the case where the analog / digital converter waits to detect a signal outside the frequency band that can only be displayed, whether or not it is possible to assume whether the received tone is correct can be obtained from the sampled value. The correct frequency indicates that it is possible to clearly detect a tone of 10 MHz, for example when fs is 44 MHz and the tone is 10 MHz and all the allowed input signals to the ADC are within the frequency band 0-22 MHz. If three of the four A / D channels are cut off, the effective sampling frequency is changed to 11 MHz. According to the Nyquist sampling theory, tones with frequencies 1 MHz, 10 MHz, 12 MHz and 21 MHz have the same appearance in the output data of the A / D converter.

When it is known from the system specification that the tone is a narrowband tone and a tone other than the wake up tone cannot be transmitted, the tone can be detected significantly.

In case of doubt, it is necessary to activate the analog / digital converter to clearly determine what is received.

In the third situation, if the message is a narrowband message, due to the fact that the frequency indication is unique even with the low precision of the A / D converter, the message can be detected without fully activating the analog / digital converter. When the message is a wideband message, it is necessary to activate the entire analog / digital converter.

By completely blocking the supply current to one or more A / D channels and by switching off one or more switches 30, 32, 34 and 36, the channels can be switched off and thus energy is saved.

An alternative method is to switch off the circuit clock. In the case where the clock is static, it is sufficient to switch off the clock, and even when the clock includes the dynamic mode, it is often advantageous to switch off the voltage source via switches 30, 32, 34 and 36. The problem with dynamic mode is that the logic value persists with the help of the capacitor's charge. This charge can be shorted over time. The charge is generally updated with each clock period. A charge leakage of 10% does not have any significant effect because it is possible to distinguish between logic 1 and logic 0. However, a large amount of electric charge may leak when the clock is switched off for a long time. If the dynamic mode is the input to the inverter and the potential reaches somewhere between ground and the supply voltage, a short circuit may occur through the inverter due to the passage of large currents through it.

Logical blocks (gates) in the CMOS, the inverter generally includes two transistors. When the inverter input is connected to ground, one of the transistors is in a conductive state, but when the inverter input is connected to a power supply voltage, another transistor is in a conductive state. The transistors can all be in a conductive state between the voltages between them, ie, the ground and power supply voltages.

Analog parts of the A / D channels, for example comparators and operational amplifiers, often have control signals that control, for example, standing or quiescent currents. This control signal can be used to switch off the analog portion of the A / D channel.                 

For practical reasons it is conceivable to switch off only the main part of the circuit. As shown in FIG. 2, it is also conceivable to include a common sample and hold unit.

Claims (12)

In parallel analog-to-digital converters (ADCs), Two or more A / D channels, each of which has an analog input signal converted to a digital output signal and includes respective signal inputs and signal outputs on the A / D channels coupled to the sample and hold units, A multiplexing unit comprising at least two inputs and outputs coupled to the outputs of the A / D channels, respectively; A time control unit for clocking the computation channel and controlling the multiplexing unit, Said parallel analog / digital converter is provided with means for switching between a so-called idle mode and a so-called normal mode. The method of claim 1, The A / D channel is switched off completely or partially in the idle mode of the converter. The method of claim 1, And the clock frequency of said time control unit is lowered in idle mode. The method of claim 2, And the current into the A / D channel is completely switched off. The method according to any one of claims 1 to 4, The A / D channel of the analog / digital converter detects an active signal and switches the analog / digital converter from an idle mode to a normal mode. The method according to claim 1 or 4, And said analog / digital converter switches to an idle mode after a predetermined signal absence time in said A / D channel. In the parallel analog / digital conversion method, Converting an analog input signal into a digital output signal with the aid of two or more A / D channels including signal inputs and signal outputs on the A / D channels respectively coupled to the sample and hold units, Multiplexing the digital output signals from each A / D channel together in a multiplexing unit, and Clocking and controlling the A / D channel and the multiplexing unit with the aid of a time control unit, Switching said analog / digital converter between a so-called idle mode and a so-called normal mode. The method of claim 7, wherein Switching off the A / D channel completely or partially in idle mode. The method of claim 7, wherein Lowering the clock frequency of the time control unit in the idle mode. The method of claim 9, And completely switching off the current to the A / D channel. The method according to any one of claims 7 to 10, Detecting an active signal by the A / D channel of the analog / digital converter and switching the analog / digital converter from an idle mode to a normal mode. The method according to any one of claims 7 to 10, Switching a digital converter from a normal mode to an idle mode when a period of any signal absence appears in the A / D channel.

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