KR100886707B1 - Semiconductor device and logic gate included the same - Google Patents

Abstract

The present invention relates to MOS transistors having a finger structure connected in series provided in a semiconductor device and a logic gate including the MOS transistors. The present invention relates to a first MOS transistor having a common gate, a common drain, and a source separated from each other. Transistor group; And a second MOS transistor group having a common gate, a common source, and drains separated from each other; wherein a source of each of the first MOS transistors and a drain of each of the second MOS transistors are connected in a one-to-one correspondence. It is done.

Description

Semiconductor device and logic gate provided therein {SEMICONDUCTOR DEVICE AND LOGIC GATE INCLUDED THE SAME}

1 is a circuit diagram showing a general NAND gate.

FIG. 2 is a circuit diagram illustrating a conventional NAND gate where two NMOS transistors N1 and N2 of FIG. 1 are fingered.

3 illustrates a layout structure of the fingered NMOS transistors N01, N02, N11, and N12 of FIG.

4 is a circuit diagram illustrating a conventional NAND gate in which four NMOS transistors N1 and N2 of FIG. 1 are fingered.

FIG. 5 illustrates a layout structure of the fingered NMOS transistors N21, N22, N23, N24, N31, N32, N33, and N34 of FIG. 4.

FIG. 6 is a circuit diagram illustrating a NAND gate of the present invention in which the NMOS transistors N1 and N2 of FIG. 1 are each fingered. FIG.

FIG. 7 illustrates a layout structure of the fingered NMOS transistors N41, N42, N51, and N52 of FIG. 6.

FIG. 8 is a circuit diagram illustrating a NAND gate of the present invention in which the NMOS transistors N1 and N2 of FIG. 1 are each fingered.

9 is a diagram illustrating a layout structure of the fingered NMOS transistors N61, N62, N63, N64, N71, N72, N73, and N74 of FIG. 8.

FIG. 10 is a resistance equivalent circuit diagram of the fingered NMOS transistors N21, N22, N23, N24, N31, N32, N33, and N34 of FIG. 4.

FIG. 11 is a resistance equivalent circuit diagram of the fingered NMOS transistors N61, N62, N63, N64, N71, N72, N73, N74 of FIG.

The present invention relates to a semiconductor device, and more particularly, to a MOS transistor having a finger structure connected in series provided in the semiconductor device, and a logic gate including the MOS transistors.

In general, a MOS transistor used in a semiconductor device has a finger structure when the size is large. For example, as illustrated in FIG. 1, in the case of a NAND gate outputting an output signal OUT by NAND combining two input signals IN1 and IN2, two PMOS transistors P1 and P2 constituting the NAND gate and two yen When the size of the MOS transistors N1 and N2 is large, fingering occurs in each of the MOS transistors P1, P2, N1, and N2.

In this case, when MOS transistors connected in series are conventionally fingered, each MOS transistor is divided by the number of fingers, and the connection between two adjacent fingered transistors is made through one node.

That is, when two NMOS transistors N1 and N2 connected in series of FIG. 1 are fingered by two NMOS transistors N01 and N02 and two NMOS transistors N11 and N12 as shown in FIG. NMOS transistors N01 and N02 are connected to two NMOS transistors N11 and N12 through one node ND1.

Referring to FIG. 3, a layout structure of two NMOS transistors N01 and N02 and two NMOS transistors N11 and N12 having a finger structure is described as a drain (or source) region of two NMOS transistors N01 and N02. One metal line corresponding to the node ND1 is electrically connected to the drain (or source) regions of the two NMOS transistors N11 and N12.

In addition, when two NMOS transistors N1 and N2 are fingered into four NMOS transistors N21, N22, N23 and N24 and four NMOS transistors N31, N32, N33 and N34 as shown in FIG. The NMOS transistors N21, N22, N23, and N24 are connected to four NMOS transistors N31, N32, N33, and N34 through one node ND2.

Similarly, a layout structure of four NMOS transistors N21, N22, N23 and N24 and four NMOS transistors N31, N32, N33 and N34 having a finger structure will be described with reference to FIG. 5. The drain (or source) regions of N22, N23, and N24 are electrically connected to the drain (or source) regions of the two NMOS transistors N11 and N12 through one metal line corresponding to the node ND2.

As such, the MOS transistors connected in series are conventionally fingered by the number of fingers, and the MOS transistor groups of two adjacent finger structures are connected to each other through one node.

However, when the MOS transistors connected in series are fingered and connected to one node as in the related art, as shown in the dotted lines of FIGS. 3 and 5, a metal line, that is, a node ( Since the lengths of the ND1 and ND2 become long, there is a problem in that the output loading becomes long corresponding to the length of the nodes ND1 and ND2.

An object of the present invention is to reduce the signal loading generated when the MOS transistors of the finger structure is connected in series.

In accordance with an aspect of the present invention, there is provided a semiconductor device comprising: a first MOS transistor group having a common gate, a common drain, and a source structure in which a source is separated from each other; And a second MOS transistor group having a common gate, a common source, and drains separated from each other; wherein a source of each of the first MOS transistors and a drain of each of the second MOS transistors are connected in a one-to-one correspondence. It is done.

The first and second MOS transistors are preferably NMOS transistors, respectively.

According to an aspect of the present invention, a logic gate according to an aspect of the present invention provides a logic combination of a first and a second input signal to an output node, one end of which is commonly connected to the output node, and the other end of the logic gate. A first MOS transistor group of separated finger structures; And a second MOS transistor group having a finger structure, one end of which is commonly connected to a predetermined voltage line, and the other end of which is connected one-to-one to the other end of each of the first MOS transistors. The first input signal is commonly input, and the second MOS transistor group is characterized in that the second input signal is commonly input to a gate.

Here, each of the first and second MOS transistors is preferably an NMOS transistor, and the voltage line is preferably a ground voltage line. Alternatively, each of the first and second MOS transistors is preferably a PMOS transistor, and the voltage line is preferably a power supply voltage line.

In accordance with another aspect of the present invention, a semiconductor device includes: an active region; At least two first gates disposed in the active region in a finger structure and commonly connected to a first metal line; And at least two or more second gates disposed in the active region in parallel with the first gates and connected to a second metal line in common, wherein both sides of each of the gates in the active region The contact region may be divided into a non-contact region, and the non-contact region may be electrically connected between the transistor including the first gate and the transistor including the second gate.

Preferably, the contact region is a source region in which a contact is formed, and the non-contact region is a drain region in which no contact is formed.

The first gates are arranged in pairs, and contact regions are disposed between the pair of first gates, respectively.

Here, the second gates are disposed on both sides of the pair of first gates one by one, and a non-contact area is disposed on one side of the second gate in the first gate direction with respect to the second gate, respectively. Preferably, contact regions are disposed on the other side of the second gate in the active region.

When at least two pairs of the first gates are disposed, a pair of the second gates are disposed between the two pairs of first gates, and contact regions are respectively formed in the region between the pair of second gates. Preferably disposed.

According to another aspect of the present invention, there is provided a logic gate, including a logic combination of a signal transmitted to a first input line and a signal transmitted to a second input line, and outputting an output line to an output line; At least two first gates disposed in the active region in a finger structure and commonly connected to the first input line; And at least two or more second gates disposed in the active region in parallel with the first gates and connected to the second input line in common, wherein both sides of each gate in the active region are included. Is divided into a contact region and a non-contact region, wherein the contact region adjacent to the first gate is commonly connected to the output line, and the contact region adjacent to the second gate is commonly connected to a predetermined voltage line. .

Preferably, the contact region is a source region in which a contact is formed, and the non-contact region is a drain region in which no contact is formed.

In addition, the first gates are disposed in pairs, and contact regions are disposed between the pair of first gates, respectively.

Here, the second gates are disposed one outside of the pair of first gates, and a non-contact region is disposed between the first gate and the second gate, respectively, and the outside of the second gate in the active region. Preferably, contact regions are disposed in the regions.

When at least two pairs of the first gates are disposed, a pair of the second gates are disposed between the two pairs of first gates, and contact regions are respectively formed in the region between the pair of second gates. Preferably disposed.

On the other hand, the voltage line is preferably a ground voltage line.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention has a structure in which MOS transistors of a finger structure are connected in series, and MOS transistors sharing a drain (or source) are connected in series in a one-to-one correspondence.

Specifically, referring to the NAND gate of FIG. 1 as an example, when two NMOS transistors N1 and N2 connected in series are each fingered, the present invention has a structure as shown in FIG. 6.

That is, the semiconductor device of the present invention includes two PMOS transistors P1 and P2 and four NMOS transistors N41, N42, N51, and N52 having a finger structure, as shown in FIG. 6. .

The PMOS transistor P1 pulls up the output signal OUT to the power supply voltage level in response to the input signal IN1, and the PMOS transistor P2 pulls up the output signal OUT to the power supply voltage level in response to the input signal IN2.

The four NMOS transistors N41, N42, N51, and N52 of the finger structure pull down the output signal OUT to the ground voltage level in response to the two input signals IN1 and IN2.

Here, the gates of the two NMOS transistors N41 and N42 having the finger structure are commonly inputted with the input signal IN1, and the source (or drain) of the two NMOS transistors N41 and N42 are commonly connected to the output node. The drains (or sources) 60 of the two NMOS transistors N41 and N42 are connected in one-to-one correspondence to the drains (or sources) 60 of the two NMOS transistors N51 and N52, respectively.

In addition, the gates of the two NMOS transistors N51 and N52 of the finger structure are commonly inputted with the input signal IN2, and the source (or drain) of the two NMOS transistors N51 and N52 is common to the ground voltage line GND. The drains (or sources) 60 of the two NMOS transistors N51 and N52 are connected to the drains (or sources) 60 of the two NMOS transistors N41 and N42, respectively.

In the semiconductor device of the present invention having the above structure, the four NMOS transistors N41, N42, N51, and N52 having the finger structure may be laid out as shown in FIG. 7.

Referring to FIG. 7, the gates of the two NMOS transistors N41 and N42 and the gates of the two NMOS transistors N51 and N52 are respectively disposed in the active region 70. Here, the gates of the two NMOS transistors N41 and N42 are disposed in parallel and adjacent to each other, the gate of the NMOS transistor N51 is disposed in parallel to one side of the gate of the NMOS transistor N41, and the NMOS transistor The gate of N52 is disposed in parallel to one side of the gate of the NMOS transistor N42.

The gates of the two NMOS transistors N41 and N42 are commonly connected to the gate pad 72, and the gate pad 72 is electrically connected to the metal line through which the input signal IN1 is transmitted through the contacts CNTs. .

In addition, the gates of the two NMOS transistors N51 and N52 are commonly connected to the gate pad 74, and the gate pad 74 is electrically connected to the metal line through which the input signal IN2 is transmitted through the contacts CNTs. .

On the other hand, both sides of the gate of each of the NMOS transistors N41, N42, N51, and N52 in the active region 70 are divided into a contact region and a non-contact region 60. Here, the contact region is a source (or drain) region in which a plurality of contacts CNTs are formed, and the non-contact region 60 refers to a drain (or source) region in which no contact is formed.

In addition, a contact region disposed between the gates of the two NMOS transistors N41 and N42, that is, a source (or drain) region of the two NMOS transistors N41 and N42 is connected to the output signal OUT through the contacts CNTs. Is electrically connected to the output metal line.

In addition, the source (or drain) of the contact region disposed on one side of the gate of the NMOS transistor N51 and the contact region disposed on one side of the gate of the NMOS transistor N52, that is, the two NMOS transistors N51 and N52. ) Region is electrically connected to ground voltage line GND via contacts CNT.

As can be seen from the layout of FIG. 7, the two NMOS transistors N41 and N42 and the two NMOS transistors N51 and N52 are connected to each other by sharing the drain (or source) region 60 without a metal line, respectively. There is an effect that the loading of the metal line corresponding to the node (ND1), such as the dotted line of FIG.

Similarly, in the NAND gate of FIG. 1, when two NMOS transistors N1 and N2 connected in series are each fingered by four, the present invention has the structure as shown in FIG. 8.

Specifically, the semiconductor device of the present invention is another embodiment, as shown in FIG. 8, two PMOS transistors P1 and P2 and eight NMOS transistors N61, N62, N63, N64, and N71 having a finger structure. , N72, N73, N74).

Here, the gates of the four NMOS transistors N61, N62, N63, and N64 of the finger structure are commonly inputted with the input signal IN1, and the source (or drain) of the four NMOS transistors N61, N62, N63, and N64 is Commonly connected to the output node, the drain (or source) of the four NMOS transistors N61, N62, N63, and N64 are one-to-one to the drain (or source) of the four NMOS transistors N71, N72, N73, and N74, respectively. Correspondingly, connection 80 is made.

In addition, the gates of the four NMOS transistors N71, N72, N73, and N74 of the finger structure receive the input signal IN2 in common, and the source (or drain) of the four NMOS transistors N71, N72, N73, and N74 is The drain (or source) of the four NMOS transistors N71, N72, N73, and N74 is commonly connected to the ground voltage line GND, and the drain (or source) of the four NMOS transistors N61, N62, N63, and N64. ) Are connected one-to-one to each other (80).

In the semiconductor device of the present invention having the above structure, eight NMOS transistors N61, N62, N63, N64, N71, N72, N73, and N74 having a finger structure may be laid out as illustrated in FIG. 9.

9, gates of four NMOS transistors N61, N62, N63, and N64 and gates of four NMOS transistors N71, N72, N73, and N74 are respectively arranged in the active region 90 in a finger structure. .

Here, the gates of the two NMOS transistors N61 and N62 are disposed in parallel and adjacent to each other, and the gates of the two NMOS transistors N63 and N64 are disposed in parallel and adjacent to each other. The gates of the two NMOS transistors N72 and N73 are disposed in parallel to each other between the gates of the two NMOS transistors N62 and N63. In addition, the gate of the NMOS transistor N71 is disposed in parallel to one side of the NMOS transistor N61, and the gate of the NMOS transistor N74 is disposed in parallel to one side of the NMOS transistor N64.

In addition, the gates of the four NMOS transistors N61, N62, N63, and N64 are commonly connected to the gate pad 92, and the gate pad 92 may include a metal line through which the input signal IN1 is transmitted through the contacts CNT. Electrically connected.

In addition, the gates of the four NMOS transistors N71, N72, N73, and N74 are commonly connected to the gate pad 94, and the gate pad 94 may include a metal line through which the input signal IN2 is transmitted through the contacts CNT. Electrically connected.

In the active region 90, both sides of the gates of the NMOS transistors N61, N62, N63, N64, N71, N72, N73, and N74 are divided into a contact region and a non-contact region 80. Here, the contact region is a source (or drain) region in which a plurality of contacts CNTs are formed, and the non-contact region 80 refers to a drain (or source) region in which no contact is formed.

The contact region disposed between the gates of the two NMOS transistors N61 and N62 and the contact region disposed between the gates of the two NMOS transistors N63 and N64, that is, the four NMOS transistors N61, N62 and N63. The source (or drain) region of N64 is electrically connected to the metal line through which the output signal OUT is output through the contacts CNTs.

Further, a contact region disposed between the gates of the two NMOS transistors N72 and N73, a contact region disposed on one side of the gate of the NMOS transistor N71, and one side of the gate of the NMOS transistor N74. The contact region, that is, the source (or drain) region of the four NMOS transistors N71, N72, N73, and N74 is electrically connected to the ground voltage line GND through the contacts CNTs.

Similarly, as can be seen in the layout of FIG. 9, the four NMOS transistors N61, N62, N63, N64 and the four NMOS transistors N71, N72, N73, N74 have a drain (or source) region 80 without a metal line. ) Are connected to each other by sharing each other, so that the loading of the metal line corresponding to the node ND2 as in the dotted line of FIG. 5 is eliminated.

As described above, in the semiconductor device of the present invention, when the MOS transistors connected in series are fingered, each MOS transistor is fingered by a MOS transistor of a plurality of finger structures, and the MOS transistors of two adjacent finger structures each have a drain ( Or a source).

The semiconductor device of the present invention having such a structure has the same operating characteristics as in the prior art. For example, comparing the resistance values between the output node and the ground voltage line GND in FIGS. 4 and 8 is as follows.

The conventional output node of FIG. 4 has four resistors R21, R22, R23, and R24 connected in parallel between the output node and the node ND2, and the node ND2 and the ground voltage line GND, as shown in FIG. The resistances are equal to four resistors (R31, R32, R33, and R34) connected in parallel. Here, the four resistors R21, R22, R23, and R24 correspond to the turn-on resistors of the four NMOS transistors N21, N22, N23, and N24 of FIG. 4, respectively, and the four resistors R31, R32, R33, and R34. Corresponds to the turn-on resistors of the four NMOS transistors N31, N32, N33, and N34 of FIG.

Assuming that the resistors R21, R22, R23, R24, R31, R32, R33, and R34 all have the same resistance value, the resistance value between the output node and the node ND2 becomes 'R / 4'. The resistance value between the node ND2 and the ground voltage line GND becomes 'R / 4'. Therefore, the resistance value between the output node and the ground voltage line GND becomes 'R / 2'.

In addition, as shown in FIG. 11, the output node of FIG. 8, which is another embodiment of the present invention, includes resistor chains R61, R71, R62, R72, R63, R73, and R64 between the output node and the ground voltage line GND. R74 has the same resistance value as connected in parallel. Here, the four resistors R61, R62, R63, and R64 correspond to the turn-on resistors of the four NMOS transistors N61, N62, N63, and N64 of FIG. 8, respectively, and the four resistors R71, R72, R73, and R74. Corresponds to the turn-on resistors of the four NMOS transistors N71, N72, N73, and N74 of FIG.

Similarly, assuming that the resistors R61, R62, R63, R64, R71, R72, R73, R74 all have the same resistance value, the resistance value between the output node and the ground voltage line GND is' R /. 2 '.

As described above, since the resistance values between the output node and the ground voltage line GND of FIGS. 4 and 8 are the same, FIGS. 4 and 8 are equivalent circuits. However, in terms of layout, since the loading generated by the node ND2 of FIG. 5 is eliminated as shown in FIG. 9 of the present invention, the loading is reduced compared to the conventional art.

7 and 9, since the ground voltage is supplied to the source (or drain) region of '(finger number) / 2 + 1', the surface of the semiconductor device of the present invention is superior to the conventional voltage supply surface. The output is also generated by '(finger number) / 2', so that the output characteristics can be enhanced.

The present invention is applicable to various circuits in which series MOS transistors as well as the NAND gates described above are used. For example, in the case of a NOR gate in which PMOS transistors are connected in series, the same effect may be obtained when PMOS transistors sharing a source (or drain) are connected in a one-to-one correspondence when the PMOS transistors are fingered.

As described above, when the MOS transistors connected in series have a finger structure, the MOS transistors sharing a drain (or source) are connected in series in a one-to-one correspondence, thereby reducing the output load due to the connection between transistors, thereby reducing circuit characteristics. There is an effect that can be prevented.

In addition, the present invention has the effect that the voltage supply can be enhanced and the output characteristics can be improved because the MOS transistor of the finger structure receives voltage in more paths and generates outputs in more paths corresponding to the number of fingers.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (18)

delete delete A logic gate for logically combining the first and second input signals to output to an output node, A first MOS transistor group having a finger structure, one end of which is commonly connected to the output node and the other end of which is separated from each other; And A second MOS transistor group having a finger structure, one end of which is commonly connected to a predetermined voltage line and the other end of which is connected one-to-one to the other end of each of the first MOS transistors. And the first MOS transistor group receives a common input of the first input signal through a gate, and the second MOS transistor group receives a common input of the second input signal through a gate. The method of claim 3, wherein Each of the first and second MOS transistors is an NMOS transistor. The method of claim 4, wherein And the voltage line is a ground voltage line. The method of claim 3, wherein Wherein each of the first and second MOS transistors is a PMOS transistor. The method of claim 6, And the voltage line is a power supply voltage line. Active area; At least two first gates disposed in the active region in a finger structure and commonly connected to a first metal line; And At least two or more second gates disposed in the active region in parallel with the first gates and connected to a second metal line in common; Both sides of the gate are divided into a contact region and a non-contact region in the active region, and a transistor including the first gate and a transistor including the second gate are electrically connected through the non-contact region. A semiconductor device, characterized in that. The method of claim 8, And the contact region is a source region where a contact is formed, and the non-contact region is a drain region where no contact is formed. The method of claim 8, And the first gates are arranged in pairs, and contact regions are disposed between the pair of first gates, respectively. The method of claim 10, The second gates are disposed on both sides of the pair of first gates, and non-contact regions are disposed on one side of the second gate in the first gate direction with respect to the second gate, respectively, and the active region And a contact region is disposed on the other side of the second gate in each other. The method of claim 11, When at least two pairs of the first gates are disposed, a pair of the second gates are disposed between the two pairs of first gates, and contact regions are respectively formed in the region between the pair of second gates. A semiconductor device, characterized in that arranged. A logic gate for logically combining a signal transmitted to a first input line and a signal transmitted to a second input line to output to an output line, Active area; At least two first gates disposed in the active region in a finger structure and commonly connected to the first input line; And At least two second gates disposed in the active region in parallel with the first gates and connected to the second input line in common; Both sides of the gate are respectively divided into a contact region and a non-contact region in the active region, a contact region adjacent to the first gate is commonly connected to the output line, and a contact region adjacent to the second gate is predetermined. Logic gate, characterized in that commonly connected to the voltage line. The method of claim 13, And the contact region is a source region where a contact is formed, and the non-contact region is a drain region where no contact is formed. The method of claim 13, And the first gates are arranged in pairs, and contact regions are respectively disposed between the pair of first gates. The method of claim 15, The second gates are disposed one outside of the pair of first gates, and non-contact regions are disposed between the first gate and the second gate, respectively, and in the outer region of the second gate in the active region. Logic gates, each contact region being disposed. The method of claim 16, When at least two pairs of the first gates are disposed, a pair of the second gates are disposed between the two pairs of first gates, and contact regions are respectively formed in the region between the pair of second gates. Logic gates, characterized in that arranged. The method of claim 13, And the voltage line is a ground voltage line.

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